KR20130036501A - Power mosfet having superjunction trench and fabrication method thereof - Google Patents

Abstract

PURPOSE: A power MOSFET with a superjunction trench structure and a manufacturing method thereof are provided to reduce an on-resistance by filling a deep trench with p-type doped conductive materials to form a p-type pillar layer. CONSTITUTION: Second conductive type first pillar layers are horizontally separated in a drain region and are filled with conductive materials in a vertical trench. A second conductive type base region is formed around each first pillar layer with a preset depth. A second conductive type contact region(46) is narrower and deeper than a source region around the first pillar layers in the base region. The junction depth of the second conductive type contact region is shallower than the junction depth of the base region. A gate electrode(70) is formed in a second pillar layer, two base regions, and two source regions by interposing a gate insulation layer. A source electrode(80) is contacted with the source region exposed to both sides of the gate electrode, the contact region, and each upper side of the first pillar layers.

Description

Power MOSFET having superjunction trench structure and manufacturing method thereof {POWER MOSFET HAVING SUPERJUNCTION TRENCH AND FABRICATION METHOD THEREOF}

The present invention relates to a power semiconductor device, and more particularly, to a structure of a power MOSFET and a method of manufacturing the same.

Power MOSFET is a power switching device using MOSFET, low on-resistance (Ron) and high breakdown voltage (BV) is required.

In general planar MOSFET structure, in order to lower the on-resistance, it is necessary to increase the concentration of epi layer, which is the current path, or to decrease the thickness thereof. In this case, the breakdown voltage (BV) decreases, so that the trade-off relationship between the two Relationship has been difficult to do both.

In order to solve such a problem, a power MOSFET having a superjunction structure as shown in FIG. 1 has been proposed (see Patent Document 1). According to this, the N + pillar layer 171 serving as the current path and the P + pillar layer 172 for maintaining reverse pressure resistance between the source and the drain are formed in the depth direction (vertical direction), and the on-resistance is the N + pillar layer ( At the concentration of 171, the internal pressure is determined by the concentration and the width of the N + pillar layer 171 and the P + pillar layer 172, since the depletion layer extends in the horizontal direction, and the reverse internal pressure between the source and the drain (for example, 600V) and There is an advantage that the on-resistance can be improved simultaneously (for example, the on-resistance is reduced to about 1/3 to 1/4).

By the way, as shown in FIG. 1, the cool moth repeatedly performs a photo process and P + ion implantation to grow an N + epitaxial layer on the semiconductor substrate 173 and form a P + pillar (No. 6 in FIG. 1). To prolong the high temperature for a long time to form a superjunction P + pillar layer 172, the process is complicated and must proceed according to a long process, there is a problem that the manufacturing cost and time is increased to increase the manufacturing cost.

Reference numeral 174 in FIG. 1 denotes an N ++ source region, 175 a gate electrode, and 176 an insulating film.

In order to solve the manufacturing problems of the cool moss, a power MOSFET having a NPN pillar structure in which a deep trench is formed in the source electrode portion as shown in FIG. 2 and N + ion implantation and P + ion implantation are formed in the trench sidewalls is proposed. (See Patent Document 1).

This leads to N- epitaxial growth, deep trench formation, NPN pillars 183 and 184 formed by co-injection and thermal diffusion of B ions and As ions, and formation of device isolation regions 185 by trench filling. Since the process is completed relatively short, there is an advantage that can lower the manufacturing cost than the kulmos.

However, the NPN pillar structure disclosed in Patent Document 1 utilizes the diffusion rate of B ions larger than As ions, and simultaneously injects B ions and As ions after forming a deep trench and thermally diffuses them to a high temperature so as to make NPN pillars 183 and 184. To simultaneously form, the problem of not being able to accurately control the concentration of the N + pillar layer 184 and P + pillar layer 183, and as disclosed in Patent Literature 1, the process of thermal diffusion for at least 2000 minutes at a high temperature of 1150 ℃ This is a necessary problem.

In FIG. 2, reference numeral 180 denotes an N ++ substrate, 183a denotes a P + base region, 186 denotes an N + source region, 187 denotes a gate oxide film, 188 denotes a gate electrode, and 190 denotes a source metal wiring.

3, a superjunction power MOSFET in which a trench 116 having a predetermined depth is formed in the N-type semiconductor substrate 119 to form the P-pillar layer 104 and the P + contact layer 107 by ion implantation. This patent document 2 was disclosed.

This is an advantage that the epitaxial process and the deep trench process are not required, respectively, compared to the structures of FIGS. 1 and 2, but in order to form the P-pillar layer 104, ion implantation and thermal diffusion processes are performed, in this case, lateral diffusion. 3, it is not easy to form the P-pillar layer 104 vertically down as shown in FIG. 3, and it is difficult to form the N + drain region 102, so that the source electrode 110, the trench contact 117, and the P + contact are formed. Through the layer 107 and the P-pillar layer 104, there is a problem in that holes generated in the N-pillar layer 103, which is a current path, are difficult to be properly pulled out. That is, there is a certain limit to reducing the on resistance (Ron).

In FIG. 3, reference numeral 101 denotes a drain electrode, 105 denotes a P-base layer, 106 denotes an N-source layer, 108 denotes a gate insulating layer, and 109 denotes a gate electrode.

Patent Document 1: Korean Patent No. 10-0418972, 2004. 2. 14. Patent Document 2: US Patent No. 7,605,426, Oct. 20, 2009.

The present invention has been proposed to solve the above problems of the prior art, by forming a P-type pillar layer by filling a deep trench with a conductive material, such as a semiconductor material doped with a P-type, the process is simple, high pressure resistance ( It is an object of the present invention to provide a power MOSFET having a superjunction trench structure capable of reducing on-resistance (Ron) as well as a chip size, and a method of manufacturing the same.

In order to achieve the above object, the power MOSFET having a superjunction trench structure according to the present invention comprises a first conductive drain region formed in horizontal contact with the drain electrode at the bottom; Two second conductive first pillar layers filled with a conductive material in a trench vertically spaced horizontally and vertically spaced on the drain region; A second conductive base region formed to a predetermined depth around each of the first pillar layers; A first conductive source region formed around the upper portion of the first pillar layer in the base region and having a smaller junction depth than the base region; A second conductive contact region formed in the base region around the first pillar layer and having a smaller width and a larger bonding depth than the source region and a smaller bonding depth than the base region; A second conductive diffusion region formed around the first pillar layer below the base region; A first conductive second pillar layer formed between the first conductive diffusion region and the base region between the first pillar layers on the drain region; A gate electrode formed on the second pillar layer, two base regions formed on both sides of the second pillar layer, and two source regions with a gate insulating film interposed therebetween; And a source electrode formed between the insulating layer on the gate electrode and in contact with the upper surface of the source region, the contact region, and the first pillar layer exposed to both sides of the gate electrode.

Here, a second trench is formed in the upper portion of the second pillar layer to have a side contact with the source region and the base region, and a second gate insulating layer is formed on the inner wall of the second trench. The gate electrode may be formed on the gate insulating film.

On the other hand, the method of manufacturing a power MOSFET having a superjunction trench structure according to the present invention includes a first step of growing an epitaxial layer of a first conductive type on a semiconductor substrate having a first conductive type; A second step of forming an etch mask horizontally on the epitaxial layer and etching the epitaxial layer to form a trench of a predetermined depth vertically; Filling the trench with a conductive material and planarizing the exposed epitaxial layer to form a first pillar layer of a second conductivity type; A fourth step of sequentially forming a gate insulating film and a gate electrode on the epitaxial layer exposed between the first pillar layers; A fifth step of forming a base region of a second conductivity type, a source region of a first conductivity type, and a contact region of a second conductivity type in the epi layer around the first pillar layer by an ion implantation and thermal diffusion process; Forming a source electrode to contact the source region, the contact region, and the first pillar layer; And a seventh step of forming a drain region of the first conductivity type by grinding a predetermined thickness of the back surface of the semiconductor substrate and implanting ions into the back surface, and forming a drain electrode under the drain region.

Forming a etch mask horizontally on the semiconductor substrate having the first conductivity type horizontally and etching the semiconductor substrate to form a trench of a predetermined depth vertically; Filling the trench with a conductive material, grinding the bottom of the semiconductor substrate to expose the trench, and then bonding a second semiconductor substrate having a first conductivity type; Etching the conductive material and removing the etching mask to form a first pillar layer of a second conductive type; A fourth step of sequentially forming a gate insulating film and a gate electrode on an active region of the semiconductor substrate exposed between the first pillar layers; Forming a base region of a second conductivity type, a source region of a first conductivity type, and a contact region of a second conductivity type in the active region around the first pillar layer by an ion implantation and thermal diffusion process; Forming a source electrode to contact the source region, the contact region, and the first pillar layer; And a seventh step of forming a drain region of the first conductive type by grinding a predetermined thickness of the back surface of the second semiconductor substrate and implanting ions into the back surface, and forming a drain electrode under the drain region. .

The present invention forms a trench in a first conductive epitaxial layer or a semiconductor substrate, and fills a conductive material such as a semiconductor material doped with a second conductive type, and then, by a simple diffusion process, a first pillar layer (eg, a P-type pillar layer). By forming the second pillar layer (e.g., N-type pillar) which is a current path, the process is much simpler than that of a power MOSFET having a cooler structure, and the formation of the first pillar layer (for example, P-type pillar layer) can be controlled. To reduce the on-resistance (Ron) by effectively discharging the minority carriers (e.g. holes) generated in the layer) and to form a depletion layer on the side of the first pillar layer (e.g., P-type pillar layer). It is possible to reduce the size of the chip as well as possible.

1 is a cross-sectional view showing a conventional cool moss structure.
2 is a cross-sectional view illustrating a structure of a power MOSFET having an NPN pillar structure divided into a device isolation region filled with an insulating material in a conventional deep trench.
3 is a cross-sectional view showing a structure of a power MOSFET having a conventional P- pillar layer and a P + contact layer.
4 to 8 is a cross-sectional view showing a method of manufacturing a power MOSFET according to an embodiment of the present invention.
9 to 12 are cross-sectional views showing the structure of a power MOSFET according to another embodiment of the present invention.
13 to 16 is a cross-sectional view showing a method for manufacturing a power MOSFET according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[Structure Example ]

The power MOSFET according to the present invention basically has a first conductive type (eg, N-type) drain region formed horizontally in contact with the drain electrode 90 at the bottom, as commonly expressed in FIGS. 8 to 12 and 16. 10a; Two agents filled with a conductive material such as a semiconductor material (eg, polysilicon) doped with a second conductive (eg, P-type) impurity in a trench 40a vertically spaced apart from each other by a horizontal distance on the drain region. Two conductive first pillar layers 40; Second conductive base regions (44; 44a) formed to a predetermined depth around each of the first pillar layers; A first conductive source region 50 formed around the upper portion of the first pillar layer in the base region and having a smaller bonding depth than the base region; A second conductive contact region 46 formed around the upper portion of the first pillar layer in the base region, the width of which is smaller than that of the source region, and the bonding depth is smaller than that of the base region; A second conductive diffusion region (42; 42a) formed around the first pillar layer below the base region; First conductive second pillar layers 22; 12 and 22a formed between the first conductive diffusion regions 42 and 42a and the base regions 44 and 44a on the drain region between the first pillar layers. ); Gate electrodes 70 and 72 formed on the second pillar layer, two base regions formed on both sides of the second pillar layer, and two source regions with gate insulating layers 60 and 61 interposed therebetween; And an insulating layer 62 disposed on the gate electrode so as to be in contact with each upper surface of the source region 50, the contact region 46, and the first pillar layer 40 exposed to both sides of the gate electrode. Characterized in that it comprises a formed source electrode (80).

In this manner, when a turn-on voltage is applied to the gate electrodes 70 and 72, the inversion layer is formed on both base regions 44 and 44a in contact with the gate insulating layers 60 and 61. Channel is formed to generate a current path to both source electrodes 80-> second pillar layers 22; 12 and 22a-> drain electrode 90. The second pillar layers 22; By adjusting the doping concentration and the first pillar layer 40, it is possible to effectively remove the minority carriers (eg, holes) generated in the second pillar layers 22; 12 and 22a, thereby lowering the on resistance Ron as much as possible. .

In addition, the voltage applied to the source electrode 80 and the drain electrode 90 when turned on is applied with a reverse bias between the second conductive contact region 46 and the first conductive drain region 10a. The depletion layer generated at this time is formed between the second conductive diffusion region 42; 42a surrounding the first pillar layer 40 and the first conductive second pillar layer 22; (BV) also has the advantage of being possible.

If the first conductivity type is N type, the second conductivity type is P type and may be opposite to each other. In the present specification and the accompanying drawings, the first conductive type is described as N type and the second conductive type is described as P type for convenience, but may be described or displayed opposite to each other.

In the present specification and the accompanying drawings, P- and P + all refer to a P-type impurity doping layer, and N-, N +, and N ++ all refer to an N-type impurity doping layer, and + is greater than-, ++ is greater than +. It is doped at a high concentration.

The power MOSFET according to the present invention may be specifically implemented as shown in FIGS. 8 to 12 and 16.

According to the embodiment shown in FIG. 8, the P-diffusion region 42 is formed to surround the P-type first pillar layer 40 and to diffuse to the N ++ drain region 10a.

Although the second pillar layer 22 is illustrated as N−, the doping concentration may be further increased (eg, N0: N0> N−) to further lower the on resistance Ron.

In addition, when the MOSFET is turned on, electron current flows to both source electrodes 80-> second pillar layer 22-> drain electrode 90, and at this time, the N-second pillar layer 22 prevents electron flow. The holes pass through a depletion layer formed between the N-second pillar layer 22 and the P- diffusion region 42 with reverse bias, and the P-type first pillar layer 40-> P + contact region 46-> source As it exits to the electrode 80, the on resistance Ron can be further lowered.

According to the embodiment shown in FIG. 9, a P + sinker part 48 is further formed below the P-type first pillar layer 40, so that the holes entering the P- diffusion region 42 are formed in the P-type first pillar layer 40. One pillar layer 40 can be more effectively pulled out.

In the embodiment of FIG. 9, the P + sinker part is formed up to the N ++ drain region 10a, but may be formed apart from the N ++ drain region 10a. The P-diffusion region 42 is formed between the P-base region 44 and the P + sinker portion 48 to surround the P-type first pillar layer 40.

According to the embodiment shown in FIG. 10, in the embodiment according to FIG. 9, the sidewall insulating layer 51 is further formed on the trench sidewall 40a and filled with a conductive material to form the P-type first pillar layer 40. In this case, the conductive material may be a metallic material such as metal silicide as well as a silicon-based material such as polysilicon doped with P-type impurities.

According to the embodiment shown in FIG. 11, in each of the above-described embodiments, a second trench is formed at a predetermined depth from the top of the N− second pillar layer 22, and a second gate insulating layer 61 is formed on the inner wall of the second trench. The gate electrode 72 is formed to be in contact with the N + source region 50 and the P− base region 44 laterally, and a gate electrode 72 having a trench is formed on the second gate insulating film.

In this case, the second trench depth is preferably smaller than the depth of the trench 40a for forming the P-type first pillar layer 40 and larger than the junction depth of the P-base region 44.

11, a vertical channel is formed in the side base region 44 in contact with the gate insulating film 61, and the current path formed in the N-second pillar layer 22 is shortened, thereby turning on resistance (Ron). It is possible to further reduce the size and to reduce the area occupied by the horizontal channel has the advantage that can significantly reduce the size of the chip (device).

According to the embodiment shown in FIG. 12, in the embodiment according to FIG. 11, the second gate insulating layer 61 further includes an optional insulating layer 63 formed at the bottom of the second trench, so that the second gate insulating layer 61 is formed more than the sidewall at the bottom of the second trench. In this way, the influence of the electric field generated at the end of the gate electrode 72 can be reduced.

8 to 12 are formed by etching an N- epitaxial layer having a predetermined thickness on an N-type semiconductor substrate and etching the same, or the N-type semiconductor substrate itself may be formed by etching. Of course.

According to the embodiment shown in FIG. 16, the structure is similar to that of the embodiment of FIG. 8, but the N-type semiconductor substrate itself is etched to form a large portion, and the second N-type semiconductor substrate is pasted to attach the N ++ drain region 10a. Shows that they form.

As shown in Fig. 16, in each embodiment according to Figs. 8 to 12, the P-base region 44 and the P-diffusion region 42 are P-type first pillars as one P-region 42a. It may be formed surrounding the layer 40.

In FIG. 16, reference numeral 11 denotes a substrate bonding layer, and 12 denotes a second N-type semiconductor substrate or an epi layer of the substrate, respectively.

[Production method First Embodiment ]

Next, referring to FIGS. 4 to 8, a method of manufacturing a power MOSFET according to an embodiment of the present invention will be described.

First, as shown in FIG. 4, the N− epitaxial layer 20 is grown to a predetermined thickness on the N + semiconductor substrate 10 having the first conductivity type (eg, N type) (first step).

Subsequently, as shown in FIG. 5, a predetermined interval etching mask 30 is formed horizontally on the epitaxial layer 20 and the epitaxial layer 20 is etched to form a trench 40a having a predetermined depth vertically. Step 2).

In this case, a step of injecting P-type impurities into the inner wall of the trench 40a may be further added.

In particular, as shown in FIG. 9, in order to form a P + sinker portion 48 below the P-type first pillar layer 40, P-type impurities are injected at a high concentration (for example, into the trench inner wall) at the bottom of the trench 40a. Injecting at an impurity concentration or a concentration higher than the doping concentration of the P-type first pillar layer may be further added.

As shown in FIG. 10, the method may further include forming a sidewall insulating layer 51 on the sidewalls of the trench 40a.

Subsequently, as shown in FIG. 6, the trench 40a is filled with a conductive material and planarized to expose the epitaxial layer to form a first pillar layer 40 of a second conductive type (eg, P type) (step 3). ).

The conductive material may be a semiconductor material doped with an impurity or a metallic material such as metal silicide, but the P-type diffusion layer 41 may be formed by forming the P-type first pillar layer 40 and subsequently diffusing the P-type impurity. In order to form, a silicon-based material such as polysilicon doped with P-type impurities is preferable.

Therefore, the P-diffusion region 41 shown in FIG. 6 may be formed by injecting P-type impurities into the inner wall of the trench 40a in the second step, and the P-type first pillar layer 40 in the third step. After forming, the thermal diffusion process may be performed. The latter thermal diffusion process may later be replaced by a thermal diffusion process when the base region 44, the source region 50, and the contact region 46 are formed.

Next, as shown in FIG. 7, a gate insulating film 60 and a gate electrode 70 are sequentially formed on the epitaxial layer 20 exposed between the P-type first pillar layer 40 (fourth step).

11 and 12, when the trench gate electrode 72 is formed, the trench gate electrode 72 may be formed smaller than the trench depth of the second step on the epitaxial layer 20 exposed between the first pillar layers 40. Forming a second trench larger than the junction depth of the P-base region 44 to be formed (step 4-1), and forming a gate insulating layer 61 on the second trench inner wall and the epitaxial layer. (Step 4-2), and depositing and etching a gate material on the gate insulating film to form a gate electrode 72 (step 4-3).

In addition, between steps 4-2 and 4-3, as shown in FIG. 12, an insulating layer 63 is further formed on the bottom of the second trench to make a difference in thickness between the sidewall and the gate insulating layer. You can proceed further.

Thereafter, using the gate electrodes 70 and 72 and forming an ion implantation mask (not shown), if necessary, as shown in FIGS. 7, 11 and 12, to the epi layer 20 by an ion implantation and thermal diffusion process. A P− base region 44, an N + source region 50, and a P + contact region 46 are formed around the P-type first pillar layer 40 (step 5).

Next, a source electrode 80 is formed of a conductive material to contact the N + source region, the P + contact region, and the P-type first pillar layer 40 (step 6).

Finally, as shown in FIG. 8, the rear surface of the semiconductor substrate 10 is ground to a predetermined thickness and ion implanted into the back surface with N-type impurities to form an N ++ drain region 10a, and a drain electrode under the drain region 10a. 90 is formed (7th step).

In the above embodiment, the first conductive type is described as N type, and the second conductive type is described as P type, but may be described in reverse.

[Production method Second Embodiment ]

13 to 16, a method of manufacturing a power MOSFET according to another embodiment of the present invention will be described.

First, as shown in FIG. 13, a constant interval etching mask 30 is formed horizontally on an N- semiconductor substrate 20a having a first conductivity type (eg, N type), and the semiconductor substrate is etched to be vertically constant. A trench 40a of depth is formed (first step).

In this case, a step of injecting P-type impurities into the inner wall of the trench 40a may be further added.

In particular, in order to form the P + sinker portion 48 below the P-type first pillar layer 40, a high concentration of P-type impurities (for example, an impurity concentration that is injected into the trench inner wall or a later P) is formed at the bottom of the trench 40a. Injecting at a concentration higher than the doping concentration of the mold first pillar layer may be further added.

The sidewall insulating layer 51 may be further formed on the sidewalls of the trench 40a.

Subsequently, as shown in FIG. 14, the conductive material 40b is filled in the trench 40a, and the bottom of the semiconductor substrate 20a is ground to expose the trench 40a. The N-type semiconductor substrates 10 and 12 are bonded (second step).

Here, the conductive material 40b may be a semiconductor material doped with impurities or a metallic material such as metal silicide, but the P-type diffusion region is formed by forming a P-type first pillar layer 40 and diffusing the P-type impurities. In order to form, a silicon-based material such as polysilicon doped with P-type impurities is preferable.

Therefore, the P-diffusion region to be formed later may be formed by injecting P-type impurities into the inner wall of the trench 40a in the first step, or the thermal diffusion process after forming the P-type first pillar layer 40 in the second step. It may be formed by proceeding, or may be formed by ion implantation and thermal diffusion process after the gate electrode 70 is formed.

The trench 40a can be formed by changing the bottom of the semiconductor substrate 20a to expose the trench 40a, and using a known substrate bonding technique, as shown in FIG. 15, the second trench 40a can be formed. N-type semiconductor substrates 10 and 12 are bonded to form a drain region later.

The second N-type semiconductor substrates 10 and 12 may be formed by growing an N− epitaxial layer 12 on the N + substrate 10 or injecting N-type impurities into the N− substrate 12 to form an N + layer 10. ) May be formed.

Next, as shown in FIG. 15, the conductive material 40b is etched and the etch mask 30 is removed to form the P-type first pillar layer 40 (third step).

Subsequently, as shown in FIG. 15, the gate insulating layer 60a and the gate electrode 70 are sequentially formed on the active region of the semiconductor substrate exposed between the first pillar layers 40 (fourth step).

In this case, as in the first embodiment of the manufacturing method, when the trench gate electrode 72 shown in FIG. 11 is formed, the first and second active layers 20b are exposed on the active region 20b. Forming a second trench larger than the junction depth of the P-base region 44a to be formed later than the depth of the trench 40a of the first step (step 4-1), and forming the second trench inner wall and the epi layer. After the gate insulating layer 61 is formed on the gate insulating layer 61 (step 4-2), the gate material 72 may be formed by etching and etching the gate material on the gate insulating layer (step 4-3). have.

In addition, between steps 4-2 and 4-3, as shown in FIG. 12, an insulating layer 63 is further formed on the bottom of the second trench to make a difference in thickness between the sidewall and the gate insulating layer. You can proceed further.

Subsequently, the gate electrodes 70 and 72 are used and an ion implantation mask (not shown) is formed if necessary. As shown in FIG. 15, the P-type first pillar is formed in the active region 20b by an ion implantation and thermal diffusion process. P-base region 44a, N + source region 50 and P + contact region 46 are formed around layer 40 (step 5).

In this case, the P-base region 44a may be simultaneously formed with the P-diffusion region 42a surrounding the first pillar layer 40. That is, the ion implantation energy may be increased to form the ion implantation energy to the lower portion of the first pillar layer 40 when the P-base region 44a is formed, and the P-type impurity implanted when the first pillar layer 40 is formed. P-diffusion regions 42a surrounding the first pillar layer 40 may also be formed by diffusion.

Next, a source electrode 80 is formed of a conductive material to contact the N + source region, the P + contact region, and the P-type first pillar layer 40 (step 6).

Lastly, as shown in FIG. 16, the rear surface of the second semiconductor substrate 10 is ground to a predetermined thickness, and ion implanted into the rear surface of the second semiconductor substrate 10 to form an N ++ drain region 10a, and the lower portion of the drain region 10a. A drain electrode 90 is formed in the seventh step.

In the above embodiment, the first conductive type is described as N type, and the second conductive type is described as P type, but may be described in reverse.

10, 20a: N-type semiconductor substrate
11: bonding layer
10a: N ++ drain region
12, 22, 22a: N-second pillar layer
20: N- epi layer
20b: N-active area
30: etching mask
40: P-type second pillar layer
42: P-diffusion layer
44: P-base area
46: P + contact area
48: P + sinker part
50: N + source area
60, 61: gate insulating film
70: gate electrode
80: source electrode
90: drain electrode

Claims (21)

A first conductive drain region horizontally contacting the drain electrode at a lower portion thereof;
Two second conductive first pillar layers filled with a conductive material in a trench vertically spaced horizontally and vertically spaced on the drain region;
A second conductive base region formed to a predetermined depth around each of the first pillar layers;
A first conductive source region formed around the upper portion of the first pillar layer in the base region and having a smaller junction depth than the base region;
A second conductive contact region formed in the base region around the first pillar layer and having a smaller width and a larger bonding depth than the source region and a smaller bonding depth than the base region;
A second conductive diffusion region formed around the first pillar layer below the base region;
A first conductive second pillar layer formed between the first conductive diffusion region and the base region between the first pillar layers on the drain region;
A gate electrode formed on the second pillar layer, two base regions formed on both sides of the second pillar layer, and two source regions with a gate insulating film interposed therebetween; And
And a source electrode formed to be in contact with each of the top surfaces of the source region, the contact region, and the first pillar layer exposed to both sides of the gate electrode with an insulating film interposed therebetween on the gate electrode. Power MOSFET with trench structure.
The method of claim 1,
The diffusion region is a power MOSFET having a superjunction trench structure, characterized in that the diffusion is formed to the drain region.
The method of claim 1,
A power MOSFET having a superjunction trench structure, wherein a second conductive type sinker part is further formed under each of the first pillar layers.
The method of claim 3, wherein
The first pillar layer is a power MOSFET having a superjunction trench structure, characterized in that formed of polysilicon or metal silicide doped with a second conductive type.
The method of claim 4, wherein
And the first pillar layers further form a sidewall insulating film on the sidewalls of the trench and are filled with the conductive material.
The method of claim 4, wherein
The sinker portion is formed to the drain region,
The diffusion region is a power MOSFET having a superjunction trench structure, characterized in that the diffusion is formed between the base region and the sinker portion.
7. The method according to any one of claims 1 to 6,
A second trench of a predetermined depth is formed on the second pillar layer to contact the source region and the base region laterally.
A second gate insulating layer is formed on the second trench inner wall;
And the gate electrode is formed on the second gate insulating layer, and has a super junction trench structure.
The method of claim 7, wherein
And said second trench depth is less than the depth of the trench for forming said first pillar layer and greater than the junction depth of said base region.
The method of claim 8,
And the second gate insulating layer is formed thicker than a sidewall at the bottom of the second trench.
A first step of growing an epitaxial layer of the first conductive type to a predetermined thickness on a semiconductor substrate having the first conductive type;
A second step of forming an etch mask horizontally on the epitaxial layer and etching the epitaxial layer to form a trench of a predetermined depth vertically;
Filling the trench with a conductive material and planarizing the exposed epitaxial layer to form a first pillar layer of a second conductivity type;
A fourth step of sequentially forming a gate insulating film and a gate electrode on the epitaxial layer exposed between the first pillar layers;
A fifth step of forming a base region of a second conductivity type, a source region of a first conductivity type, and a contact region of a second conductivity type in the epi layer around the first pillar layer by an ion implantation and thermal diffusion process;
Forming a source electrode to contact the source region, the contact region, and the first pillar layer; And
And a seventh step of forming a drain region of a first conductivity type by removing a predetermined thickness of the back surface of the semiconductor substrate and implanting ions into the back surface, and forming a drain electrode under the drain region. Method for producing a power MOSFET having a.
11. The method of claim 10,
The method may further include implanting ions into the trench inner wall between the second step and the third step, or forming the first pillar layer in the third step and further performing a diffusion process before the fourth step. The impurity implanted in the first pillar layer is diffused to form a diffusion region of the second conductivity type around the trench, the method of manufacturing a power MOSFET having a superjunction trench structure.
11. The method of claim 10,
And forming a sinker portion having a high concentration such as that of the contact region by injecting a second conductive type impurity into the bottom of the trench between the second and third steps. Method for producing a power MOSFET having a.
11. The method of claim 10,
And forming a sidewall insulating film on the sidewalls of the trench between the second step and the third step.
The method according to any one of claims 10 to 13,
In the fourth step, a fourth trench is formed on the epitaxial layer exposed between the first pillar layers to form a second trench larger than the junction depth of the base region of the fifth stage, which is smaller than the trench depth of the second stage. ;
Forming a gate insulating layer on the second trench inner wall and the epitaxial layer; And
And forming a gate electrode by depositing and etching a gate material on the gate insulating layer to form a gate electrode.
15. The method of claim 14,
And forming an insulating film on the bottom of the second trench to make a difference in the thickness of the sidewalls and the gate insulating film between the steps 4-2 and 4-3. Method for producing a power MOSFET having a.
Forming a etch mask horizontally on the semiconductor substrate having the first conductivity type horizontally and etching the semiconductor substrate to form a trench of a predetermined depth vertically;
Filling the trench with a conductive material, grinding the bottom of the semiconductor substrate to expose the trench, and then bonding a second semiconductor substrate having a first conductivity type;
Etching the conductive material and removing the etching mask to form a first pillar layer of a second conductive type;
A fourth step of sequentially forming a gate insulating film and a gate electrode on an active region of the semiconductor substrate exposed between the first pillar layers;
Forming a base region of a second conductivity type, a source region of a first conductivity type, and a contact region of a second conductivity type in the active region around the first pillar layer by an ion implantation and thermal diffusion process;
Forming a source electrode to contact the source region, the contact region, and the first pillar layer; And
And a seventh step of forming a drain region of a first conductivity type by grinding a rear surface of the second semiconductor substrate by a predetermined thickness and implanting ions into the rear surface, and forming a drain electrode under the drain region. A method for producing a power MOSFET having a junction trench structure.
17. The method of claim 16,
The method may further include implanting ions into the trench inner wall between the first step and the second step, or forming the first pillar layer in the third step and further performing a diffusion process before the fourth step. The impurity implanted in the first pillar layer is diffused to form a diffusion region of the second conductivity type around the trench, the method of manufacturing a power MOSFET having a superjunction trench structure.
17. The method of claim 16,
And forming a sinker portion having a high concentration such as that of the contact region by injecting a second conductive impurity into the bottom of the trench between the first and second steps. Method for producing a power MOSFET having a.
17. The method of claim 16,
And forming a sidewall insulating film on the sidewalls of the trench between the first step and the second step.
The method according to any one of claims 16 to 19,
In the fourth step, a fourth trench is formed on the active region exposed between the first pillar layers to form a second trench larger than a junction depth of the base region of the fifth stage, which is smaller than the trench depth of the first stage. ;
Forming a gate insulating layer on the second trench inner wall and the epitaxial layer; And
And forming a gate electrode by depositing and etching a gate material on the gate insulating layer to form a gate electrode.
21. The method of claim 20,
And forming an insulating film on the bottom of the second trench to make a difference in the thickness of the sidewalls and the gate insulating film between the steps 4-2 and 4-3. Method for producing a power MOSFET having a.

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