TWI641107B - Lateral diffused metal oxide semiconductor field effect transistor - Google Patents

Abstract

An embodiment of the present invention provides a laterally diffused metal oxide semiconductor field-effect transistor including: a body region, which is located above the substrate; a drift region, which is located above the substrate and is adjacent to the body region; The source region is located in the body region; the drain region is located in the drift region; the first isolation region is located in the drift region between the source region and the drain region; the top doped region is located below the first isolation region ; The capacitor is located above the well region; and the second isolation region is located in the well region between the source region and the capacitor; in the above view, the gate electrode is in a loop shape, and the drain region is provided in a loop shape. Inside, the source region is disposed on the outside of the loop shape; wherein the loop shape has a gap, and the first isolation region and the second isolation region are connected at the gap, and the capacitor surrounds the gate.

Description

Laterally diffused metal oxide semiconductor field effect transistor

Embodiments of the present invention relate to a semiconductor technology, and particularly to a laterally diffused metal oxide semiconductor field effect transistor.

The high-voltage semiconductor element is suitable for the field of integrated circuits of high voltage and high power. A conventional high-voltage semiconductor device includes a lateral diffused metal oxide semiconductor (LDMOS). The advantage of high-voltage semiconductor components is that they are easily compatible with other processes and are cost-effective. Therefore, they are widely used in power supply, power management, display drive IC components, communications, automotive electronics, industrial control and other fields.

When a laterally diffused metal-oxide half-field effect transistor is connected to an AC power source, a large amount of electrostatic charges may be accumulated, and these electrostatic charges may flow at any two ends to generate an electrostatic discharge (ESD) current. If the electrostatic discharge current is not properly controlled, it may burn the integrated circuit and cause damage to the components. For example, if the electrostatic discharge current flows from the drain to the source of the element, it may also flow to the gate of the element, causing damage to the gate.

In summary, although the existing laterally diffused metal-oxide-semiconductor field-effect transistors generally meet the requirements, they are not satisfactory in all aspects, especially the electrostatic discharge current of laterally-diffused metal-oxide-semiconductor field-effect transistors is still Needs further improvement.

An embodiment of the present invention provides a laterally diffused metal oxide semiconductor field effect transistor, including: a substrate having a first conductivity type; a body region located above the substrate; the body region having the first conductivity type; a drift region located above the substrate Adjacent to the body region, the drift region has a second conductivity type opposite to the first conductivity type; the gate electrode is located above the body region and the drift region; the source region is located in the body region, and the source region has a second conductivity type; The drain region is located in the drift region, the drain region has a second conductivity type; the first isolation region is located in the drift region between the source region and the drain region; the top doped region is located below the first isolation region The top doped region has a first conductivity type; a capacitor is located above the well region; and a second isolation region is located in the well region between the source region and the capacitor; wherein, in the upper view, the gate has a loop shape, The drain electrode is disposed on the inner side of the loop shape, and the source electrode is disposed on the outer side of the loop shape. The loop shape has a gap, and the first isolation region and the second isolation region are connected at the gap, and the capacitor surrounds the gate.

An embodiment of the present invention provides another laterally diffused metal oxide semiconductor field effect transistor, including: a substrate having a first conductivity type; a body region located above the substrate; the body region having the first conductivity type; a drift region located on the substrate; The upper part is adjacent to the body region, the drift region has a second conductivity type opposite to the first conductivity type; the gate electrode is located above the body region and the drift region; the source region is located in the body region, and the source region has a second conductivity Type; drain region, located in the drift region, the drain region has a second conductivity type; a first isolation region, located in the drift region adjacent to the drain region; a second isolation region, located in the drift region adjacent to the gate; top The doped region is located below the first isolation region and the second isolation region, and the top doped region has a first conductive region Electrical type; and a capacitor located above the drift region between the first isolation region and the second isolation region.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are described below in detail, in conjunction with the accompanying drawings, as follows.

100, 200, 300, 400, 500‧‧‧ laterally diffused metal oxide semiconductor field effect transistors

102‧‧‧ substrate

104‧‧‧Body area

106‧‧‧ Drifting Zone

108‧‧‧well area

110‧‧‧Source area

112‧‧‧ Drain

114‧‧‧ base region

116‧‧‧ doped region

118‧‧‧ heavily doped drain region

120, 120A, 120B

122‧‧‧Top doped region

124‧‧‧Gate

124A‧‧‧ Dielectric layer

124B‧‧‧electrode layer

126‧‧‧Capacitor

126A‧‧‧Dielectric layer

126B‧‧‧electrode layer

128‧‧‧ gap

130‧‧‧electrostatic discharge current

232‧‧‧Buried layer

322‧‧‧top doped region

432‧‧‧burial layer

520A, 520B‧‧‧‧ isolated area

522A, 522B‧‧‧Top doped region

526‧‧‧Capacitor

534‧‧‧Interlayer dielectric layer

536‧‧‧Source Metal

536E‧‧‧Edge

538‧‧‧Contact

AA ’, BB’‧‧‧ line segments

XA, XB‧‧‧ distance

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

FIG. 1 is a top view of a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 2A is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 2B is a cross-sectional view illustrating a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 3 is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 4 is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 5 is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments.

FIG. 6 illustrates a top view of a laterally diffused metal oxide semiconductor field effect transistor according to other embodiments.

FIG. 7 illustrates a laterally diffused metal oxide half according to other embodiments. Sectional view of a conductor field effect transistor.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. These space-related terms Words are used to facilitate the description of the relationship between one or more elements or features and other elements or features in the illustration. These spatially related terms include different positions of the device in use or operation, as well as in the drawings. The described orientation. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used in it will also be interpreted in terms of the orientation after turning.

Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, the "about", "large" can still be implied without specifying "about", "approximately", and "probably" Meaning "about" and "probably."

An embodiment of the present invention provides a lateral diffused metal oxide semiconductor (LDMOS) field effect transistor, which is used to form a capacitor in a device, which can release electrostatic discharge (ESD) current without damaging the gate electrode. Without adding too much extra capacitor area and without changing its DC performance.

FIG. 1 illustrates a top view of a laterally diffused metal oxide semiconductor field effect transistor 100 according to some embodiments of the present invention, and FIGS. 2A and 2B illustrate a laterally diffused metal oxide semiconductor field effect transistor according to some embodiments of the present invention. A cross-sectional view of the crystal 100. Figure 2A is a cross-sectional view along line AA 'in Figure 1 and Figure 2B is a cross-sectional view along line BB' in Figure 1. In some embodiments, the laterally diffused metal-oxide-semiconductor field-effect transistor 100 is a high-voltage device, and its operating voltage ranges from 100V to 800V.

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 includes a substrate 102. This substrate 102 may be a semiconductor substrate, which may include elemental semiconductors such as silicon (Si), germanium (Ge), etc .; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), Gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc .; alloy semiconductors, such as silicon germanium alloy (SiGe), phosphorous arsenic gallium alloy (GaAsP), aluminum arsenic Indium alloy (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphorus (GaInP), indium gallium phosphorus arsenide (GaInAsP), or a combination of the above materials. In addition, the substrate 102 may be a semiconductor on insulator substrate. In some embodiments, the substrate 102 has a first conductivity type.

According to some embodiments, as shown in FIG. 2A, the lateral diffusion metal oxide semiconductor field effect transistor 100 includes a body region 104, a drift region 106, and a well region 108, which are disposed on an upper portion of the substrate 102. In some embodiments, the body region 104, the drift region 106, and the well region 108 are formed by ion implanting the substrate 102 through a patterned mask. In some embodiments, the body region 104 has a first conductivity type, and the drift region 106 and the well region 108 have a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type. In other embodiments, when the first conductivity type is N-type, the second conductivity type is P-type. In some embodiments, the P-type dopant may include boron, gallium, aluminum, indium, boron trifluoride ion (BF ₃ ⁺ ), or a combination thereof, and the N-type dopant may include phosphorus, arsenic, nitrogen, antimony, Or a combination of the foregoing. In some embodiments, the doping concentration of the body region 104 is between 5e16 / cm ³ and 5e18 / cm ³ , and the doping concentration of the drift region 106 is between 1e16 / cm ³ and 5e17 / cm ^{3. The} well region The doping concentration of 108 is between 1e16 / cm ³ and 5e18 / cm ³ . In some embodiments, the doping concentration of the well region 108 is greater than or equal to the doping concentration of the drift region 106 to obtain better device characteristics.

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a source region 110, a drain region 112, a base region 114, and a doped region 116. The source region 110 and the base region 114 are disposed in the body region 104 adjacent to the upper surface of the substrate 102, and the source region 110 adjoins the base region 114. The drain region 112 is disposed in the drift region 106 adjacent to the upper surface of the substrate 102. The doped region 116 is disposed in the well region 108 adjacent to the upper surface of the substrate 102. In some embodiments, the source region 110, the drain region 112, the base region 114, and the doped region 116 are formed by ion implanting the substrate 102 through a patterned mask. In some embodiments, the base region 114 has a first conductivity type, and its doping concentration is higher than the first conductivity type doping concentration of the body region 104. The doped region 116 also has the first conductivity type, and the source region 110 Both the drain region 112 and the drain region 112 have a second conductivity type, and their doping concentrations are higher than the second conductivity type doping concentration of the drift region 106. In some embodiments, the doping concentration of the source region 110 is between 5e19 / cm ³ and 1e21 / cm ³ , and the doping concentration of the drain region 112 is between 5e19 / cm ³ and 1e21 / cm ³ . The doping concentration of the base region 114 is between 5e19 / cm ³ and 1e21 / cm ³ , and the doping concentration of the doped region 116 is between 5e19 / cm ³ and 1e21 / cm ³ .

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a heavily doped drain region 118. The heavily doped drain region 118 is disposed in the drift region 106 adjacent to the upper surface of the substrate 102 and surrounds the drain region 112. In some embodiments, the heavily doped drain region 118 is formed by ion implanting the substrate 102 through a patterned mask. In some embodiments, the heavily doped drain region 118 has a second conductivity type, and its doping concentration is higher than the second conductivity type doping concentration of the drift region 106 and lower than the second conductivity type doping of the drain region 112. concentration. In some embodiments, the doping concentration of the heavily doped drain region 118 is between 1e17 / cm ³ and 5e18 / cm ³ . The heavily doped drain region 118 can reduce the doping gradient and reduce the electric field strength at the drain terminal.

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a plurality of isolation regions 120A and 120B formed on the substrate 102, wherein the isolation region 120A is located in the source region 110 and On the drift region 106 between the drain regions 112. In some embodiments, the isolation regions 120A and 120B may be field oxides. In some embodiments, the isolation regions 120A and 120B may be a local oxidation of silicon, LOCOS). In other embodiments, the isolation regions 120A and 120B may be shallow trench isolation (STI) structures.

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a top doping region 122 formed below the isolation region 120A. In some embodiments, before the isolation region 120A is formed, the substrate 102 may be ion-implanted through the patterned mask to form the top doped region 122. In some embodiments, the top doped region 122 has a first conductivity type. In some embodiments, the doping concentration of the top doped region 122 is between 1e17 / cm ³ and 5e18 / cm ³ . In some embodiments, the area of the top doped region 122 is smaller than the area of the isolation region 120A. In some embodiments, the top doped region 122 does not adjoin the heavily doped drain region 118 but is spaced apart from the heavily doped drain region 118. In some embodiments, the doping depth and doping concentration of the top doped region 122 are uniformly distributed. The top doped region 122 can reduce the surface electric field, thereby improving the breakdown voltage and on-resistance (Ron) of the laterally diffused metal oxide semiconductor field effect transistor 100.

According to some embodiments, as shown in FIG. 2A, the laterally diffused metal oxide semiconductor field effect transistor 100 further includes a gate electrode 124 located on the body region 104 and the drift region 106 and extending to cover a part of the isolation region 120A. The laterally diffused metal oxide semiconductor field effect transistor 100 also includes a capacitor 126 located above the well region 108 and between the doped regions 116. In some embodiments, the gate 124 and the capacitor 126 may include dielectric layers 124A and 126A, and electrode layers 124B and 126B located above the dielectric layers 124A and 126A. In some embodiments, the dielectric layers 124A and 126A may be formed at the same time, and the electrode layers 124B and 126B may also be formed at the same time. In some embodiments, the electrode layer 126B of the capacitor 126 is grounded.

In some embodiments, the dielectric layers 124A and 126A may include silicon oxide, silicon nitride, silicon oxynitride, high-k (i.e., dielectric) Dielectric constants greater than 3.9) such as HfO ₂ , LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO , LaSiO, AlSiO, (Ba, Sr) TiO ₃ , Al ₂ O ₃ , or a combination thereof. The dielectric layers 124A and 126A may use a suitable oxidation process (such as a dry oxidation process or a wet oxidation process), a deposition process (such as a chemical vapor deposition process or an atomic layer deposition (ALD) process). , Other suitable processes, or a combination of the above. In some embodiments, the dielectric layers 124A and 126A may use a thermal oxidation process to thermally grow in an environment containing oxygen or nitrogen (eg, containing NO or N ₂ O) to form a dielectric before forming the electrode layers 124B and 126B. Layers 124A and 126A.

In some embodiments, the electrode layers 124B and 126B are formed on the dielectric layers 124A and 126A. The electrode layers 124B and 126B may include polycrystalline silicon, a metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), a metal alloy, a metal nitride (e.g., tungsten nitride, nitride Molybdenum, titanium nitride, tantalum nitride, analogs thereof, or a combination thereof), metal silicides (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, hafnium silicide, their analogs, or the like) Combinations), metal oxides (ruthenium oxide, indium tin oxide, analogs thereof, or combinations thereof), other suitable materials, or combinations thereof. The electrode layers 124B and 126B may use a chemical vapor deposition (CVD) process (such as a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition process (plasma enhanced process) chemical vapor deposition (PECVD)), physical vapor deposition (PVD) (such as resistance heating evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition (atomic layer) deposition (ALD), other suitable processes, or a combination of the above to form an electrode material on the substrate 102, and then pattern it using lithography and etching processes to form electrode layers 124B and 126B.

In some embodiments, as shown in FIG. 2A, the electrode layer 126B and the well region 108 are used as the two electrodes of the capacitor 126, and a dielectric layer 126A is sandwiched between the electrode layer 126B and the well region 108 to form the capacitor 126.

In some embodiments, the dielectric layer 126A and the electrode layer 126B of the gate electrode 124 and the capacitor 126 can be formed simultaneously in the same deposition and patterning process to simplify the process and reduce the cost.

In some embodiments, the top view of the laterally diffused metal-oxide-semiconductor field-effect transistor 100 is as shown in FIG. 1, and the gate electrode 124 has a loop shape, including a ring and a circle. ), Oval, and race track. The gate electrode 124 has a gap 128, the drain region 112 is located inside the gate electrode 124, the source region 110 is located outside the gate electrode 124, and the capacitor 126 surrounds the gate electrode 124. In some embodiments, the gate 124, the source region 110, and the capacitor 126 are substantially coaxial with respect to the drain region 112. In the embodiment shown in FIG. 1, the drain region 112, the gate 124, the source region 110, and the capacitor 126 are substantially circular. In some embodiments, as shown in FIG. 1, the isolation region 120A is located between the drain region 112 and the gate 124, and the isolation region 120B is located between the source region 110 and the capacitor 126. In some embodiments, as shown in FIG. 1, the isolation region 120A and the isolation region 120B are connected at the gap 128 to become the isolation region 120.

In some embodiments, as shown in FIG. 1 and FIGS. 2A to 2B, since the overall resistance of the drift region 106 and the well region 108 is lower at the gap 128, when the electrostatic discharge occurs, the electrostatic discharge current 130 passes through The notch 128 flows to the grounded capacitor 126, and the electrostatic discharge current 130 is released by the capacitor 126 without flowing to the gate electrode 124 to avoid causing damage to the gate electrode 124. In addition, since the capacitor 126 only allows an alternating current such as the electrostatic discharge current 130 to pass, and does not allow a direct current, the direct current of the laterally diffused metal oxide semiconductor field effect transistor 100 does not change due to the capacitor 126. The DC performance of the laterally diffused metal oxide semiconductor field effect transistor 100 can be maintained at the same time.

It should be noted that the laterally diffused metal oxide semiconductor field effect transistor 100 shown in FIG. 1 is only an example, but the embodiment of the present invention is not limited thereto. In some embodiments, the capacitor 126 may be circular, oval, race track, or other suitable shapes according to design or process requirements. By adjusting the ratio of the straight portion to the curved portion in the shape of the laterally diffused metal oxide semiconductor field effect transistor, the overall electric field distribution can be adjusted, and the breakdown voltage of the device can be further adjusted. In some embodiments, the gate 124 may have one or more gaps 128, depending on the product requirements.

FIG. 3 is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor 200 according to some embodiments. Figure 3 is a cross-sectional view along the gate gap. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. A difference from the foregoing embodiment is that a buried layer 232 is provided below the drift region 106 and the well region 108. In some embodiments, the buried layer 232 is only located below the drift region 106 and the well region 108 at the gate gap. In other embodiments, the buried layer 232 may be located below the drift region 106 and the well region 108 at the loop-shaped gate. In some embodiments, the buried layer 232 is located below a portion of the drift region 106 and the entire well region 108. In some embodiments, before the drift region 106 and the well region 108 are formed, the substrate 102 may be ion-implanted through the patterned mask to form the buried layer 232. In some embodiments, the buried layer 232 has a second conductivity type, and its doping concentration is higher than the second conductivity type doping concentration of the drift region 106. In some embodiments, the doping concentration of the buried layer 232 is between 1e17 / cm ³ and 1e19 / cm ³ .

In the embodiment shown in FIG. 3, because the doping concentration of the buried layer 232 is high, the resistance value can be further reduced, so that when an electrostatic discharge occurs, the electrostatic discharge current 130 tends to flow through the gap to the grounded capacitor 126, The capacitor 126 releases the electrostatic discharge current 130 without flowing to the gate, thereby avoiding damage to the gate.

FIG. 4 is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor 300 according to some embodiments. Figure 4 is a sectional view along the gate gap. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that the doping depth of the top doping region 322 under the isolation region 120 is not uniformly distributed, but decreases linearly from the capacitor 126 to the drain region 112.

In some embodiments, before the isolation region 120 is formed, the substrate 102 may be ion-implanted through the patterned mask to form the top doped region 322. In some embodiments, the patterned mask forms non-equal-width and non-equidistant photoresist patterns (not shown) in the predetermined region of the top doped region 322, and the photoresist patterns near the capacitor 126 are far away from each other. The width of the photoresistive region is relatively wide, and the photoresistance pattern near the drain region 112 The cases are close to each other, and the width of the non-resistance area is relatively narrow. In this way, when ion implantation is performed, the dopants implanted near the capacitor 126 are more and deeper, and the implants closer to the drain region 112 are less and shallower. After the annealing process, the contour of the top doped region 322 is formed as shown in FIG. 4. In some embodiments, the doping depth of the top doped region 322 decreases linearly from the capacitor 126 to the drain region 112. In some embodiments, the doping concentration of the top doped region 322 decreases linearly from the capacitor 126 to the drain region 112. In this way, the breakdown voltage and on-resistance (Ron) of the laterally diffused metal oxide semiconductor field effect transistor 300 can be further improved.

In the embodiment shown in FIG. 4, since the doping depth of the top doped region 322 decreases linearly, the breakdown voltage and the on-resistance can be improved. At the same time, when an electrostatic discharge occurs, the electrostatic discharge current 130 flows to the grounded capacitor through the gap. 126, the electrostatic discharge current 130 is released by the capacitor 126 without flowing to the gate electrode to avoid causing damage to the gate electrode.

FIG. 5 is a cross-sectional view of a laterally diffused metal oxide semiconductor field effect transistor 400 according to some embodiments. Figure 5 is a sectional view along the gate gap. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the embodiment of FIG. 3 is that the doping concentration of the well region 408 at the notch is greater than the doping concentration of the well region 108 of FIG. 3, and the length of the buried layer 432 is also longer than that of the buried layer of FIG. 232 short. In some embodiments, the doping concentration of the well region 408 is between 1e16 / cm ³ and 5e18 / cm ³ , and the doping concentration of the drift region 106 is between 1e16 / cm ³ and 5e17 / cm ³ .

In the embodiment shown in FIG. 5, due to the doping concentration of the well region 408, The resistance value is higher, so the resistance value can be further reduced, so that when electrostatic discharge occurs, the electrostatic discharge current 130 is more likely to flow through the gap to the grounded capacitor 126, and the electrostatic discharge current 130 is released by the capacitor 126 without flowing to the gate to avoid causing Damage to the gate. In addition, since the well area 408 has reduced the resistance value, the length of the buried layer 432 can be shortened, and the effect of using the capacitor 126 to discharge the electrostatic discharge current 130 can be achieved.

According to some embodiments, FIG. 6 illustrates a top view of a laterally diffused metal oxide semiconductor field-effect transistor 500 according to some embodiments of the present invention, and FIG. 7 illustrates a laterally diffused metal oxide semiconductor 500 according to some embodiments of the present invention. A cross-sectional view of a field effect transistor 500. Fig. 7 is a sectional view taken along line AA 'in Fig. 6. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that in the foregoing embodiment, the source region and the drain region are in a loop-shaped structure, while in the embodiment shown in FIG. 6, the source region 110 and the drain region 112 are referred to as Interdigitated fingers. In addition, in the foregoing embodiment, the capacitor 126 surrounds the gate electrode 124. In the embodiment shown in FIG. 6, the capacitor 526 is located between two isolation regions 520A and 520B adjacent to the tip of the source region 110.

According to some embodiments, as shown in FIG. 7, the isolation region 520A is located in the drift region 106 adjacent to the drain region 112 and the isolation region 520B is located in the drift region 106 adjacent to the gate 124. The top doped region 522A is located below the isolation region 520A and has an area smaller than that of the isolation region 520A. The top doped region 522B is located below the isolation region 520B and has an area smaller than that of the isolation region 520B. In some embodiments, the top doped region 522A is spaced apart from the top doped region 522B. In some embodiments, the top doped regions 522A and 522B each have a first conductivity type. In some embodiments, the doping concentration of the top doped regions 522A and 522B is between 1e17 / cm ³ and 5e18 / cm ³ .

In some embodiments, the capacitor 526 is adjacent to the tip of the source region 110 and is located above the drift region 106 between the isolation regions 520A and 520B. In some embodiments, the capacitor 526 is isolated from the gate 124 by an isolation region 520B, and the capacitor 526 is isolated from the drain region 112 by an isolation region 520A. In some embodiments, the capacitor 526 may include a dielectric layer and an electrode layer (not shown) above the gate dielectric layer. The other electrode of the capacitor 526 is the drift region 106. In some embodiments, the electrode layer of the capacitor 526 is grounded.

According to some embodiments, as shown in FIG. 7, the laterally diffused metal oxide semiconductor field effect transistor 500 further includes an interlayer dielectric (ILD) 534 overlying the substrate 102. In some embodiments, the interlayer dielectric layer 534 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), and phosphosilicate glass. (phosphosilicate glass, PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials. Low dielectric constant dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, the interlayer dielectric layer 534 can use chemical vapor deposition (CVD) (such as high-density plasma chemical vapor deposition (HDPCVD), atmospheric pressure chemical vapor deposition). Atmospheric pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (APCVD) vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating Formed by spin-on coating, other suitable technologies, or a combination thereof.

In some embodiments, as shown in FIGS. 6 to 7, the laterally diffused metal oxide semiconductor field effect transistor 500 further includes an interconnect structure, including a source metal 536 and a contact 538. In some embodiments, the source metal 536 is electrically connected to the source region 110. The source metal 536 affects the electric field distribution and further affects the collapse voltage of the laterally diffused metal oxide semiconductor field effect transistor 500.

In some embodiments, a lithography process (e.g., covering photoresist, soft baking, exposure, post-exposure baking, development, other suitable techniques, or a combination thereof) and an etching process (e.g., wet etching) may be used Processes, dry etching processes, other suitable technologies, or a combination thereof), other suitable technologies, or a combination of the above to form openings in the interlayer dielectric layer 534 (not shown). Then, a conductive material is filled in the opening to form a contact 538. In some embodiments, the conductive material of the contact 538 includes a metal material (such as tungsten, aluminum, or copper), a metal alloy, polycrystalline silicon, other suitable materials, or a combination thereof. The contact 538 may use a physical vapor deposition (PVD) process (such as a vapor deposition method or a sputtering method), an electroplating method, an atomic layer deposition (ALD) process, other suitable processes, or the foregoing. The combination deposits a conductive material, and optionally performs chemical mechanical polishing (CMP) or etch-back to remove excess conductive material to form the contact 538.

In some embodiments, before filling the conductive material of the contact 538, A barrier layer (not shown) may be formed on the sidewall and the bottom of the opening to prevent the conductive material of the contact 538 from diffusing into the interlayer dielectric layer 534. The material of the barrier layer may be titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), other suitable materials, or the above. Of combination. The barrier layer can be deposited by a physical vapor deposition process (such as an evaporation method or a sputtering method), an atomic layer deposition process, an electroplating method, other suitable processes, or a combination thereof.

In some embodiments, a source metal 536 is formed over the interlayer dielectric layer 534. In some embodiments, the source metal 536 may include Cu, W, Ag, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te, Ga, Other suitable metal materials, the alloys described above, or a combination thereof. In some embodiments, the source metal 536 may include a stacked structure of Ti / TiN / AlCu / TiN. In some embodiments, a blanket is formed on the interlayer dielectric layer 534 by a physical vapor deposition process (such as a vapor deposition method or a sputtering method), an electroplating method, an atomic layer deposition process, other suitable processes, or a combination thereof. (blanket) metal layer (not shown). Then, the blanket metal layer is patterned by a patterning process to form the source metal 536. In some embodiments, the patterning process includes a lithography process (such as covering photoresist, soft baking, exposure, post-exposure baking, development, other suitable techniques, or a combination thereof), an etching process (such as Wet etching process, dry etching process, other suitable technologies, or a combination thereof), other suitable technologies, or a combination thereof.

According to some embodiments, FIG. 6 illustrates an edge 536E of the source metal 536. It is worth noting that the coverage area of the source metal 536 is from the source region 110 to the edge 536E of the source metal 536. However, to simplify the diagram, only the edge 536E of the source metal 536 is shown here to facilitate understanding of the source metal 536. Under the structure.

As shown in FIG. 6, the edge 536E of the source metal 536 is at a distance XA from the tip of the source region 110 and the drain region 112, and the edge 536E of the source metal 536 is at the side of the source region 110 and the drain. The polar regions 112 are separated by a distance XB. In some embodiments, the distance XA is substantially the same as the distance XB. In this way, a better electric field distribution can be obtained, and a better breakdown voltage of the laterally diffused metal oxide semiconductor field effect transistor 500 can be obtained.

In some embodiments, as shown in FIG. 7, the source metal 536 covers the capacitor 526. In this way, setting the capacitor 526 does not affect the electric field distribution, that is, does not affect the collapse voltage of the laterally diffused metal oxide semiconductor field effect transistor 500. In addition, the capacitor 526 is located completely below the source metal 536, and no additional area is required to set the capacitor 526.

In the embodiment shown in FIGS. 6 and 7, in the laterally diffused metal oxide semiconductor field effect transistor 500 with fingers intersecting, since the capacitor 526 is disposed between the drain region 112 and the gate 124, when the electrostatic discharge occurs When this occurs, the electrostatic discharge current 530 flows to the near-grounded capacitor 526, and the electrostatic discharge current 530 is released by the capacitor 526 without flowing to the gate 124 to avoid causing damage to the gate 124. In addition, since the capacitor 526 is located below the source metal 536, no additional area is required, and the electric field distribution and breakdown voltage are not affected.

In summary, an embodiment of the present invention provides a lateral diffused metal oxide semiconductor (LDMOS) field effect transistor. By embedding a capacitor in a device, a path for discharging electrostatic discharge current can be provided, and Prevent the static discharge current from flowing through the gate and damage the gate. Adding a capacitor does not affect the DC performance of the component, nor does it significantly increase the element. Piece area.

The foregoing outlines the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the aspects of the embodiments of the present invention. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

Claims (11)

A lateral diffused metal oxide semiconductor (LDMOS) field effect transistor includes: a substrate having a first conductivity type; and a body region located above the substrate, the body region It has a first conductivity type; a drift region located above the substrate and adjacent to the body region, the drift region has a second conductivity type opposite to the first conductivity type; a gate electrode is located in the Above the body region and the drift region; a source region located in the body region, the source region having the second conductivity type; a drain region located in the drift region, the drain region having the second conductivity type Conductivity type; a first isolation region located in the drift region between the source region and the drain region; a top doped region located below the first isolation region, the top doped region having the first A conductive type; a capacitor located above a well region; and a second isolation region located in the well region between the source region and the capacitor; wherein in the top view, the gate is a loop-shaped , The drain region is set in the back Inside the loop shape, the source region is disposed on the outside of the loop shape; wherein the loop shape has a gap, and the first isolation region and the second isolation region are connected at the gap, and the capacitor surrounds The gate. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of the patent application, wherein the gate electrode, the source region, and the capacitor are substantially coaxial. The laterally diffused metal-oxide-semiconductor field-effect transistor as described in item 1 of the scope of the patent application, further comprising: a buried layer located under the drift region or the well region, the buried layer having the second conductivity type, wherein The doping concentration of the buried layer is greater than the doping concentration of the drift region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 3 of the application, wherein the doping depth of the top doped region decreases linearly from one direction from the capacitor to the drain region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 3 of the scope of the patent application, wherein the doping concentration in the well region is greater than or equal to the doping concentration in the drift region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to any one of claims 1 to 5, further comprising: a base region located in the body region and adjacent to the source region, and the base electrode The region has the first conductivity type; and a pair of doped regions in the well region on both sides of the capacitor, the pair of doped regions has the first conductivity type. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 1 of the scope of the patent application, wherein the capacitor is circular, elliptical, or race track in the top view. A laterally diffused metal oxide semiconductor (LDMOS) field effect transistor includes: a substrate having a first conductivity type; a body region located above the substrate; the body region It has a first conductivity type; a drift region is located on the upper part of the substrate and is adjacent to the body region; the drift region has a second conductivity type opposite to the first conductivity type; a gate electrode is located at Above the body region and the drift region; a source region located in the body region, the source region having the second conductivity type; a drain region located in the drift region, the drain region having the first conductive region Two conductive types; a first isolation region located in the drift region adjacent to the drain region; a second isolation region located in the drift region adjacent to the gate electrode; a plurality of top doped regions located in the first region Below the isolation region and the second isolation region, the top doped regions have the first conductivity type; a capacitor is located above the drift region between the first isolation region and the second isolation region; and wherein In top view The drain region and the source region are interdigitated fingers, and the capacitor is adjacent to a tip of the source region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 8 of the patent application scope further includes: a source metal electrically connected to the source region; wherein the source metal covers the capacitor. The laterally diffused metal-oxide-semiconductor field-effect transistor according to item 9 of the scope of the patent application, wherein one edge of the source metal is kept at an equal distance from one edge of the drain region. The laterally diffused metal-oxide-semiconductor field-effect transistor according to any one of claims 8-10, further comprising: a base region located in the body region and adjacent to the source region, and the base electrode The region has this first conductivity type.