TW201338160A - Semiconductor structure and manufacturing process thereof - Google Patents

Abstract

A semiconductor structure includes a substrate having a firs conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxde is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and process thereof, and more particularly to a metal oxide semiconductor structure and process thereof.

In high voltage systems, it is important for the MOS device to have a high turn-off breakdown voltage and low on-state resistance during operation so that the semiconductor device can withstand higher voltages. More current flows between the drain and the source to reduce the power loss of the component. However, the high turn-off breakdown voltage is accompanied by a high on-resistance value, and the increase in the turn-off breakdown voltage also causes an increase in the on-resistance value. Therefore, when designing a semiconductor element, the turn-off breakdown voltage cannot be made to a maximum value. Therefore, how to improve the shutdown breakdown voltage of the semiconductor element and reduce the on-resistance during operation is a problem that the industry is eager to solve.

The invention relates to a semiconductor structure and a process thereof, which can reduce the impurity concentration adjacent to the 汲 extreme by doping impurities with opposite conductivity, so that it is easier to form a depletion region with the body region of the source terminal to obtain a higher Turn off the breakdown voltage with a lower on resistance.

According to an aspect of the invention, a semiconductor structure is provided, comprising a substrate of a first conductivity type, a first well region of a second conductivity type, a doped region of a second conductivity type, a field oxide, and a second conductivity The second well area of the type. The first well region is formed in the substrate. The doped region is formed in the first well region, and the doped region has a first impurity net concentration. Field oxides are formed in the surface region of the first well region. The second well region is located below the field oxide and is connected to one side of the doped region, wherein the second well region has a second impurity net concentration, and the second impurity net concentration is less than the first impurity net concentration.

According to another aspect of the invention, a semiconductor process is proposed comprising the following steps. A substrate of a first conductivity type is provided. A first well region of a second conductivity type is formed in the substrate. A doped region of a second conductivity type is formed in the first well region, the doped region having a first impurity net concentration. Forming a second well pattern of the second conductivity type in the doped region, the second well region is connected to one side of the doped region, and has a second impurity concentration, and the second impurity net concentration is less than the first impurity net concentration . An oxide is formed over the second well region.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The semiconductor structure of the present invention and its process are characterized by doping impurities of opposite conductivity to reduce the impurity concentration adjacent to the erbium terminal to obtain a drain-doped region such as a stepped impurity concentration, making it easier to source the source The body region forms a depletion zone. According to the low surface electric field (RESURF) effect, after forming the depletion region around the 汲 extreme, under the same distance conditions, a higher shutdown breakdown voltage and a lower conduction resistance value can be obtained, and the closer to the 汲 extreme, the impurity doping The higher the impurity concentration, the avoidance of the Kirk effect, thus maintaining a high breakdown voltage during operation.

The following is a detailed description of various embodiments, which are intended to be illustrative only and not to limit the scope of the invention.

Referring to FIG. 1, a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention is shown. The semiconductor structure is, for example, a double-diffused metal semiconductor structure including a substrate 110, a first well region 120, a source doped region 130, a drain doped region 140, a field oxide 150, and a field oxide 150. The second well zone 160 below. The substrate 110 is, for example, a P-type substrate 110, and the first well region 120 is, for example, an N-type well region, and the first well region 120 is formed in the substrate 110. Source doped region 130 and drain doped region 140 are located in first well region 120. The source doped region 130 includes a body region 131 and a heavily doped region 132. The body region 131 is, for example, a P-type body region, and the heavily doped region 132 is, for example, an N+ doped region and a P+ doped region, which may serve as a contact region of the source terminal 133 or a contact region of the base terminal 134, respectively. The surface of the drain doped region 140 has a heavily doped region 141, such as an N+ doped region, which can serve as a contact region for the germanium terminal 143. The field oxide 150 is formed in a surface region of the first well region 120 and between the source doping region 130 and the gate doping region 140, and is made of, for example, hafnium oxide. The field oxide 150 can also be a shallow trench isolation structure for isolating the source doped region 130 and the drain doped region 140.

Further, a gate structure 170 is formed on the body region 131, the channel region 190, and a portion of the field oxide 150. This embodiment modulates the voltage applied to the gate structure 170 to control the turn-on voltage of the semiconductor structure 100 or to turn off the semiconductor structure 100. In addition, when there is a bias between the voltage applied to the drain doping region 140 and the voltage applied to the source doping region 130, current may be applied to the drain doping region 140 and the source doping region 130. Flow between. For example, under high voltage operation, the drain doped region 140 is connected to a high voltage and the source doped region 130 is grounded.

In the present embodiment, the second well region 160 below the field oxide 150 is connected to one side of the gate doped region 140, and the second well region 160 has a second conductivity type impurity concentration. For example, the substrate 110 and the source doped region 130 have impurities of a first conductivity type, such as a P type, and the first well region 120, the drain doping region 140, and the second well region 160 have a first conductive The impurity of the second conductivity type of the opposite polarity is, for example, an N type. The drain doping region 140 has a first impurity net concentration, the second well region 160 has a second impurity net concentration, and the second impurity net concentration is less than the first impurity net concentration. In one embodiment, a second well region 160 may be formed by doping, for example, a P-type impurity into the partial drain doping region 140, so that the net impurity concentration of the second well region 160 is less than the gate doping region. The net concentration of impurities of 140.

Referring to FIG. 1 , a third well region 180 of the second conductivity type may be formed in the first well region 120 , and the second well region 160 is located between the third well region 180 and the gate doping region 140 . The Mitsui District 180 has a third impurity net concentration, and the third impurity net concentration is less than the second impurity net concentration. For example, a third well region 180 may be formed by doping, for example, a P-type impurity into a portion of the first well region 120 such that the net impurity concentration of the third well region 180 is less than the impurity of the gate doped region 140. Net concentration. In addition, the first well region 120 has a fourth impurity net concentration, and the fourth impurity net concentration is less than the net impurity concentration of the drain doping region 140, but greater than the net impurity concentration of the third well region 180.

If compared with the concentration of the impurities, the net concentration of the impurities of the second conductivity type is, for example, stepwise decreasing from the drain doping region 140 to the third well region 180. When the net concentration of impurities of the second conductivity type decreases stepwise, the more easily the depletion region is formed around the drain doping region 140, so that the gate doping region 140 can relatively withstand a higher breakdown voltage.

Next, please refer to FIGS. 2A and 2D, which respectively show schematic diagrams of a semiconductor process in accordance with an embodiment of the present invention. In FIG. 2A, a substrate 110 of a first conductivity type is provided and a first well region 120 of a second conductivity type is formed in the substrate 110. A doping process is performed to form a drain doped region 140 in the first well region 120, the drain doped region 140 having a first impurity net concentration. Next, in FIGS. 2B and 2C, for example, a photoresist 101 is used as a mask to shield a portion of the drain doping region 140, and a first conductivity type (eg, P-type) impurity doping process is performed to form a first The second well region 160 is in the partial drain doping region 140. The second well region 160 is connected to one side of the gate doped region 140 and has a net concentration of impurities of a second conductivity type (for example, N type), that is, a net concentration of the second impurity. The second impurity net concentration is less than the first impurity net concentration. Although the present invention is exemplified by the N-type drain doping region 140, the present invention is not limited thereto.

In addition, in FIG. 2C, a portion of the first well region 120 may be subjected to, for example, a P-type impurity implantation process to form a third well region 180 of the second conductivity type on one side of the second well region 160. The third well region 160 has a third impurity net concentration, and the third impurity net concentration is less than the second impurity net concentration. In this embodiment, the second well region and the third well region are formed, for example, in the same mask process.

In one embodiment, the second well region 160, the third well region 180, and the P-well doped region 182 are implanted with P-type impurities, for example, using the same mask process. Therefore, there is no need to increase the number of steps in the process or increase the cost of the mask.

In FIG. 2C, since the second well region 160 and the third well region 180 are doped with P-type impurities, the net concentration of impurities of the second conductivity type can be stepped down, so that it is easier to form a depletion region in the drain doping. Around the region 140, the drain doped region 140 is relatively resistant to higher breakdown voltages.

Next, referring to FIG. 2D, a thermal oxidation process is performed to form a field oxide 150 in the surface region of the first well region 120, and the second well region 160 and the third well region 180 are located below the field oxide 150. The field oxide 150 is used to isolate the source doping region 130 from the drain doping region 140. The field oxide 150 is connected, for example, to the N+ doping region 141 of the drain doping region 140, and to the source doping region 130. There is a channel zone 190 between them. In addition, a gate structure 170 can be formed on the body region 131 of the drain doping region 140, the channel region 190, and a portion of the field oxide 150. When the gate structure 170 turns on the semiconductor device and applies a bias voltage between the drain doping region 140 and the source doping region 130, a gate can be generated between the drain doping region 140 and the source doping region 130. Current flows through channel region 190. In one embodiment, since the second conductivity type impurity concentration of the third well region 180 is decreased to reduce the on-resistance value, resulting in higher gate current generation, the speed of operation can be increased.

Please refer to FIG. 3, which is a graph showing the value of the conduction resistance and the breakdown voltage. At the same breakdown voltage, the structure of the present invention has a lower on-resistance value than conventional structures. For example, when the breakdown voltage (Vbd) is 60V, the on-resistance (Ronsp) of the effective area can be reduced from 58 micro ohms to 48 micro ohms, and thus the quality factor (Ronsp/Vbd) is also reduced from 0.97 to 0.8. In other words, it is possible to maintain a high breakdown voltage while the size of the semiconductor is reduced, thereby increasing the yield and reducing the manufacturing cost.

The semiconductor structure 100 described above may be a metal oxide semiconductor device such as a vertical diffusion metal oxide semiconductor (VDMOS), a lateral double diffusion metal oxide semiconductor (LDMOS) or an enhanced diffusion gold oxide semiconductor (EDMOS) device. However, the invention is not limited thereto.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Semiconductor structure

101. . . Photoresist

110. . . Base

120. . . First well area

130. . . Source doping region

131. . . Body area

132. . . Heavily doped region

140. . . Bipolar doping zone

141. . . Heavily doped region

150. . . Field oxide

160. . . Second well area

170. . . Gate structure

180. . . Third well area

182. . . P-type well doped area

190. . . Channel area

1 is a schematic view of a semiconductor structure in accordance with an embodiment of the present invention.

2A and 2D are schematic views respectively showing a semiconductor process in accordance with an embodiment of the present invention.

Figure 3 is a graph showing the value of the conduction resistance and the breakdown voltage.

100. . . Semiconductor structure

110. . . Base

120. . . First well area

130. . . Source doping region

131. . . Body area

132. . . Heavily doped region

140. . . Bipolar doping zone

141. . . Heavily doped region

150. . . Field oxide

160. . . Second well area

170. . . Gate structure

180. . . Third well area

190. . . Channel area

Claims (10)

A semiconductor structure comprising:
a substrate of a first conductivity type;
a first well region of a second conductivity type formed in the substrate;
a doped region of a second conductivity type formed in the first well region, the doped region having a first impurity net concentration;
a field oxide formed in a surface region of the first well region; and a second well region of a second conductivity type under the field oxide and connected to one side of the doped region, wherein the second well The zone has a second impurity net concentration, and the second impurity net concentration is less than the first impurity net concentration. The semiconductor structure of claim 1, further comprising a third well region of a second conductivity type, the second well region being connected between the third well region and the doped region, and the third The well region has a third impurity net concentration, and the third impurity net concentration is less than the second impurity net concentration. The semiconductor structure of claim 2, wherein the first well region has a fourth impurity net concentration, and the fourth impurity net concentration is less than the first impurity net concentration and greater than the third impurity net concentration. The semiconductor structure of claim 2, wherein the net concentration of impurities of the second conductivity type is decreased from the doped region to the third well region. The semiconductor structure of claim 1, wherein the doped region is a drain doped region connected to one side of the field oxide. The semiconductor structure of claim 1, further comprising a gate structure disposed on a portion of the field oxide. A semiconductor process that includes:
Providing a substrate of a first conductivity type;
Forming a first well region of a second conductivity type in the substrate;
Forming a doping region of a second conductivity type in the first well region, the doping region having a first impurity net concentration;
Forming a second well pattern of a second conductivity type in the doped region, the second well region being connected to one side of the doped region, and having a second impurity net concentration, the second impurity net concentration being less than the a first impurity net concentration; and forming a field oxide above the second well region. The semiconductor process of claim 7, further comprising forming a third well region of a second conductivity type in the first well region, the second well region being connected to the third well region and the doping Between the zones, and the third well zone has a third impurity net concentration, the third impurity net concentration is less than the second impurity net concentration, wherein the step of forming the third conductivity type third well zone comprises the first The conductive impurity is doped in a portion of the first well region such that the third impurity net concentration is less than the second impurity net concentration, and the second well region and the third well region are formed in the same mask process. The semiconductor process of claim 8, wherein the first well region has a fourth impurity net concentration, and the fourth impurity net concentration is less than the first impurity net concentration and greater than the third impurity net concentration. The semiconductor process of claim 8, wherein a net concentration of impurities of the second conductivity type is decreased from the doped region to the third well region, the doped region being a drain doped region, connected The field oxide, the semiconductor process further includes forming a gate structure on a portion of the field oxide.