JP6064240B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a high breakdown voltage DMOS transistor, a high breakdown voltage CMOS transistor, and a low breakdown voltage CMOS transistor on a common semiconductor substrate, and a method for manufacturing the same.

2. Description of the Related Art Conventionally, a semiconductor device is known that includes a high breakdown voltage field effect transistor (DMOSFET) and a complementary field effect transistor (CMOSFET) on a common semiconductor substrate.
For example, the semiconductor device of Patent Document 1 includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. The epitaxial layer is separated into a DMOSFET formation region and a CMOSFET formation region.

The DMOSFET formation region includes a first DMOS body layer, a DMOS source layer and a second DMOS body layer formed adjacent to the DMOS body layer, a third well layer, and a third well layer. A DMOS drain layer formed in the well layer is formed.
In the CMOS formation region, a first well layer and a second well layer are formed adjacent to each other. A first CMOS source / drain layer is formed in the first well layer, and a second CMOS source / drain layer is formed in the second well layer.

JP 2000-232224 A

When the DMOSFET and the CMOSFET are provided on a common semiconductor substrate as in the semiconductor device of Patent Document 1, it is required to perform the process flow of each MOSFET in parallel as much as possible in order to simplify the manufacturing process.
By the way, when the DMOSFET is used for a panel controller IC, an LCD driver IC, or the like, it is necessary to have a specification capable of withstanding a high voltage. However, if the process flow of the DMOSFET and the CMOSFET is the same as described above, the impurity concentration of the well of the CMOSFET is high, so it is difficult to give the DMOSFET on the well constrained to that concentration sufficient voltage resistance. There is a bug that there is. As a result, as in Patent Document 1, it is necessary to separate the formation process of the first well layer and the second well layer in the CMOS formation region from the formation process of the first DMOS body layer in the DMOSFET formation region. The

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can easily manufacture a high-breakdown-voltage DMOS transistor without increasing the number of manufacturing steps.

  The semiconductor device of the present invention is a semiconductor device including a high breakdown voltage DMOS transistor, a high breakdown voltage CMOS transistor, and a low breakdown voltage CMOS transistor on a common first conductivity type semiconductor substrate, wherein the high breakdown voltage of the semiconductor substrate is provided. The high breakdown voltage first conductivity type well and the high breakdown voltage second conductivity type well formed in the CMOS transistor region and spaced apart from each other, and the low breakdown voltage CMOS transistor region in the semiconductor substrate are spaced from each other. Each having a higher impurity concentration than the high breakdown voltage first conductivity type well and the high breakdown voltage second conductivity type well, and higher than the high breakdown voltage first conductivity type well and the high breakdown voltage second conductivity type well. A low breakdown voltage first conductivity type well and a low breakdown voltage second conductivity type well formed in a shallow depth, and the high breakdown voltage DMOS transistor of the semiconductor substrate. A DMOS second conductivity type well having the same impurity concentration and depth as the high breakdown voltage second conductivity type well, and a DMOS second region formed in an inner region of the DMOS second conductivity type well. A first conductivity type body region; a DMOS second conductivity type source region formed in an inner region of the DMOS first conductivity type body region; and an inner region of the DMOS second conductivity type well; A DMOS second conductivity type drain region formed at a distance from the type body region, and a DMOS gate insulating film on a DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well The DMOS first conductivity type body region has the same impurity concentration and the same depth as the high breakdown voltage first conductivity type well. A double well structure is formed in a low concentration region and an inner region of the low concentration region, and includes a high concentration region having the same impurity concentration and the same depth as the low breakdown voltage first conductivity type well ( Claim 1).

  According to this configuration, since the region in contact with the DMOS second conductivity type well in the DMOS first conductivity type body region is the low concentration region, the junction breakdown voltage of the DMOS first conductivity type body region with respect to the DMOS second conductivity type well is improved. Can be made. Thereby, the breakdown voltage between the drain and the well can be improved. Furthermore, since the high concentration region is disposed inward of the low concentration region, the depletion layer generated from the pn junction between the low concentration region and the DMOS second conductivity type well can be made difficult to extend. Thereby, the punch-through breakdown voltage between the source and the drain can be improved.

  The semiconductor device of the present invention is a method for manufacturing a semiconductor device comprising a high breakdown voltage DMOS transistor, a high breakdown voltage CMOS transistor, and a low breakdown voltage CMOS transistor on a common first conductivity type semiconductor substrate. By selectively introducing a second conductivity type impurity into the region for the high voltage CMOS transistor and the region for the high voltage DMOS transistor of the substrate, the high voltage second conductivity type is introduced into the region for the high voltage CMOS transistor. Forming a well at the same time, forming a DMOS second conductivity type well in the region for the high breakdown voltage DMOS transistor, and forming the region for the high breakdown voltage CMOS transistor on the semiconductor substrate and the DMOS second conductivity type well. By selectively introducing a first conductivity type impurity into the first region, the high breakdown voltage CMO Forming a high breakdown voltage first conductivity type well in the transistor region and simultaneously forming a low concentration region in the DMOS second conductivity type well; and forming the low breakdown voltage CMOS transistor region and the low voltage region on the semiconductor substrate; By selectively introducing a first conductivity type impurity into the inner region of the concentration region, a low breakdown voltage first conductivity type well is formed in the region for the low breakdown voltage CMOS transistor, and at the same time, A high concentration region having a higher impurity concentration than the low concentration region and shallower than the low concentration region is formed, and the low concentration region and the high concentration region are formed in an inner region of the DMOS second conductivity type well. Including a step of forming a DMOS first conductivity type body region having a double well structure including a second conductivity type impurity in the region for the low breakdown voltage CMOS transistor of the semiconductor substrate. Selectively introducing a low breakdown voltage second conductivity type well and selectively introducing a second conductivity type impurity into an inner region of the DMOS second conductivity type well, thereby forming a DMOS first. Forming a second conductivity type drain region and forming a DMOS second conductivity type source region by selectively introducing a second conductivity type impurity into an inner region of the DMOS first conductivity type body region; And a step of forming a DMOS gate electrode on the DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well via a DMOS gate insulating film. It can be produced by the method (claim 9).

  According to this method, the low-concentration region of the DMOS first conductivity type body region can be formed in the same process as the high breakdown voltage first conductivity type well of the high breakdown voltage CMOS transistor. The concentration region can be formed in the same process as the low breakdown voltage first conductivity type well of the low breakdown voltage CMOS transistor. That is, the above-described high voltage DMOS transistor can be easily manufactured by changing the mask layout without increasing the number of processes. Therefore, this method makes it possible to easily manufacture a high voltage DMOS transistor necessary for a panel controller IC, an LCD driver IC, or the like.

The low concentration region is preferably formed in a polygonal shape having a plurality of rounded corners in a plan view of the semiconductor substrate as viewed from the surface side (Claim 2).
According to this configuration, by concentrating the low-concentration region that forms the outer shape of the DMOS first conductivity type body region, it is possible to reduce electric field concentration at the corners of the DMOS first conductivity type body region. As a result, the breakdown voltage of the semiconductor device can be further improved.

In this case, it is preferable that the high concentration region is also formed in a polygonal shape having a plurality of rounded corners when the semiconductor substrate is viewed from the front side. With this configuration, the breakdown voltage of the semiconductor device can be further improved.
The DMOS channel region is formed across the low concentration region and the high concentration region, and the DMOS gate electrode is disposed so as to cross a boundary between the low concentration region and the high concentration region in the DMOS channel region. (Claim 4).

In this case, it is preferable that the low-concentration region is formed so that a portion where the DMOS channel region is formed is selectively wider than other portions in a plan view of the semiconductor substrate as viewed from the front side ( Claim 5).
The DMOS second conductivity type drain region is preferably formed with the same impurity concentration and the same depth as the low breakdown voltage second conductivity type well.

This configuration is obtained by simultaneously performing the step of forming the low breakdown voltage second conductivity type well and the step of forming the DMOS second conductivity type drain region in the method of manufacturing the semiconductor device. Item 10). By this method, the manufacturing process of the semiconductor device can be further simplified.
The semiconductor device has an STI (Shallow Trench Isolation) structure in which an insulator is embedded in a trench dug down from the surface of the semiconductor substrate, and the high breakdown voltage DMOS transistor, the high breakdown voltage CMOS transistor, and the low breakdown voltage CMOS transistor The element isolation | separation part which divides the area | region for each may be included (Claim 7).

The low breakdown voltage first conductivity type well and the low breakdown voltage second conductivity type well are each surrounded and divided by the element isolation part, and the low breakdown voltage first conductivity type well surrounded by the element isolation part. May be 1 μm to 5 μm, and the size of the low breakdown voltage second conductivity type well surrounded by the element isolation part may be 1 μm to 10 μm .

1A and 1B are schematic views of a semiconductor device according to an embodiment of the present invention. FIG. 1A is an overall cross-sectional view, and FIG. 1B is a plan view of an HV-DMOS region. FIG. 2 is a schematic view showing a part of the manufacturing process of the semiconductor device. FIG. 3 is a schematic view showing the next step of FIG. FIG. 4 is a schematic diagram showing the next step of FIG. FIG. 5 is a schematic view showing the next step of FIG. FIG. 6 is a schematic view showing the next step of FIG. FIG. 7 is a schematic view showing the next step of FIG. FIG. 8 is a schematic view showing the next step of FIG. FIG. 9 is a schematic view showing the next step of FIG. FIG. 10 is a schematic view showing the next step of FIG. FIG. 11 is a schematic view showing the next step of FIG. FIG. 12 is a schematic view showing the next step of FIG. FIG. 13 is a schematic view showing the next step of FIG. FIG. 14 is a schematic view showing the next step of FIG. FIG. 15 is a schematic view showing the next step of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1A and 1B are schematic views of a semiconductor device according to an embodiment of the present invention. FIG. 1A is an overall cross-sectional view, and FIG. 1B is a plan view of an HV-DMOS.
The semiconductor device 1 includes an HV-DMOS (High Voltage-Double Diffused Metal Oxide Semiconductor) 2 as an example of a high-voltage DMOS transistor of the present invention and an HV-CMOS (High Voltage--as an example of a high-voltage CMOS transistor of the present invention. Complementary Metal Oxide Semiconductor) 3 and LV-CMOS 4 as an example of the low breakdown voltage CMOS transistor of the present invention are provided on a common p-type semiconductor substrate (for example, silicon substrate) 5. The HV-CMOS 3 includes an HV-nMOS 6 and an HV-pMOS 7, and the LV-CMOS 4 includes an LV-nMOS 8 and an LV-pMOS 9.

On the surface portion of the semiconductor substrate 5, an element isolation portion 10 for isolating the HV-DMOS 2, the HV-nMOS 6, the HV-pMOS 7, the LV-nMOS 8 and the LV-pMOS 9 from each other is formed. The element isolation unit 10 surrounds the regions where the HV-DMOS 2, the HV-nMOS 6, the HV-pMOS 7, the LV-nMOS 8 and the LV-pMOS 9 are respectively formed in a rectangular shape. In the element isolation portion 10, an insulating material such as silicon oxide (SiO ₂ ) is provided in a groove (for example, a shallow trench having a depth of 0.2 μm to 0.5 μm) dug relatively shallowly from the surface of the semiconductor substrate 5. It has an embedded structure (STI structure).

The size of the region for the HV-DMOS 2 partitioned by the element isolation unit 10 is, for example, 20 μm to 40 μm.
The size of the area for HV-CMOS 3 is, for example, 20 μm to 100 μm. More specifically, the size of the region for HV-nMOS 6 is 20 μm to 60 μm, and the size of the region for HV-pMOS 7 is 20 μm to 100 μm.

The size of the region for LV-CMOS 4 is, for example, 1 μm to 10 μm. More specifically, the size of the region for LV-nMOS 8 is 1 μm to 5 μm, and the size of the region for LV-pMOS 9 is 1 μm to 10 μm.
A deep n-type well 11 as an example of the DMOS second conductivity type well of the present invention is formed in the region for the HV-DMOS 2 along the side of the element isolation portion 10 surrounding the region in a rectangular shape.

In the inner region of the deep n-type well 11, a DMOS-p type body region 12 as an example of the DMOS first conductivity type body region of the present invention and a DMOS as an example of the DMOS second conductivity type drain region of the present invention The n-type drain region 13 is formed along the surface of the semiconductor substrate 5 so as to be spaced from each other.
The DMOS-p type body region 12 is formed in a well shape in the deep n-type well 11, formed in a well shape in a low concentration region 14 having a relatively low impurity concentration, and in an inner region of the low concentration region 14, It has a double well structure including a high concentration region 15 having a relatively high impurity concentration compared to the low concentration region 14.

  As shown in FIG. 1B, both the low concentration region 14 and the high concentration region 15 are formed in a quadrangular shape having rounded corners when the semiconductor substrate 5 is viewed from the surface side. Has been. The low-concentration region 14 and the high-concentration region 15 may be other polygonal shapes such as a triangular shape, a pentagonal shape, a hexagonal shape having a plurality of rounded corners, a circular shape, an elliptical shape, or the like. Etc. Moreover, it is not necessary for all of the plurality of corners to be rounded, and only some of the corners may be rounded.

  In the inner region of the high concentration region 15, the DMOS second conductivity type of the present invention is spaced apart from the boundary between the high concentration region 15 and the low concentration region 14 on the side away from the DMOS-n type drain region 13. A DMOS-n type source region 16 is formed as an example of the source region. A region between the DMOS-n type source region 16 and the deep n type well 11 is a channel region (DMOS channel region 17) of the DMOS-p type body region 12. In this embodiment, the DMOS channel region 17 (hatched portion in FIG. 1B) is formed across the low concentration region 14 and the high concentration region 15.

Further, the high concentration region 15 is arranged so as to be shifted to the far side of the low concentration region 14 on the side closer to and far from the DMOS-n drain region 13 facing each other in the plan view. . As a result, the lightly doped region 14 forming the DMOS channel region 17 is selectively wider than the lightly doped regions 14 of other regions.
A LOCOS oxide film 18 is formed on the surface of the semiconductor substrate 5 so as to sandwich the DMOS-n type drain region 13 from both sides of the DMOS-p type body region 12 and the opposite side of the DMOS-n type drain region 13. Is formed. A DMOS-n drift region 19 is formed below each LOCOS oxide film 18 so as to be in contact with the LOCOS oxide film 18. The DMOS-n type drift region 19 is formed shallower than the DMOS-n type drain region 13.

  On the surface portions of the DMOS-p type body region 12 and the DMOS-n type drain region 13, a DMOS body contact region 20 and a DMOS drain contact region 21 formed by diffusing impurities at a high concentration are formed. The DMOS body contact region 20 is formed in contact with the DMOS-n type source region 16 on the opposite side of the DMOS channel region 17 with respect to the DMOS-n type source region 16.

A DMOS gate insulating film 22 is formed on the surface of the semiconductor substrate 5 in the region for the HV-DMOS 2. A DMOS gate electrode 23 is formed so as to face the DMOS channel region 17 with the DMOS gate insulating film 22 interposed therebetween.
In this embodiment, the DMOS gate electrode 23 is formed so as to straddle the LOCOS oxide film 18 and the DMOS gate insulating film 22, and further disposed across the boundary between the low concentration region 14 and the high concentration region 15 in the DMOS channel region 17. Has been. An end portion (edge portion) on the drain side of the DMOS gate electrode 23 is disposed on the LOCOS oxide film 18 at a distance from the DMOS-n type drain region 13. On the other hand, the end portion (edge portion) on the source side of the DMOS gate electrode 23 is disposed on the high concentration region 15 at a distance from the DMOS-n type source region 16.

Further, both side surfaces of the DMOS gate electrode 23 are covered with sidewalls 24 made of an insulator such as silicon oxide (SiO ₂ ). An n-type low concentration layer 25 is formed between the DMOS-n type source region 16 and the DMOS gate electrode 23, that is, in a region immediately below the sidewall 24. Thus, the LDD structure is formed. The n-type low concentration layer 25 is a region that is formed at a lower concentration than the DMOS-n type source region 16 and is formed by implanting impurity ions shallower than these. The n-type low concentration layer 25 is formed in a self-aligned manner with respect to the DMOS gate electrode 23, and the DMOS-n-type source region 16 is formed in a self-aligned manner with respect to the sidewall 24.

In the HV-nMOS 6 region of the HV-CMOS 3, a deep p-type well 26 as an example of the high breakdown voltage first conductivity type well of the present invention is provided along the side of the element isolation portion 10 surrounding the region in a rectangular shape. Is formed. The deep p-type well 26 is formed with the same impurity concentration and the same depth as the low-concentration region 14 of the DMOS-p-type body region 12.
In the inner region of the deep p-type well 26, an HV-n type source region 27 and an HV-n type drain region 28 are formed along the surface of the semiconductor substrate 5 and spaced from each other. A region between the HV-n type source region 27 and the HV-n type drain region 28 is a channel region (HV-n type channel region 29) of the deep p-type well 26. The HV-n type source region 27 and the HV-n type drain region 28 are formed with the same impurity concentration and the same depth as the DMOS-n type drain region 13.

An HV-n type source contact region 30 and an HV-n type drain contact region 31 formed by diffusing impurities at high concentrations on the surface portions of the HV-n type source region 27 and the HV-n type drain region 28, respectively. Is formed.
A LOCOS oxide film 32 is formed on the surface of the semiconductor substrate 5 so as to sandwich the HV-n type source region 27 from both sides of the HV-n type drain region 28 and the opposite side of the HV-n type source region 27. Is formed. Further, a LOCOS oxide film 33 is formed so as to sandwich the HV-n type drain region 28 from both sides of the HV-n type source region 27 and the opposite side of the HV-n type drain region 28. An HV-n type drift region 34 is formed below the LOCOS oxide films 32 and 33 so as to be in contact with the LOCOS oxide films 32 and 33. The HV-n type drift region 34 is formed shallower than the HV-n type source region 27 and the HV-n type drain region 28.

An HV-nMOS gate insulating film 35 is formed on the surface of the semiconductor substrate 5 in the region for the HV-nMOS 6. An HV-nMOS gate electrode 36 is formed so as to face the HV-n type channel region 29 with the HV-nMOS gate insulating film 35 interposed therebetween.
In this embodiment, the HV-nMOS gate electrode 36 is formed across the LOCOS oxide film 32 and the LOCOS oxide film 33. An end portion (edge portion) on the drain side of the HV-nMOS gate electrode 36 is disposed on the LOCOS oxide film 33 at a distance from the HV-n type drain region 28. On the other hand, the end portion (edge portion) on the source side of the HV-nMOS gate electrode 36 is disposed on the LOCOS oxide film 32 at a distance from the HV-n type source region 27. Further, both side surfaces of the HV-nMOS gate electrode 36 are covered with sidewalls 37 made of an insulator such as silicon oxide (SiO ₂ ).

In the HV-pMOS 7 region of the HV-CMOS 3, a deep n-type well 38 as an example of the high breakdown voltage second conductivity type well of the present invention is provided along the side of the element isolation portion 10 surrounding the region in a rectangular shape. Is formed. The deep n-type well 38 is formed with the same impurity concentration and the same depth as the deep n-type well 11 of the HV-DMOS 2.
In the inner region of the deep n-type well 38, an HV-p type source region 39 and an HV-p type drain region 40 are formed along the surface of the semiconductor substrate 5 so as to be spaced from each other. A region between the HV-p type source region 39 and the HV-p type drain region 40 is a channel region (HV-p type channel region 41) of the deep n-type well 38. The HV-p type source region 39 and the HV-p type drain region 40 are formed with the same impurity concentration and the same depth as the high concentration region 15 of the DMOS-p type body region 12.

The HV-p type source contact region 42 and the HV-p type drain contact region 43 formed by diffusing impurities at a high concentration on the surface portions of the HV-p type source region 39 and the HV-p type drain region 40, respectively. Is formed.
A LOCOS oxide film 44 is formed on the surface of the semiconductor substrate 5 so as to sandwich the HV-p type source region 39 from both sides of the HV-p type drain region 40 and the opposite side of the HV-p type source region 39. Is formed. Further, a LOCOS oxide film 45 is formed so as to sandwich the HV-p type drain region 40 from both sides of the HV-p type source region 39 and the opposite side of the HV-p type drain region 40. Under each LOCOS oxide film 44, 45, an HV-p drift region 46 is formed so as to be in contact with the LOCOS oxide films 44, 45. The HV-p type drift region 46 is formed shallower than the HV-p type source region 39 and the HV-p type drain region 40.

An HV-pMOS gate insulating film 47 is formed on the surface of the semiconductor substrate 5 in the region for the HV-pMOS 7. An HV-pMOS gate electrode 48 is formed so as to face the HV-p-type channel region 41 with the HV-pMOS gate insulating film 47 interposed therebetween.
In this embodiment, the HV-pMOS gate electrode 48 is formed across the LOCOS oxide film 44 and the LOCOS oxide film 45. An end portion (edge portion) on the drain side of the HV-pMOS gate electrode 48 is disposed on the LOCOS oxide film 45 at a distance from the HV-p type drain region 40. On the other hand, the end portion (edge portion) on the source side of the HV-pMOS gate electrode 48 is disposed on the LOCOS oxide film 44 at a distance from the HV-p type source region 39. Further, both side surfaces of the HV-pMOS gate electrode 48 are covered with sidewalls 49 made of an insulator such as silicon oxide (SiO ₂ ).

  In the region for the LV-nMOS 8 of the LV-CMOS 4, a p-type well 50 as an example of the low breakdown voltage first conductivity type well of the present invention is formed along the side of the element isolation portion 10 surrounding the region in a rectangular shape. Has been. The p-type well 50 has a higher impurity concentration than the low-concentration region 14 and the deep p-type well 26 of the DMOS-p-type body region 12 and is shallower than the low-concentration region 14 and the deep p-type well 26. . The p-type well 50 is formed with the same impurity concentration and the same depth as those of the high-concentration region 15, the HV-p-type source region 39 and the HV-p-type drain region 40 of the DMOS-p-type body region 12.

In the inner region of the p-type well 50, an LV-n type source region 51 and an LV-n type drain region 52 are formed along the surface of the semiconductor substrate 5 and spaced from each other. A region between the LV-n source region 51 and the LV-n drain region 52 is a channel region (LV-n channel region 53) of the p-type well 50.
An LV-nMOS gate insulating film 54 is formed on the surface of the semiconductor substrate 5 in the region for the LV-nMOS 8. An LV-nMOS gate electrode 55 is formed so as to face the LV-n type channel region 53 with the LV-nMOS gate insulating film 54 interposed therebetween.

Both side surfaces of the LV-nMOS gate electrode 55 are covered with sidewalls 56 made of an insulator such as silicon oxide (SiO ₂ ). N-type low concentration layers 57 and 58 are formed between the LV-n type source region 51 and the LV-n type drain region 52 and the LV-nMOS gate electrode 55, that is, in a region immediately below the sidewall 56. Yes. Thus, the LDD structure is formed. The n-type low concentration layers 57 and 58 are regions formed at a lower concentration than the LV-n type source / drain regions 51 and 52 and implanted by impurity ions shallower than these. The n-type low concentration layers 57 and 58 are formed in a self-aligned manner with respect to the LV-nMOS gate electrode 55, and the LV-n-type source / drain regions 51 and 52 are self-aligned with respect to the sidewall 56. Is formed.

  In the region for the LV-pMOS 9 of the LV-CMOS 4, an n-type well 59 as an example of the low breakdown voltage second conductivity type well of the present invention is formed along the side of the element isolation portion 10 surrounding the region in a rectangular shape. Has been. The n-type well 59 has a higher impurity concentration than the deep n-type well 11 and the deep n-type well 38 and is shallower than the deep n-type well 11 and the deep n-type well 38. The n-type well 59 is formed with the same impurity concentration and the same depth as those of the DMOS-n-type drain region 13, the HV-n-type source region 27 and the HV-n-type drain region 28.

In the inner region of the n-type well 59, an LV-p type source region 60 and an LV-p type drain region 61 are formed along the surface of the semiconductor substrate 5 and spaced from each other. A region between the LV-p type source region 60 and the LV-p type drain region 61 is a channel region (LV-p type channel region 62) of the n-type well 59.
An LV-pMOS gate insulating film 63 is formed on the surface of the semiconductor substrate 5 in the region for the LV-pMOS 9. An LV-pMOS gate electrode 64 is formed so as to face the LV-p type channel region 62 with the LV-pMOS gate insulating film 63 interposed therebetween.

Both side surfaces of the LV-pMOS gate electrode 64 are covered with sidewalls 65 made of an insulator such as silicon oxide (SiO ₂ ). P-type low concentration layers 66 and 67 are formed between the LV-p type source region 60 and the LV-p type drain region 61 and the LV-pMOS gate electrode 64, that is, in a region immediately below the sidewall 65. Yes. Thus, the LDD structure is formed. The p-type low-concentration layers 66 and 67 are regions formed at a lower concentration than the LV-p-type source / drain regions 60 and 61 and implanted by impurity ions shallower than these. The p-type low concentration layers 66 and 67 are formed in a self-aligned manner with respect to the LV-pMOS gate electrode 64, and the LV-p-type source / drain regions 60 and 61 are self-aligned with respect to the sidewall 65. Is formed.

An interlayer film 68 made of an insulator such as silicon oxide (SiO ₂ ) is stacked on the semiconductor substrate 6. On the interlayer film 68, source wirings 69 to 73, drain wirings 74 to 78, and gate wirings 79 to 83 made of a conductive material such as aluminum (Al) are formed.
The source wirings 69 to 73 are connected to the DMOS-n type source region 16, the DMOS body contact region 20, the HV-n type source contact region 30, and the HV-p type source contact region 42 through contact plugs that penetrate the interlayer film 68. , LV-n type source region 51 and LV-p type source region 60, respectively.

The drain wirings 74 to 78 are connected to the DMOS drain contact region 21, the HV-n type drain contact region 31, the HV-p type drain contact region 43, and the LV-n type drain region 52 through contact plugs that penetrate the interlayer film 68. And LV-p type drain region 61, respectively.
The gate wirings 79 to 83 are connected to the DMOS gate electrode 23, the HV-nMOS gate electrode 36, the HV-pMOS gate electrode 48, the LV-nMOS gate electrode 55 and the LV-pMOS gate electrode through contact plugs that penetrate the interlayer film 68. 64 respectively.

Details of each part of the semiconductor device 1 will be described below.
The semiconductor substrate 5 is p-type having an impurity concentration of 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁵ cm ⁻³ , for example. The thickness of the semiconductor substrate 5 is, for example, 600 μm to 900 μm.
The deep n-type well 11 and the deep n-type well 38 are n-type having an impurity concentration of, for example, 5 × 10 ¹⁴ cm ^{−3 to} 3 × 10 ¹⁵ cm ⁻³ . The depth from the surface of the semiconductor substrate 5 to the deepest part of the deep n-type wells 11 and 38 is, for example, 2 μm to 3 μm.

The DMOS-n type drain region 13, the HV-n type source region 27, the HV-n type drain region 28, and the n type well 59 have an impurity concentration of, for example, 5 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁶ cm ⁻³ . N-type. The depth from the surface of the semiconductor substrate 5 to the deepest part of the DMOS-n type drain region 13, the HV-n type source region 27, the HV-n type drain region 28 and the n type well 59 is, for example, 1 μm to 1.5 μm. It is.

The low concentration region 14 and the deep p-type well 26 are p-type having an impurity concentration of 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁵ cm ⁻³ , for example. The depth from the surface of the semiconductor substrate 5 to the deepest part of the low concentration region 14 and the deep p-type well 26 is, for example, 1.5 μm to 2 μm.
The high concentration region 15, the HV-p type source region 39, the HV-p type drain region 40, and the p type well 50 are, for example, p having an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁶ cm ^−3. It is a type. The depth from the surface of the semiconductor substrate 5 to the deepest portion of the high concentration region 15, the HV-p type source region 39, the HV-p type drain region 40 and the p type well 50 is, for example, 0.8 μm to 1.2 μm. is there.

The DMOS-n type source region 16, the DMOS drain contact region 21, the HV-n type source contact region 30, the HV-n type drain contact region 31, the LV-n type source region 51 and the LV-n type drain region 52 are, for example, It is an n ⁺ type having an impurity concentration of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ .
The DMOS body contact region 20, the HV-p type source contact region 42, the HV-p type drain contact region 43, the LV-p type source region 60, and the LV-p type drain region 61 are, for example, 1 × 10 ¹⁸ cm ^−3. It is a p ⁺ type having an impurity concentration of ˜3 × 10 ¹⁸ cm ⁻³ .

The DMOS-n type drift region 19 and the HV-n type drift region 34 are, for example, n ⁺ type having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ .
The HV-p type drift region 46 is ap ⁺ type having an impurity concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁶ cm ⁻³ , for example.
The thickness of the LOCOS oxide films 18, 32, 33, 44, and 45 is, for example, 2000 to 3000 mm.

The thicknesses of the DMOS gate insulating film 22, the HV-nMOS gate insulating film 35, and the HV-pMOS gate insulating film 47 are, for example, 1000 mm to 1500 mm.
The thicknesses of the LV-nMOS gate insulating film 54 and the LV-pMOS gate insulating film 63 are, for example, 80 to 150 mm.
The thicknesses of the DMOS gate electrode 23, the HV-nMOS gate electrode 36, the HV-pMOS gate electrode 48, the LV-nMOS gate electrode 55, and the LV-pMOS gate electrode 64 are, for example, 2000 to 3000 mm.

2 to 15 are schematic diagrams for explaining a part of the manufacturing process of the semiconductor device 1 of FIG. 2 to 15, (a) corresponds to FIG. 1 (a), and (b) corresponds to FIG. 1 (b).
First, as shown in FIG. 2, the element isolation part 10 is formed in the semiconductor substrate 5 by the STI method. Thereby, each active area for HV-DMOS2, HV-nMOS6, HV-pMOS7, LV-nMOS8 and LV-pMOS9 is secured.

Next, as shown in FIG. 3, a deep n-type well 11 and a deep n-type well 38 are formed. Specifically, a resist film (not shown) having a predetermined pattern is formed on the semiconductor substrate 5, and the resist film is used as a mask to form n n in the region where the deep n-type well 11 and the deep n-type well 38 are to be formed. Type impurity ions are selectively implanted into the semiconductor substrate 5. For example, As ⁺ ions or P ⁺ ions are used as n-type impurity ions (hereinafter the same). Thus, the deep n-type well 11 and the deep n-type well 38 are formed simultaneously.

Next, as shown in FIG. 4, a process of forming the low concentration region 14 and the deep p-type well 26 is performed. Specifically, a resist film 84 having a predetermined pattern is formed on the semiconductor substrate 5, and p-type impurity ions are formed in regions where the low concentration region 14 and the deep p-type well 26 are to be formed using the resist film 84 as a mask. It is selectively implanted into the semiconductor substrate 5. For example, B ⁺ ions are used as p-type impurities (hereinafter the same). At this time, the low concentration region 14 and the deep p-type well 26 are formed shallower than the deep n-type well 11 and the deep n-type well 38 by controlling the acceleration of implantation and thermal diffusion conditions. Thus, the low concentration region 14 and the deep p-type well 26 are formed simultaneously.

Next, as shown in FIG. 5, a hard mask 85 (for example, a SiN film of about 1000 mm) is laminated on the semiconductor substrate 5 (hatched portion in FIG. 5B), and patterned to form the hard mask 85. The portions where the LOCOS oxide films 18, 32, 33, 44, 45 are to be formed are selectively removed.
Next, as shown in FIG. 6, a resist film (not shown) having a predetermined pattern that selectively covers the region for HV-DMOS 2, the region for HV-nMOS 6, and the region for LV-CMOS 4 is formed on the semiconductor substrate 5. Using the resist film and the hard mask 85 as a mask, p-type impurity ions are selectively implanted into the semiconductor substrate 5 that is selectively exposed from the hard mask 85. Thus, the HV-p type drift region 46 is formed.

  Similarly, a resist film 86 having a predetermined pattern that selectively covers the low concentration region 14, the region for HV-pMOS 7, and the region for LV-CMOS 4 is formed on the semiconductor substrate 5. As a mask, n-type impurity ions are selectively implanted into the semiconductor substrate 5 exposed from the hard mask 85. Thus, the DMOS-n type drift region 19 and the HV-n type drift region 34 are formed.

Next, as shown in FIG. 7, the LOCOS oxide films 18, 32, 33, 44, and 45 are simultaneously formed by selectively thermally oxidizing the semiconductor substrate 5 exposed from the hard mask 85.
Next, as shown in FIG. 8, a resist film 87 is laminated on the semiconductor substrate 5 and patterned to form the HV-nMOS gate insulating film 35 and the HV-pMOS gate insulating film 47 of the resist film 87. Parts are selectively removed. Then, the hard mask 85 exposed from the resist film 87 is selectively removed using the resist film 87 as a mask.

Next, as shown in FIG. 9, by selectively thermally oxidizing the semiconductor substrate 5 exposed from the hard mask 85, the HV-nMOS gate insulating film 35 and the HV-pMOS gate insulating film 47 are simultaneously formed. The Thereafter, the hard mask 85 is removed.
Next, as shown in FIG. 10, the step of simultaneously forming the DMOS-n type drain region 13, the HV-n type source region 27, the HV-n type drain region 28 and the n type well 59, the high concentration region 15, The step of simultaneously forming the HV-p type source region 39, the HV-p type drain region 40 and the p type well 50 is performed.

  Specifically, a resist film (not shown) having a predetermined pattern is formed on the semiconductor substrate 5, and using the resist film as a mask, the DMOS-n type drain region 13, the HV-n type source region 27, and the HV- N-type impurity ions are selectively implanted into the semiconductor substrate 5 in regions where the n-type drain region 28 and the n-type well 59 are to be formed. Thus, the DMOS-n type drain region 13, the HV-n type source region 27, the HV-n type drain region 28, and the n type well 59 are formed simultaneously.

  Similarly, a resist film 88 having a predetermined pattern is formed on the semiconductor substrate 5, and using the resist film 88 as a mask, the high concentration region 15, the HV-p type source region 39, the HV-p type drain region 40, and the p type. P-type impurity ions are selectively implanted into the semiconductor substrate 5 in the region where the well 50 is to be formed. At this time, the high concentration region 15 is formed shallower than the low concentration region 14 by controlling the acceleration of implantation and the thermal diffusion conditions. Thus, the high concentration region 15, the HV-p type source region 39, the HV-p type drain region 40, and the p type well 50 are formed simultaneously.

Next, as shown in FIG. 11, the DMOS gate insulating film 22, the LV-nMOS gate insulating film 54, and the LV-pMOS gate insulating film 63 are simultaneously formed by selectively thermally oxidizing the semiconductor substrate 5. Then, a polysilicon material 89 is deposited on the semiconductor substrate 5.
Next, as shown in FIG. 12, a resist film 90 having a predetermined pattern is formed on the polysilicon material 89, and the polysilicon material 89 is selectively removed using the resist film 90 as a mask. Thus, the DMOS gate electrode 23, the HV-nMOS gate electrode 36, the HV-pMOS gate electrode 48, the LV-nMOS gate electrode 55 and the LV-pMOS gate electrode 64 are formed simultaneously.

Next, as shown in FIG. 13, a resist film (not shown) having a predetermined pattern is formed on the semiconductor substrate 5, and p-type low concentration layers 66 and 67 are to be formed using the resist film as a mask. Then, p-type impurity ions are selectively implanted into the semiconductor substrate 5. Thus, the p-type low concentration layers 66 and 67 are formed simultaneously.
Similarly, a resist film 91 having a predetermined pattern is formed on the semiconductor substrate 5. Using the resist film 91 as a mask, n-type impurity ions are formed in regions where the n-type low concentration layers 25, 57 and 58 are to be formed. 5 is selectively injected. Thus, the n-type low concentration layers 25, 57 and 58 are formed simultaneously.

Next, as shown in FIG. 14, after an insulating film such as a silicon oxide (SiO ₂ ) film or a silicon nitride (SiN) film is deposited on the entire surface of the semiconductor substrate 5 by a CVD method, Is etched back by dry etching. When this etch back is performed until the gate electrodes 23, 36, 48, 55, and 64 are exposed, sidewalls 24, 37, 49, 56, and 65 are simultaneously formed on both side surfaces thereof.

  Next, as shown in FIG. 15, a resist film (not shown) having a predetermined pattern is formed on the semiconductor substrate 5, and the DMOS-n type source region 16 and the DMOS drain contact region 21 are formed using the resist film as a mask. , HV-n type source contact region 30, HV-n type drain contact region 31, LV-n type source region 51 and LV-n type drain region 52 are selected as n type impurity ions in semiconductor substrate 5 Injected. Thus, the DMOS-n type source region 16, the DMOS drain contact region 21, the HV-n type source contact region 30, the HV-n type drain contact region 31, the LV-n type source region 51, and the LV-n type drain region 52 are formed. Formed simultaneously.

  Similarly, a resist film 92 having a predetermined pattern is formed on the semiconductor substrate 5, and using the resist film 92 as a mask, the DMOS body contact region 20, the HV-p type source contact region 42, and the HV-p type drain contact region 43. The p-type impurity ions are selectively implanted into the semiconductor substrate 5 in the regions where the LV-p type source region 60 and the LV-p type drain region 61 are to be formed. Thus, the DMOS body contact region 20, the HV-p type source contact region 42, the HV-p type drain contact region 43, the LV-p type source region 60, and the LV-p type drain region 61 are formed simultaneously.

  Thereafter, an interlayer film 68 covering the entire surface of the semiconductor substrate 5 is formed, a plurality of contact holes are formed in the interlayer film 68 by etching, and contact plugs are embedded in these contact holes. Then, the semiconductor device 1 shown in FIG. 1 is obtained through the above steps in which the source wirings 69 to 73, the drain wirings 74 to 78, and the gate wirings 79 to 83 are formed on the interlayer film 68.

  As described above, according to this semiconductor device 1, in the DMOS-p type body region 12, the region in contact with the deep n-type well 11 of the HV-DMOS 2 is the low concentration region 14. Thus, by bringing the low-concentration region 14 and the deep n-type well 11 having a relatively low concentration into contact with each other, the junction breakdown voltage of the DMOS-p-type body region 12 with respect to the deep n-type well 11 can be improved. Thereby, the breakdown voltage between the drain and the well can be improved.

Furthermore, since the high concentration region 15 is disposed inside the low concentration region 14, the depletion layer generated from the pn junction between the low concentration region 14 and the deep n-type well 11 can be made difficult to extend. Thereby, the punch-through breakdown voltage between the source and the drain can be improved.
In addition, by concentrating the low-concentration region 14 that forms the outer shape of the DMOS-p-type body region 12, electric field concentration at the corners of the DMOS-p-type body region 12 can be reduced. As a result, the breakdown voltage of the semiconductor device 1 can be further improved.

  2 to 15, the low concentration region 14 of the DMOS-p type body region 12 can be formed in the same process as the deep p type well 26 of the HV-CMOS 3 (see FIG. 4). ), The high concentration region 15 of the DMOS-p type body region 12 can be formed in the same process as the p type well 50 of the LV-CMOS 4 (see FIG. 10). That is, the HV-DMOS 2 can be easily manufactured by changing the mask layout without increasing the number of processes. Therefore, this method makes it possible to easily manufacture a high voltage DMOS transistor necessary for a panel controller IC, an LCD driver IC, or the like.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 is inverted may be employed. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
In addition, various design changes can be made within the scope of matters described in the claims.

1 Semiconductor device 2 HV-DMOS
3 HV-CMOS
4 LV-CMOS
5 Semiconductor substrate 6 HV-nMOS
7 HV-pMOS
8 LV-nMOS
9 LV-pMOS
DESCRIPTION OF SYMBOLS 10 Element isolation part 11 Deep n type well 12 DMOS-p type body region 13 DMOS-n type drain region 14 Low concentration region 15 High concentration region 16 DMOS-n type source region 17 DMOS channel region 19 DMOS-n type drift region 22 DMOS gate insulating film 23 DMOS gate electrode 26 Deep p-type well 27 HV-n type source region 28 HV-n type drain region 29 HV-n type channel region 34 HV-n type drift region 35 HV-nMOS gate insulating film 36 HV -NMOS gate electrode 38 Deep n-type well 39 HV-p type source region 40 HV-p type drain region 41 HV-p type channel region 46 HV-p type drift region 47 HV-pMOS gate insulating film 48 HV-pMOS gate electrode 50 p-type well 51 LV-n type source region 52 LV-n type drain region 53 LV-n type channel region 54 LV-nMOS gate insulating film 55 LV-nMOS gate electrode 59 n type well 60 LV-p type source region 61 LV-p type drain Region 62 LV-p type channel region 63 LV-pMOS gate insulating film 64 LV-pMOS gate electrode

Claims (10)

A semiconductor device comprising a high breakdown voltage DMOS transistor, a high breakdown voltage CMOS transistor, and a low breakdown voltage CMOS transistor on a common first conductivity type semiconductor substrate,
A high breakdown voltage first conductivity type well and a high breakdown voltage second conductivity type well formed in the region for the high breakdown voltage CMOS transistor of the semiconductor substrate and spaced apart from each other;
Formed in the region for the low breakdown voltage CMOS transistor of the semiconductor substrate, spaced apart from each other, each having a higher impurity concentration than the high breakdown voltage first conductivity type well and the high breakdown voltage second conductivity type well; and A low breakdown voltage first conductivity type well and a low breakdown voltage second conductivity type well formed shallower than the high breakdown voltage first conductivity type well and the high breakdown voltage second conductivity type well;
A DMOS second conductivity type well formed in a region for the high voltage withstand voltage DMOS transistor of the semiconductor substrate and having the same impurity concentration and depth as the high voltage withstand voltage second conductivity type well;
A DMOS first conductivity type body region formed in an inner region of the DMOS second conductivity type well;
A DMOS second conductivity type source region formed in an inner region of the DMOS first conductivity type body region;
A DMOS second conductivity type drain region formed in an inner region of the DMOS second conductivity type well and spaced apart from the DMOS first conductivity type body region;
A DMOS gate electrode formed on the DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well via a DMOS gate insulating film;
The DMOS first conductivity type body region is formed in a low concentration region having the same impurity concentration and the same depth as the high breakdown voltage first conductivity type well and an inner region of the low concentration region, and the low breakdown voltage first conductivity type A semiconductor device having a double well structure including a high concentration region having the same impurity concentration and the same depth as the type well.   2. The semiconductor device according to claim 1, wherein the low concentration region is formed in a polygonal shape having a plurality of rounded corners when the semiconductor substrate is viewed from the front side.   The semiconductor device according to claim 2, wherein the high-concentration region is formed in a polygonal shape having a plurality of rounded corners when the semiconductor substrate is viewed from the surface side. The DMOS channel region is formed across the low concentration region and the high concentration region,
The semiconductor device according to claim 1, wherein the DMOS gate electrode is disposed so as to cross a boundary between the low concentration region and the high concentration region in the DMOS channel region.   5. The low concentration region according to claim 4, wherein a portion where the DMOS channel region is formed is selectively wider than another portion in a plan view of the semiconductor substrate as viewed from the surface side. Semiconductor device.   The semiconductor device according to claim 1, wherein the DMOS second conductivity type drain region is formed with the same impurity concentration and the same depth as the low breakdown voltage second conductivity type well.   The semiconductor device has an STI (Shallow Trench Isolation) structure in which an insulator is embedded in a trench dug down from the surface of the semiconductor substrate, and the high breakdown voltage DMOS transistor, the high breakdown voltage CMOS transistor, and the low breakdown voltage CMOS transistor The semiconductor device as described in any one of Claims 1-6 containing the element isolation | separation part which divides the area | region for each. The low breakdown voltage first conductivity type well and the low breakdown voltage second conductivity type well are each surrounded and partitioned by the element isolation part ,
The size of the low breakdown voltage first conductivity type well surrounded by the element isolation part is 1 μm to 5 μm, and the size of the low breakdown voltage second conductivity type well surrounded by the element isolation part is 1 μm to 10 μm . The semiconductor device according to claim 7. A method of manufacturing a semiconductor device comprising a high breakdown voltage DMOS transistor, a high breakdown voltage CMOS transistor, and a low breakdown voltage CMOS transistor on a common first conductivity type semiconductor substrate,
By selectively introducing a second conductivity type impurity into the region for the high breakdown voltage CMOS transistor and the region for the high breakdown voltage DMOS transistor of the semiconductor substrate, the high breakdown voltage second region is introduced into the region for the high breakdown voltage CMOS transistor. Forming a conductivity type well and simultaneously forming a DMOS second conductivity type well in the region for the high breakdown voltage DMOS transistor;
By selectively introducing an impurity of the first conductivity type into the region for the high breakdown voltage CMOS transistor and the inner region of the DMOS second conductivity type well of the semiconductor substrate, the region for the high breakdown voltage CMOS transistor is increased. Forming a withstand voltage first conductivity type well and simultaneously forming a low concentration region in the DMOS second conductivity type well;
By selectively introducing a first conductivity type impurity into the region for the low breakdown voltage CMOS transistor and the inner region of the low concentration region of the semiconductor substrate, the low breakdown voltage first transistor is introduced into the region for the low breakdown voltage CMOS transistor. A conductive well is formed, and at the same time, a high concentration region having a higher impurity concentration than the low concentration region and shallower than the low concentration region is formed in the low concentration region. Forming a DMOS first conductivity type body region having a double well structure including the low concentration region and the high concentration region in an inner region;
Forming a low breakdown voltage second conductivity type well by selectively introducing a second conductivity type impurity into the low breakdown voltage CMOS transistor region of the semiconductor substrate;
Forming a DMOS second conductivity type drain region by selectively introducing a second conductivity type impurity into an inner region of the DMOS second conductivity type well;
Forming a DMOS second conductivity type source region by selectively introducing a second conductivity type impurity into an inner region of the DMOS first conductivity type body region;
Forming a DMOS gate electrode on the DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well via a DMOS gate insulating film.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the low breakdown voltage second conductivity type well and the step of forming the DMOS second conductivity type drain region are simultaneously performed.

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