JP5973824B2 - Field effect transistor and semiconductor device - Google Patents

Field effect transistor and semiconductor device Download PDF

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JP5973824B2
JP5973824B2 JP2012165105A JP2012165105A JP5973824B2 JP 5973824 B2 JP5973824 B2 JP 5973824B2 JP 2012165105 A JP2012165105 A JP 2012165105A JP 2012165105 A JP2012165105 A JP 2012165105A JP 5973824 B2 JP5973824 B2 JP 5973824B2
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drift region
layer
effect transistor
field effect
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JP2014027062A (en
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松田 順一
順一 松田
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旭化成エレクトロニクス株式会社
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Description

  The present invention relates to a field effect transistor and a semiconductor device, and more particularly to a field effect transistor and a semiconductor device that can reduce on-resistance while maintaining a high drain breakdown voltage.

2. Description of the Related Art Conventionally, LDMOS (Laterally Diffused MOS) transistors having a structure in which an impurity layer in the vicinity of a drain is diffused in a lateral direction are known, and researches are being made to increase the breakdown voltage and lower the on-resistance of LDMOS transistors.
For example, Non-Patent Document 1 discloses a structure in which STI layers are arranged on both sides of a drain extension, and gate fingers are arranged on the STI layer. The drain extension is a drift layer formed from the drain toward the bottom of the gate electrode (that is, the channel). The gate finger is a part of the gate electrode and is an electrode portion extending from the channel toward the drain. According to this structure, a parasitic capacitance is generated between the gate finger and the drain extension obliquely below the gate finger. Since charges are accumulated in the parasitic capacitance, a depletion layer is formed in the drain extension. Thereby, the surface electric field of the drain extension can be relaxed (that is, a reduced surface field: RESURF effect is obtained), and the drain breakdown voltage can be increased.

A. Heringaet al., "Innovative lateral field plates by gate fingers on STI regions in deep submicron CMOS," Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC ’s, pp.271-274, May 18-22, 2008.

Incidentally, in the LDMOS transistor, the drain breakdown voltage and the on-resistance are in a trade-off relationship. That is, when the concentration of the drain extension is increased, the on-resistance of the LDMOS transistor can be reduced, but in this case, the depletion layer is difficult to extend due to the drain extension, so that the drain breakdown voltage is lowered. In the structure disclosed in Non-Patent Document 1, the RESURF effect is surely obtained, but the degree of the effect is not sufficient, and it is difficult to reduce the on-resistance while maintaining a high drain breakdown voltage.
SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and an object thereof is to provide a field effect transistor and a semiconductor device that can reduce on-resistance while maintaining a high drain breakdown voltage.

(Claim equivalent)
In order to solve the above problems, a field effect transistor according to one embodiment of the present invention is a field effect transistor formed over a semiconductor substrate, the region serving as a channel and the drain of the first conductivity type in the semiconductor substrate. A drift region of a first conductivity type disposed between, a field oxide film disposed on the drift region, a first electrode portion disposed on the field oxide film, and the semiconductor substrate A second conductivity type first impurity diffusion layer disposed below the drift region, wherein the drift region has a first conductivity type impurity concentration higher than that of the first drift region and the first drift region. And a second drift region exposed from under the field oxide film, and at least a part of the first impurity diffusion layer is a front side when viewed from the stacking direction of the field effect transistor. Through the first drift region and wherein the overlapping with the second drift region.

In the field effect transistor, the first impurity diffusion layer may be located directly below the second drift region via the first drift region.
The field effect transistor may further include a second impurity diffusion layer of a second conductivity type disposed under the drift region of the semiconductor substrate, and the second impurity diffusion layer includes the first impurity. The impurity concentration of the second conductivity type is lower than that of the diffusion layer, and the impurity concentration may be located directly below the field oxide film via the first drift region.

The field effect transistor may further include an insulating film disposed on the semiconductor substrate and covering the first electrode portion, and a second electrode portion disposed on the insulating film, wherein the second electrode At least a part of the portion may overlap the second drift region with the insulating film interposed therebetween.
In the above-described field effect transistor, the second electrode portion may be located immediately above the second drift region with the insulating film interposed therebetween.
In the field effect transistor, the first electrode portion may be disposed on the field oxide film on both sides of the second drift region.

  A field effect transistor according to another aspect of the present invention is a MOS transistor formed on a semiconductor substrate, and is a first transistor disposed between a region serving as a channel of the semiconductor substrate and a drain of a first conductivity type. A drift region of one conductivity type; a field oxide film disposed on the drift region; a first electrode portion disposed on the field oxide film; and the first electrode portion disposed on the semiconductor substrate. An insulating film for covering, and a second electrode portion disposed on the insulating film, wherein the drift region has a first drift region and an impurity concentration of the first conductivity type higher than that of the first drift region, And a second drift region exposed from under the field oxide film, and when viewed from the stacking direction of the field effect transistor, at least a part of the second electrode portion is interposed through the insulating film. And wherein the overlapping with the second drift region.

In the above-described field effect transistor, the second electrode portion may be located immediately above the second drift region with the insulating film interposed therebetween.
A semiconductor device according to still another aspect of the present invention includes any one of the above-described field effect transistors.

  According to one embodiment of the present invention, in a field-effect transistor in an off state, the drift region can be efficiently depleted, and a reverse bias is applied between the source and the drain while the source and the semiconductor substrate are connected. In addition, it becomes easy to completely deplete the drift region when the reverse bias is small. For this reason, the surface electric field of the drift region can be sufficiently relaxed (that is, the RESURF effect can be sufficiently obtained). Further, since the RESURF effect can be sufficiently obtained, the impurity concentration in the vicinity of the surface of the drift region can be increased like the second drift region. As a result, the on-resistance can be reduced while maintaining a high drain breakdown voltage.

1 is a cross-sectional view showing a configuration example of an LDMOS transistor 100 according to a first embodiment. FIG. 2 is a plan view showing a configuration example of an LDMOS transistor 100. Sectional drawing which shows the manufacturing method of the LDMOS transistor 100 in order of a process. Sectional drawing which shows the manufacturing method of the LDMOS transistor 100 in order of a process. The figure which shows the improvement of the trade-off characteristic of drain breakdown voltage and on-resistance. Sectional drawing which shows the structural example of the LDMOS transistor 200 which concerns on 2nd Embodiment. FIG. 2 is a plan view showing a configuration example of an LDMOS transistor 200. Sectional drawing which shows the manufacturing method of the LDMOS transistor 200 in order of a process. Sectional drawing which shows the structural example of the LDMOS transistor 300 which concerns on 3rd Embodiment. FIG. 3 is a plan view showing a configuration example of an LDMOS transistor 300. Sectional drawing which shows the manufacturing method of the LDMOS transistor 300 in order of a process.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
<First Embodiment>
(Construction)
FIG. 1 is a sectional view showing a configuration example of an LDMOS transistor 100 according to the first embodiment of the present invention. FIG. 2 is a plan view showing a configuration example of the LDMOS transistor 100. FIG. 1 is a cross-sectional view taken along line Y1-Y′1 in FIG.

  As shown in FIGS. 1 and 2, the LDMOS transistor 100 is an N-channel transistor formed on, for example, a P-type silicon substrate 1 (P-sub), and a gate insulating film (on the silicon substrate 1). The gate electrode 10 formed through the gate electrode 10, the N-type source 20 and drain 30 formed on the silicon substrate 1 below both sides of the gate electrode 10, and a region (as a channel) of the silicon substrate 1 ( Hereinafter, an N type drift region 50 disposed between the channel region 40 and the drain 30 and a field oxide film 60 disposed on the drift region 50 are provided.

  The N-type drift region 50 is an N-type impurity diffusion layer having one end connected to the drain 30 and the other end connected to the channel region 40 in the channel length direction (that is, the X-axis direction). The drift region 50 includes an N-drift layer (hereinafter referred to as an N-layer) 51 containing N-type impurities and a first drain extension (hereinafter referred to as an N layer) containing N-type impurities at a higher concentration than the N-layer 51. 52 and a second drain extension (hereinafter referred to as an N + layer) 53 containing an N-type impurity at a higher concentration than the N layer 52.

  As shown in FIG. 1, N layer 52 is interposed between N − layer 51 and field oxide film 60. The N + layer 53 is disposed on the N layer 52 and is exposed from under the field oxide film 60, and the N layer 52 is interposed between the N + layer 53 and the second P-type buried layer 80. As shown in FIG. 2, the N layer 52 is also interposed between the N + layer 53 and the channel region 40. That is, one end of the N + layer 53 is connected to the N layer 52 in the channel length direction. Further, the other end of the N + layer 53 is connected to the drain 30 in the channel length direction. The field oxide film 60 is, for example, a LOCOS (Local Oxidation of Silicon) film.

  The gate electrode 10 has a plurality of field plate electrodes 10 a extending from the drain side end toward the drain 30. Each of the plurality of field plate electrodes 10 a is arranged on field oxide film 60 on N layer 52. The gate electrode 10 and the field plate electrode 10a are formed by patterning a conductive film and are electrically connected to each other. The conductive film forming the gate electrode 10 and the field plate electrode 10a is, for example, a polysilicon film containing N-type impurities or P-type impurities.

  The LDMOS transistor 100 includes a first P-type buried layer (first PBL; hereinafter referred to as P layer) 70 disposed under the drift region 50, and a second P-type impurity that is higher in concentration than the P layer 70. P-type buried layer (second PBL; hereinafter referred to as P + layer) 80. P + layer 80 is located immediately below (ie, directly below) N + layer 53, and P layer 70 is located directly below field oxide film 60.

  As shown in FIG. 2, the N-type source 20 and the drain 30 are composed of an N ++ layer containing N-type impurities at a higher concentration than the N + layer 53. A high-concentration P-type impurity diffusion layer (P ++ layer) 35 that is electrically connected to the silicon substrate 1 is disposed inside the source 20. A contact hole 37 on the source 20 is also disposed on the P ++ layer 35. Thus, the silicon substrate 1 and the source 20 can maintain the same potential via a conductive film (not shown) that fills the contact hole 37. A contact hole 47 is disposed on the drain 30.

(Production method)
3 and 4 are cross-sectional views showing the method of manufacturing the LDMOS transistor 100 in the order of steps. As shown in FIG. 3A, first, a P-type silicon substrate 1 is prepared. Next, for example, a resist pattern 91 is formed on the silicon substrate 1, and N-type impurities such as phosphorus or arsenic are ion-implanted into the silicon substrate 1 using the resist pattern 91 as a mask to form an N-layer 51. To do.

  Subsequently, for example, a P-type impurity such as boron is ion-implanted into the silicon substrate 1 using the resist pattern 91 as a mask to form a P layer 70 as shown in FIG. Then, for example, using the resist pattern 91 as a mask, N-type impurities such as phosphorus or arsenic are ion-implanted into the silicon substrate 1 to form the N layer 52. After forming the N layer 52, the resist pattern 91 is removed. Then, the silicon substrate 1 is subjected to heat treatment to activate the N− layer 51, the P layer 70, and the N layer 52, respectively.

  In the first embodiment of the present invention and the second and third embodiments (hereinafter, each embodiment) described later, the order of forming the N-layer 51, the P layer 70, and the N layer 52 is limited to the above. Each layer may be formed in any order. In each embodiment of the present invention, the resist pattern for forming the N-layer 51, the P layer 70, and the N layer 52 may be the same pattern as described above, or may be separate patterns. Good. For example, a first resist pattern for forming the N− layer 51, a second resist pattern for forming the P layer 70, a third resist pattern for forming the N layer 52, and so on. Correspondingly, a resist pattern may be formed.

Next, as shown in FIG. 3C, a field oxide film 60 is locally formed on the silicon substrate 1. A method of forming the field oxide film 60 is, for example, a LOCOS method. In each embodiment of the present invention, the method for forming the field oxide film 60 is not limited to the LOCOS method. The formation method of the field oxide film 60 may be, for example, an STI (Shallow Trench Isolation) method in which a trench is formed in the silicon substrate 1 and an insulating film or the like is embedded.
Next, a gate insulating film (not shown) is formed on the surface of the region of the silicon substrate 1 where the field oxide film 60 is not formed (that is, the active region). Then, for example, a polysilicon film is deposited on the gate insulating film and patterned. Thereby, as shown in FIG. 4A, the gate electrode 10 (including the field plate electrode 10a) is formed.

  Next, as shown in FIG. 4B, on the silicon substrate 1 on which the gate electrode 10 is formed, for example, the drift region and the gate electrode 10 are opened and the other regions are covered. A resist pattern 92 having a shape is formed. Next, N-type impurities such as phosphorus or arsenic are ion-implanted into the silicon substrate 1 using the resist pattern 92 as a mask. As a result, an N + layer 53 is formed on the N layer 52. An N-type impurity is also introduced into the gate electrode 10. After the N + layer 53 is formed, the resist pattern 92 is removed.

  Next, as shown in FIG. 4C, on the silicon substrate 1 on which the N + layer 53 is formed, for example, a resist pattern 93 having a shape that opens above the N + layer 53 and covers other regions is formed. To do. Next, P-type impurities such as boron are ion-implanted into the silicon substrate 1 using the resist pattern 93 as a mask. Thereby, a P + layer 80 (see FIG. 1) is formed. After forming the P + layer 80, the resist pattern 93 is removed.

  Thereafter, on the silicon substrate 1 on which the N + layer 53 and the P + layer 80 are formed, for example, a resist pattern (not shown) having a shape covering the drift region and covering the other region is formed. Next, using this resist pattern as a mask, an N-type impurity such as phosphorus or arsenic is ion-implanted into the silicon substrate 1 to form an N-type source 20 and drain 30. After the N-type source 20 and drain 30 are formed, the resist pattern is removed. Through the above steps, the N-channel type LDMOS transistor 100 shown in FIGS. 1 and 2 is completed.

  In the first embodiment, the silicon substrate 1 corresponds to the “semiconductor substrate” of the present invention, and the field plate electrode 10a corresponds to the “first electrode portion” of the present invention. The second PBL (P + layer) 80 corresponds to the “first impurity diffusion layer” of the present invention, and the first PBL (P layer) 70 corresponds to the “second impurity diffusion layer” of the present invention. Further, the N− layer 51 and the N layer 52 correspond to the “first drift region” of the present invention, and the N layer 53 corresponds to the “second drift region” of the present invention. The LDMOS transistor 100 corresponds to the “field effect transistor” of the present invention. Further, the N type corresponds to the “first conductivity type” of the present invention, and the P type corresponds to the “second conductivity type” of the present invention.

(Effect of 1st Embodiment)
The first embodiment of the present invention has the following effects.
(1) A parasitic capacitance is generated between the field plate electrode 10 a disposed on the field oxide film 60 and the N + layer 53 disposed on the silicon substrate 1. Charges are accumulated in the parasitic capacitance, and a depletion layer is formed near the surface of the N + layer 53 on the field plate electrode 10a side. Therefore, when the LDMOS transistor 100 is turned off, the N + layer 53 can be depleted from obliquely above.

(2) The field plate electrodes 10a are arranged not only on one side of the N + layer 53 but also on both sides in plan view. For this reason, depletion layers are formed in the vicinity of the surfaces on both sides of the N + layer 53, respectively. Thereby, when the LDMOS transistor 100 is turned off, the N + layer 53 can be depleted from the left and right diagonally upper sides.
(3) A P + layer 80 is arranged directly under the N + layer 53, and a depletion layer is formed by a PN junction between the N + layer 53, the N layer 52, the N− layer 51, and the P + layer 80. . Thereby, when the LDMOS transistor 100 is turned off, the N + layer 53, the N layer 52, and the N− layer 51 can be depleted from the lower P + layer 80 side.

(4) A P layer 70 is disposed directly under the field oxide film 60, and a depletion layer is formed between the N layer 52 and the N− layer 51 and the P layer 70 by a PN junction. Thus, when the LDMOS transistor 100 is turned off, the N layer 52 and the N− layer 51 can be depleted from the lower N− layer 51 side.
(5) Due to the effects (1) to (4), in the LDMOS transistor 100 in the off state, the drift region 50 can be depleted from three directions, diagonally upward and downward on the left and right. This facilitates complete depletion of the drift region 50 when a reverse bias is applied between the source 20 and the drain 30 in a state where the source 20 and the semiconductor substrate 1 are connected. Therefore, the surface electric field of the drift region 50 can be sufficiently relaxed (that is, the RESURF effect can be sufficiently obtained).

(6) Since the RESURF effect can be sufficiently obtained, the N-type impurity concentration in the vicinity of the surface of the drift region 50 located immediately above (that is, directly above) the p + layer 80 as in the N + layer 53 can be increased. it can. As a result, the on-resistance can be reduced while maintaining the drain breakdown voltage of the LDMOS transistor 100 high. For example, as shown by the arrows in FIG. 5, the trade-off characteristics between the drain breakdown voltage and the on-resistance can be improved.

  In FIG. 5, BVdss on the horizontal axis is the state where the semiconductor substrate 1, the gate electrode 10 and the source 20 are electrically connected (that is, in the off state), and a reverse bias is applied to the drain 30. This is a voltage value when current starts to flow from the drain 30 to the source 20 and the semiconductor substrate 1 due to avalanche breakdown. Ron · sq on the vertical axis is a resistance value between the source 20 and the drain 30 when the LDMOS transistor 100 is on, and is a value indicating the resistance value per unit area of the element.

(Modification)
(1) In the first embodiment described above, regarding the positional relationship between the N + layer 53 and the P + layer 80, the P + layer 80 is located immediately below the N + layer 53 (via the N− layer 51 and the N layer 52). Explained the case. However, in the first embodiment, the positional relationship between the N + layer 53 and the P + layer 80 is not limited to this, and the P + layer 80 may be arranged at a position slightly shifted from directly below the N + layer 53. If at least a part of the P + layer 80 is disposed at a position overlapping the N + layer 53 (via the N− layer 51 and the N layer 52) when viewed from the stacking direction of the LDMOS transistor 100, when the LDMOS transistor 100 is turned off, The N + layer 53 can be depleted from the lower P + layer 80 side.

(2) In the first embodiment, the LDMOS transistor 100 and other elements (hereinafter referred to as pMOS transistors) may be mixedly mounted on the same silicon substrate 1 to constitute a semiconductor device. Even in such a case, the same effects as those of the first embodiment can be obtained.
(3) Further, in the first embodiment, the LDMOS transistor 100 is an N-channel type, but the LDMOS transistor 100 may be a P-channel type. That is, in the first embodiment, the N type may be replaced with the P type, and the P type may be replaced with the N type. Even in such a case, in the P-channel type LDMOS transistor 100, the trade-off characteristics between the drain breakdown voltage and the on-resistance can be improved.

Second Embodiment
In the first embodiment, the case where the P + layer 80 is disposed directly below the N + layer 53 in order to enhance the RESURF effect has been described. However, in the embodiment of the present invention, the RESURF effect may be enhanced by disposing the gate electrode 10 not directly under the N + layer 53 but directly above the N + layer 53. In the second embodiment, such an aspect will be described.

(Construction)
FIG. 6 is a cross-sectional view showing a configuration example of the LDMOS transistor 200 according to the second embodiment of the present invention. FIG. 7 is a plan view showing a configuration example of the LDMOS transistor 200. FIG. 6 is a cross-sectional view of FIG. 7 cut along line Y6-Y′6. In FIG. 7, the interlayer insulating film 110 is not shown in order to avoid complication of the drawing.

  As shown in FIGS. 6 and 7, the LDMOS transistor 200 is different in structure from the LDMOS transistor 100 described in the first embodiment in that the second gate electrode 10 is provided instead of the P + layer 80. is there. That is, the LDMOS transistor 200 includes an interlayer insulating film 110 formed on the silicon substrate 1 and covering a gate electrode (hereinafter referred to as a first gate electrode) 10, a second gate electrode 120 formed on the interlayer insulating film 110, Is provided.

  The interlayer insulating film 110 is, for example, a silicon oxide film or a silicon nitride film, or a film in which these are stacked. The second gate electrode 120 is located immediately above the N + layer 53 with the interlayer insulating film 110 interposed therebetween. The second gate electrode 120 is electrically connected to the first gate electrode 10 through the contact hole 117. The second gate electrode 120 is made of polysilicon containing N-type or P-type impurities, for example.

(Production method)
FIG. 8 is a cross-sectional view showing a method of manufacturing the LDMOS transistor 200 in the order of steps. As shown in FIG. 8A, in the manufacturing method of the LDMOS transistor 200, the process up to the step of forming the N + layer 53 is the same as that of the first embodiment. In the second embodiment, after forming the N + layer 53, the step of forming the P + layer 80 is skipped, and the N-type source 20 and drain 30 are formed in the same manner as in the first embodiment. Thereafter, as shown in FIG. 8B, an interlayer insulating film 110 is deposited on the silicon substrate 1 by, eg, CVD. Next, the interlayer insulating film 110 is patterned to form a contact hole 117 having the first gate electrode 10 as a bottom surface. Then, for example, a polysilicon film is deposited on the interlayer insulating film 110 so as to fill the contact hole 117. Further, the deposited polysilicon film is patterned to form the second gate electrode 120. Through the above steps, the N-channel LDMOS transistor 200 shown in FIGS. 6 and 7 is completed.

  In the second embodiment, the interlayer insulating film 110 corresponds to the “insulating film” of the present invention, and the second gate electrode 120 corresponds to the “second electrode portion” of the present invention. The LDMOS transistor 200 corresponds to the “field effect transistor” of the present invention. Other correspondences are the same as in the first embodiment.

(Effect of 2nd Embodiment)
The second embodiment of the present invention has the following effects in addition to the effects (1), (2), and (4) of the first embodiment.
(1) The second gate electrode 120 is disposed immediately above the N + layer 53 with the interlayer insulating film 110 interposed therebetween. For this reason, a parasitic capacitance is generated between the second gate electrode 120 and the N + layer 53. Charges are also accumulated in this parasitic capacitance, and a depletion layer is further formed near the surface of the N + layer 53. Thereby, when the field effect transistor is turned off, the drift region 50 can be further depleted from the upper side, and the RESURF effect can be sufficiently obtained.

(2) In addition to the effects (1), (2), and (4) of the first embodiment, the drift region 50 is tilted left and right in the LDMOS transistor 200 in the off state by exhibiting the effect (1) of the second embodiment. It can be depleted from above and directly above (ie, the entire top). This facilitates complete depletion of the drift region 50 when a reverse bias is applied between the source 20 and the drain 30 in a state where the source 20 and the semiconductor substrate 1 are connected. Therefore, the surface electric field of the drift region 50 can be sufficiently relaxed (that is, the RESURF effect can be sufficiently obtained).
(3) Since the RESURF effect can be sufficiently obtained, the same effect as the effect (6) of the first embodiment is achieved.

(Modification)
(1) In the second embodiment, the positional relationship between the N + layer 53 and the second gate electrode 120 is such that the second gate electrode 120 is located directly above the N + layer 53 with the interlayer insulating film 110 interposed therebetween. Explained. However, in the second embodiment, the positional relationship between the N + layer 53 and the second gate electrode 120 is not limited to this, and the second gate electrode 120 is disposed at a position slightly shifted from directly above the N + layer 53. It may be. As long as at least a part of the second gate electrode 120 is disposed at a position overlapping the N + layer 53 (via the interlayer insulating film 110) when viewed from the stacking direction of the LDMOS transistor 100, the N + layer is turned off when the LDMOS transistor 100 is turned off. 53 can be depleted from the upper side of the second gate electrode 120.
(2) The modifications (2) and (3) described in the first embodiment may be applied to the second embodiment.

<Third Embodiment>
In the embodiment of the present invention, the first embodiment and the second embodiment may be combined. In the third embodiment, such an aspect will be described.
(Construction)
FIG. 9 is a cross-sectional view showing a configuration example of an LDMOS transistor 300 according to the third embodiment of the present invention. FIG. 10 is a plan view showing a configuration example of the LDMOS transistor 300. Note that a cross section taken along line Y9-Y'9 in FIG. 10 corresponds to FIG. Further, in FIG. 10, the illustration of the interlayer insulating film 110 is omitted in order to avoid complication of the drawing.

  As shown in FIGS. 9 and 10, the LDMOS transistor 300 includes a P + layer 80 disposed under the N + layer 53 of the silicon substrate 1 and a first gate electrode 10 (field plate electrode) disposed on the silicon substrate 1. And the second gate electrode 120 disposed on the interlayer insulating film 110.

(Production method)
FIG. 11 is a cross-sectional view showing a method of manufacturing the LDMOS transistor 300 in the order of steps. As shown in FIG. 11A, the process from the formation of the P + layer 80 to the step of forming the N-type source 20 and drain 30 is the same as in the first embodiment. After removing the resist pattern after the N-type source 20 and drain 30 are formed, an interlayer insulating film 110 is deposited on the silicon substrate 1 as shown in FIG. The subsequent steps are the same as in the second embodiment. Through the above steps, the N-channel LDMOS transistor 300 shown in FIGS. 9 and 10 is completed.
In the third embodiment, the LDMOS transistor 300 corresponds to the “field effect transistor” of the present invention. Other correspondences are the same as those in the first and second embodiments.

(Effect of the third embodiment)
(1) The third embodiment of the present invention has the effects (1) to (4) of the first embodiment and the effect (1) of the second embodiment. As a result, in the LDMOS transistor 300 in the off state, the drift region 50 can be depleted from four directions, diagonally upward, right above, and below. For this reason, when a reverse bias is applied between the source 20 and the drain 30 in a state where the source 20 and the semiconductor substrate 1 are connected, it is further easy to completely deplete the drift region 50. Therefore, the surface electric field of the drift region 50 can be more sufficiently relaxed (that is, the RESURF effect can be more sufficiently obtained).
(2) Since the RESURF effect can be obtained more sufficiently, the N-type impurity concentration in the N + layer 53 can be further increased. As a result, the on-resistance can be further reduced while maintaining the drain breakdown voltage of the LDMOS transistor 300 high.

(Modification)
Modifications (1) to (3) described in the first embodiment and modification (1) described in the second embodiment may be applied to the third embodiment.
<Others>
The present invention is not limited to the embodiments described above. A design change or the like may be added to each embodiment based on the knowledge of a person skilled in the art, and an aspect in which such a change is added is also included in the scope of the present invention.

1 silicon substrate 10 (first) gate electrode 10a field plate electrode 20 source 30 drain 35 P ++ layer 37, 47 contact hole 40 channel region 50 drift region 51 N− layer (N− drift layer)
52 N layer (first drain extension)
53 N + layer (second drain extension)
60 Field oxide film 70 P layer (first PBL)
80 P + layer (2nd PBL)
91, 92, 93 Resist pattern 100, 200, 300 LDMOS transistor 110 Interlayer insulating film 117 Contact hole 120 Second gate electrode

Claims (9)

  1. A field effect transistor formed on a semiconductor substrate,
    A drift region of a first conductivity type disposed between a region of a channel of the semiconductor substrate and a drain of a first conductivity type;
    A field oxide film disposed on the drift region;
    A first electrode portion disposed on the field oxide film;
    A first impurity diffusion layer of a second conductivity type disposed under the drift region of the semiconductor substrate,
    The drift region has a first drift region, said first high impurity concentration of the first conductivity type than the drift region, and a second drift region exposed the field oxide film or al, a field oxide film Are disposed on both sides in the channel width direction of the second drift region, as viewed from the stacking direction of the field effect transistor,
    A field effect transistor, wherein at least a part of the first impurity diffusion layer overlaps with the second drift region through the first drift region when viewed from the stacking direction of the field effect transistor.
  2.   2. The field effect transistor according to claim 1, wherein the first impurity diffusion layer is located directly below the second drift region via the first drift region.
  3. A second impurity diffusion layer of a second conductivity type disposed under the drift region of the semiconductor substrate;
    The second impurity diffusion layer has an impurity concentration of a second conductivity type lower than that of the first impurity diffusion layer, and is located immediately below the field oxide film through the first drift region. Item 3. The field effect transistor according to item 1 or 2.
  4. An insulating film disposed on the semiconductor substrate and covering the first electrode portion;
    A second electrode portion disposed on the insulating film,
    4. The field effect transistor according to claim 1, wherein at least part of the second electrode portion overlaps the second drift region with the insulating film interposed therebetween. 5.
  5.   5. The field effect transistor according to claim 4, wherein the second electrode portion is positioned immediately above the second drift region with the insulating film interposed therebetween.
  6.   6. The field effect transistor according to claim 1, wherein the first electrode portion is disposed on the field oxide film on both sides of the second drift region. 7.
  7. A field effect transistor formed on a semiconductor substrate,
    A drift region of a first conductivity type disposed between a region of a channel of the semiconductor substrate and a drain of a first conductivity type;
    A field oxide film disposed on the drift region;
    A first electrode portion disposed on the field oxide film;
    An insulating film disposed on the semiconductor substrate and covering the first electrode portion;
    A second electrode portion disposed on the insulating film,
    The drift region has a first drift region, said first high impurity concentration of the first conductivity type than the drift region, and a second drift region exposed the field oxide film or al, a field oxide film Are disposed on both sides in the channel width direction of the second drift region, as viewed from the stacking direction of the field effect transistor,
    A field effect transistor, wherein at least a part of the second electrode portion overlaps the second drift region through the insulating film when viewed from the stacking direction of the field effect transistor.
  8.   The field effect transistor according to claim 7, wherein the second electrode portion is located immediately above the second drift region with the insulating film interposed therebetween.
  9.   A semiconductor device comprising the field effect transistor according to claim 1.
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