JP2014212203A - Semiconductor device - Google Patents
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- JP2014212203A JP2014212203A JP2013087558A JP2013087558A JP2014212203A JP 2014212203 A JP2014212203 A JP 2014212203A JP 2013087558 A JP2013087558 A JP 2013087558A JP 2013087558 A JP2013087558 A JP 2013087558A JP 2014212203 A JP2014212203 A JP 2014212203A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 239000010410 layer Substances 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 230000015556 catabolic process Effects 0.000 description 14
- 239000012535 impurity Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 14
- 239000002344 surface layer Substances 0.000 description 8
- 239000000969 carrier Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Abstract
Description
本発明は、半導体装置に関し、例えばトランジスタのドレイン領域とゲート電極の間に分離絶縁膜を有する半導体装置に適用可能な技術である。 The present invention relates to a semiconductor device, for example, a technique applicable to a semiconductor device having an isolation insulating film between a drain region and a gate electrode of a transistor.
電力を制御するトランジスタのドレイン領域には、高い電圧が印加される。このため、ドレイン領域とゲート電極の間の耐圧を高める必要がある。この耐圧を高めるための技術の一つに、ドレイン領域をゲート電極から離し、これらの間に分離絶縁膜を配置したトランジスタがある。このようなトランジスタに関する技術としては、例えば特許文献１に記載の構造がある。
A high voltage is applied to the drain region of the transistor that controls power. For this reason, it is necessary to increase the breakdown voltage between the drain region and the gate electrode. One technique for increasing the breakdown voltage is a transistor in which a drain region is separated from a gate electrode and an isolation insulating film is disposed between them. As a technique related to such a transistor, for example, there is a structure described in
特許文献１に記載の構造では、さらに、分離絶縁膜にフローティング状態の電極（フローティングプレート）を埋め込んでいる。この技術によれば、フローティングプレートはドレイン領域と容量カップリングし、さらにゲート電極とも容量カップリングする。このため、基板のうちドレイン領域とゲート電極の間に位置する領域において、電界の分布に偏りが生じることを抑制できる。
In the structure described in
本発明者は、ドレイン領域とゲート電極の間の耐圧をさらに高めることを検討した。その他の課題と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。 The inventor has studied to further increase the breakdown voltage between the drain region and the gate electrode. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.
一実施の形態によれば、ドレイン領域はゲート電極から離れている。そして、半導体基板のうちドレイン領域とゲート電極の間に位置する部分には、分離絶縁膜が設けられている。分離絶縁膜には、埋込導電層が設けられている。この埋込導電層は、第１コンタクトに接続している。 According to one embodiment, the drain region is remote from the gate electrode. An isolation insulating film is provided in a portion of the semiconductor substrate located between the drain region and the gate electrode. A buried conductive layer is provided in the isolation insulating film. The buried conductive layer is connected to the first contact.
前記一実施の形態によれば、ドレイン領域とゲート電極の間の耐圧を高めることができる。 According to the embodiment, the breakdown voltage between the drain region and the gate electrode can be increased.
以下、実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。 Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
（第１の実施形態）
図１は、第１の実施形態に係る半導体装置ＳＤの構造を示す断面図である。図２は、半導体装置ＳＤの平面図である。図１は、図２のＡ−Ａ´断面に対応している。ただし図２において、説明のため、ゲート電極ＧＥは点線で示しており、かつ、層間絶縁膜ＩＮＳＬを省略している。
(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device SD according to the first embodiment. FIG. 2 is a plan view of the semiconductor device SD. FIG. 1 corresponds to the AA ′ cross section of FIG. However, in FIG. 2, for the sake of explanation, the gate electrode GE is indicated by a dotted line, and the interlayer insulating film INSL is omitted.
本実施形態に係る半導体装置ＳＤは、半導体基板ＳＵＢ、ゲート絶縁膜ＧＩＮＳ、ゲート電極ＧＥ、ソース領域ＳＯＵ、ドレイン領域ＤＲＮ、分離絶縁膜ＳＩＮＳ１、埋込導電層ＣＮＬ、層間絶縁膜ＩＮＳＬ、及び第１コンタクトＣＯＮ１を備えている。ゲート絶縁膜ＧＩＮＳは半導体基板ＳＵＢ上に形成されており、ゲート電極ＧＥはゲート絶縁膜ＧＩＮＳ上に形成されている。ドレイン領域ＤＲＮ及びソース領域ＳＯＵは半導体基板ＳＵＢに形成されており、平面視でゲート電極ＧＥを挟んでいる。ゲート電極ＧＥとドレイン領域ＤＲＮの間隔は、ゲート電極ＧＥとソース領域ＳＯＵの間隔よりも広い。分離絶縁膜ＳＩＮＳ１は半導体基板ＳＵＢに設けられており、ゲート電極ＧＥとドレイン領域ＤＲＮの間に位置している。埋込導電層ＣＮＬは、分離絶縁膜ＳＩＮＳ１に埋め込まれている。埋込導電層ＣＮＬの底部は分離絶縁膜ＳＩＮＳ１の底部よりも上側に位置している。層間絶縁膜ＩＮＳＬは半導体基板ＳＵＢ上に形成されている。そして第１コンタクトＣＯＮ１は層間絶縁膜ＩＮＳＬに埋め込まれており、埋込導電層ＣＮＬに接続している。 The semiconductor device SD according to this embodiment includes a semiconductor substrate SUB, a gate insulating film GINS, a gate electrode GE, a source region SOU, a drain region DRN, an isolation insulating film SINS1, a buried conductive layer CNL, an interlayer insulating film INSL, and a first A contact CON1 is provided. The gate insulating film GINS is formed on the semiconductor substrate SUB, and the gate electrode GE is formed on the gate insulating film GINS. The drain region DRN and the source region SOU are formed in the semiconductor substrate SUB and sandwich the gate electrode GE in plan view. The distance between the gate electrode GE and the drain region DRN is wider than the distance between the gate electrode GE and the source region SOU. The isolation insulating film SINS1 is provided on the semiconductor substrate SUB and is located between the gate electrode GE and the drain region DRN. The buried conductive layer CNL is buried in the isolation insulating film SINS1. The bottom of the buried conductive layer CNL is located above the bottom of the isolation insulating film SINS1. The interlayer insulating film INSL is formed on the semiconductor substrate SUB. The first contact CON1 is buried in the interlayer insulating film INSL and is connected to the buried conductive layer CNL.
本実施形態によれば、埋込導電層ＣＮＬには第１コンタクトＣＯＮ１が接続しているため、埋込導電層ＣＮＬに固定電位を印加することができる。これにより、半導体基板ＳＵＢの表層のうち平面視で埋込導電層ＣＮＬと重なる部分には、空乏層が形成される。そしてこの空乏層が形成されることによって、ドレイン領域ＤＲＮとゲート電極ＧＥの間の耐圧を高くすることができる。以下、詳細に説明する。 According to this embodiment, since the first contact CON1 is connected to the buried conductive layer CNL, a fixed potential can be applied to the buried conductive layer CNL. Thereby, a depletion layer is formed in a portion of the surface layer of the semiconductor substrate SUB that overlaps the buried conductive layer CNL in plan view. By forming this depletion layer, the breakdown voltage between the drain region DRN and the gate electrode GE can be increased. Details will be described below.
半導体基板ＳＵＢは、例えば第１導電型のシリコン基板である。ただし半導体基板ＳＵＢは、他の半導体基板である。なお、以下の説明において、第１導電型をｐ型として、第２導電型をｎ型とする。ただし第１導電型はｎ型であり、第２導電型はｐ型であってもよい。 The semiconductor substrate SUB is, for example, a first conductivity type silicon substrate. However, the semiconductor substrate SUB is another semiconductor substrate. In the following description, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type may be n-type, and the second conductivity type may be p-type.
半導体基板ＳＵＢの表層には、素子分離膜ＳＩＮＳが形成されている。本図に示す例において、素子分離膜ＳＩＮＳはＳＴＩ（Shallow Trench Isolation）構造を有している。素子分離膜ＳＩＮＳは、図２に示すように、トランジスタのソース領域ＳＯＵ及びチャネルが形成されるべき領域（チャネル領域）を他の領域から分離するとともに、トランジスタのドレイン領域ＤＲＮが形成されるべき領域を他の領域から分離している。言い換えると、ドレイン領域ＤＲＮは、ソース領域ＳＯＵ及びチャネル領域と、素子分離膜ＳＩＮＳの一部（分離絶縁膜ＳＩＮＳ１）によって分離されている。 An element isolation film SINS is formed on the surface layer of the semiconductor substrate SUB. In the example shown in this drawing, the element isolation film SINS has an STI (Shallow Trench Isolation) structure. As shown in FIG. 2, the element isolation film SINS separates the source region SOU of the transistor and the region where the channel is to be formed (channel region) from other regions, and the region where the drain region DRN of the transistor is to be formed Is separated from other areas. In other words, the drain region DRN is separated from the source region SOU and the channel region by a part of the element isolation film SINS (isolation insulating film SINS1).
分離絶縁膜ＳＩＮＳ１には凹部ＤＥＰが形成されている。凹部ＤＥＰには、埋込導電層ＣＮＬが埋め込まれている。本図に示す例において埋込導電層ＣＮＬは、ｐ型の半導体層（例えばポリシリコン層）である。埋込導電層ＣＮＬの不純物濃度は、後述する高濃度領域ＤＩＦの不純物濃度よりも低い。また本図に示す例において、平面視において凹部ＤＥＰはドレイン領域ＤＲＮに繋がっている。このため、埋込導電層ＣＮＬのうちドレイン領域ＤＲＮ側の側面は、ドレイン領域ＤＲＮに接しており、ドレイン領域ＤＲＮとの間でＰＮ接合を形成している。 A recess DEP is formed in the isolation insulating film SINS1. A buried conductive layer CNL is buried in the recess DEP. In the example shown in this figure, the buried conductive layer CNL is a p-type semiconductor layer (for example, a polysilicon layer). The impurity concentration of the buried conductive layer CNL is lower than the impurity concentration of a high concentration region DIF described later. In the example shown in this figure, the recess DEP is connected to the drain region DRN in plan view. Therefore, the side surface of the buried conductive layer CNL on the drain region DRN side is in contact with the drain region DRN and forms a PN junction with the drain region DRN.
半導体基板ＳＵＢには、ｐ型のウェルＷＬが形成されている。ウェルＷＬの不純物濃度は、半導体基板ＳＵＢの不純物濃度よりも高い。ウェルＷＬは、深さ方向及び平面視の双方において、ソース領域ＳＯＵ及びチャネル領域が形成されるべき領域及びその周囲に設けられている。そしてウェルＷＬの表層の一部には、ｎ型のソース領域ＳＯＵ及びｐ型の高濃度領域ＤＩＦが設けられている。高濃度領域ＤＩＦの不純物濃度はウェルＷＬの不純物濃度よりも高い。本図に示す例において、ソース領域ＳＯＵ及び高濃度領域ＤＩＦは互いに隣り合っている。 A p-type well WL is formed in the semiconductor substrate SUB. The impurity concentration of the well WL is higher than the impurity concentration of the semiconductor substrate SUB. The well WL is provided in and around the region where the source region SOU and the channel region are to be formed both in the depth direction and in plan view. An n-type source region SOU and a p-type high concentration region DIF are provided in a part of the surface layer of the well WL. The impurity concentration of the high concentration region DIF is higher than the impurity concentration of the well WL. In the example shown in this figure, the source region SOU and the high concentration region DIF are adjacent to each other.
なお、平面視において、ソース領域ＳＯＵと分離絶縁膜ＳＩＮＳ１は互いに離間している。そして、ウェルＷＬの表層のうちソース領域ＳＯＵと分離絶縁膜ＳＩＮＳ１の間に位置する部分がチャネル領域となっている。 Note that the source region SOU and the isolation insulating film SINS1 are separated from each other in plan view. A portion of the surface layer of the well WL located between the source region SOU and the isolation insulating film SINS1 is a channel region.
また、半導体基板ＳＵＢには、ｎ型のドリフト領域ＤＦＴが形成されている。ドリフト領域ＤＦＴは、深さ方向及び平面視の双方において、ドレイン領域ＤＲＮが形成されるべき領域及びその周囲に設けられている。そしてドリフト領域ＤＦＴは、ウェルＷＬに繋がっている。言い換えると、ドリフト領域ＤＦＴの一部は分離絶縁膜ＳＩＮＳ１の下方にも設けられており、かつ、平面視におけるウェルＷＬ側の端部は、分離絶縁膜ＳＩＮＳ１よりもソース領域ＳＯＵ側に位置している。 In addition, an n-type drift region DFT is formed in the semiconductor substrate SUB. The drift region DFT is provided in and around the region where the drain region DRN is to be formed both in the depth direction and in plan view. The drift region DFT is connected to the well WL. In other words, part of the drift region DFT is also provided below the isolation insulating film SINS1, and the end on the well WL side in plan view is located closer to the source region SOU than the isolation insulating film SINS1. Yes.
なお、本図に示す例において、ドリフト領域ＤＦＴとウェルＷＬの深さを同一にしているが、このようにしなくても良い。例えば、ドリフト領域ＤＦＴはウェルＷＬの下にも形成されていても良い。この場合、ドリフト領域ＤＦＴの表層の一部にウェルＷＬが形成されることになる。 In the example shown in the figure, the depths of the drift region DFT and the well WL are the same, but this need not be the case. For example, the drift region DFT may be formed under the well WL. In this case, the well WL is formed in a part of the surface layer of the drift region DFT.
また、半導体基板ＳＵＢの表層のうち、分離絶縁膜ＳＩＮＳ１を挟んでソース領域ＳＯＵの反対側には、ｎ型のドレイン領域ＤＲＮが形成されている An n-type drain region DRN is formed on the surface layer of the semiconductor substrate SUB on the opposite side of the source region SOU across the isolation insulating film SINS1.
そして、半導体基板ＳＵＢの表面のうちソース領域ＳＯＵと分離絶縁膜ＳＩＮＳ１の間に位置する領域には、ゲート絶縁膜ＧＩＮＳが形成されている。ゲート絶縁膜ＧＩＮＳは、例えば半導体基板ＳＵＢを熱酸化することにより形成されている。ゲート絶縁膜ＧＩＮＳ上には、ゲート電極ＧＥが形成されている。ゲート電極ＧＥは、例えばポリシリコンによって形成されている。 A gate insulating film GINS is formed in a region located between the source region SOU and the isolation insulating film SINS1 on the surface of the semiconductor substrate SUB. The gate insulating film GINS is formed, for example, by thermally oxidizing the semiconductor substrate SUB. A gate electrode GE is formed on the gate insulating film GINS. The gate electrode GE is made of, for example, polysilicon.
素子分離膜ＳＩＮＳ及び半導体基板ＳＵＢ上には、層間絶縁膜ＩＮＳＬが形成されている。層間絶縁膜ＩＮＳＬは、例えば酸化シリコン膜である。そして層間絶縁膜ＩＮＳＬには、第１コンタクトＣＯＮ１、第２コンタクトＣＯＮ２、及び第３コンタクトＣＯＮ３が形成されている。第１コンタクトＣＯＮ１は埋込導電層ＣＮＬに接続しており、第２コンタクトＣＯＮ２はソース領域ＳＯＵに接続しており、第３コンタクトＣＯＮ３はドレイン領域ＤＲＮに接続している。また、第２コンタクトＣＯＮ２は高濃度領域ＤＩＦにも接続している。 Over the element isolation film SINS and the semiconductor substrate SUB, an interlayer insulating film INSL is formed. The interlayer insulating film INSL is, for example, a silicon oxide film. A first contact CON1, a second contact CON2, and a third contact CON3 are formed in the interlayer insulating film INSL. The first contact CON1 is connected to the buried conductive layer CNL, the second contact CON2 is connected to the source region SOU, and the third contact CON3 is connected to the drain region DRN. The second contact CON2 is also connected to the high concentration region DIF.
なお、第１コンタクトＣＯＮ１は、第３コンタクトＣＯＮ３との間の耐圧を確保するために、平面視において、埋込導電層ＣＮＬの中心よりも第１コンタクトＣＯＮ１から離れている。 Note that the first contact CON1 is farther from the first contact CON1 than the center of the buried conductive layer CNL in plan view in order to ensure a breakdown voltage between the first contact CON1 and the third contact CON3.
また、層間絶縁膜ＩＮＳＬよりも上層には、配線ＩＮＣが形成されている。配線ＩＮＣは、第２コンタクトＣＯＮ２と第１コンタクトＣＯＮ１を電気的に接続している。配線ＩＮＣは、層間絶縁膜ＩＮＳＬの上（又は表層）に形成されていても良いし、層間絶縁膜ＩＮＳＬよりも上の層間絶縁膜の上（又は表層）に形成されていても良い。 A wiring INC is formed above the interlayer insulating film INSL. The wiring INC electrically connects the second contact CON2 and the first contact CON1. The wiring INC may be formed on the interlayer insulating film INSL (or the surface layer), or may be formed on the interlayer insulating film (or the surface layer) above the interlayer insulating film INSL.
図３〜図６は、図１及び図２に示した半導体装置ＳＤの製造方法を示す断面図である。まず、図３に示すように、半導体基板ＳＵＢを準備する。次いで、半導体基板ＳＵＢに素子分離膜ＳＩＮＳを形成する。このとき、分離絶縁膜ＳＩＮＳ１も形成される。 3 to 6 are cross-sectional views showing a method for manufacturing the semiconductor device SD shown in FIGS. First, as shown in FIG. 3, a semiconductor substrate SUB is prepared. Next, an element isolation film SINS is formed on the semiconductor substrate SUB. At this time, an isolation insulating film SINS1 is also formed.
次いで、半導体基板ＳＵＢ上及び素子分離膜ＳＩＮＳ上に、レジストパターン（図示せず）を形成し、このレジストパターンをマスクとして半導体基板ＳＵＢにｐ型の不純物を導入する。これにより、ウェルＷＬが形成される。その後、レジストパターンを除去する。次いで、半導体基板ＳＵＢ上及び素子分離膜ＳＩＮＳ上に、レジストパターン（図示せず）を形成し、このレジストパターンをマスクとして半導体基板ＳＵＢにｎ型の不純物を導入する。これにより、ドリフト領域ＤＦＴが形成される。その後、レジストパターンを除去する。 Next, a resist pattern (not shown) is formed on the semiconductor substrate SUB and the element isolation film SINS, and p-type impurities are introduced into the semiconductor substrate SUB using the resist pattern as a mask. Thereby, the well WL is formed. Thereafter, the resist pattern is removed. Next, a resist pattern (not shown) is formed on the semiconductor substrate SUB and the element isolation film SINS, and n-type impurities are introduced into the semiconductor substrate SUB using the resist pattern as a mask. Thereby, the drift region DFT is formed. Thereafter, the resist pattern is removed.
次いで、図４に示すように、半導体基板ＳＵＢ上及び素子分離膜ＳＩＮＳ上にレジストパターンＰＲを形成する。レジストパターンＰＲは、凹部ＤＥＰが形成されるべき領域に開口を有している。そして、レジストパターンＰＲをマスクとして分離絶縁膜ＳＩＮＳ１をエッチングする。これにより、凹部ＤＥＰが形成される。 Next, as illustrated in FIG. 4, a resist pattern PR is formed on the semiconductor substrate SUB and the element isolation film SINS. The resist pattern PR has an opening in a region where the recess DEP is to be formed. Then, the isolation insulating film SINS1 is etched using the resist pattern PR as a mask. Thereby, the recessed part DEP is formed.
その後、図５に示すように、レジストパターンＰＲを除去する。次いで、凹部ＤＥＰ内、半導体基板ＳＵＢ上、及び素子分離膜ＳＩＮＳ上に、埋込導電層ＣＮＬとなる導電膜（例えばｐ型のポリシリコン膜）をＣＶＤ法により形成する。次いで、この導電膜のうち素子分離膜ＳＩＮＳ上及び半導体基板ＳＵＢ上に位置する部分を、ＣＭＰ法又はエッチバック法により除去する。これにより、凹部ＤＥＰ内には埋込導電層ＣＮＬが埋め込まれる。 Thereafter, as shown in FIG. 5, the resist pattern PR is removed. Next, a conductive film (for example, a p-type polysilicon film) to be a buried conductive layer CNL is formed by CVD in the recess DEP, on the semiconductor substrate SUB, and on the element isolation film SINS. Next, portions of the conductive film located on the element isolation film SINS and the semiconductor substrate SUB are removed by a CMP method or an etch back method. As a result, the embedded conductive layer CNL is embedded in the recess DEP.
次いで、図６に示すように、半導体基板ＳＵＢにゲート絶縁膜ＧＩＮＳを形成する。ゲート絶縁膜ＧＩＮＳは、例えば熱酸化法により形成されるが、他の方法によって形成されても良い。ついで、ゲート絶縁膜ＧＩＮＳ上、半導体基板ＳＵＢ上、素子分離膜ＳＩＮＳ上、及び埋込導電層ＣＮＬ上に、ゲート電極ＧＥとなる導電膜（例えばポリシリコン膜）を形成する。次いで、このポリシリコン膜上にレジストパターン（図示せず）を形成し、このレジストパターンをマスクとして、ポリシリコン膜をエッチングする。これにより、ゲート絶縁膜ＧＩＮＳ上にはゲート電極ＧＥが形成される。その後、レジストパターンを除去する。 Next, as shown in FIG. 6, a gate insulating film GINS is formed on the semiconductor substrate SUB. The gate insulating film GINS is formed by, for example, a thermal oxidation method, but may be formed by another method. Next, a conductive film (for example, a polysilicon film) to be the gate electrode GE is formed on the gate insulating film GINS, the semiconductor substrate SUB, the element isolation film SINS, and the buried conductive layer CNL. Next, a resist pattern (not shown) is formed on the polysilicon film, and the polysilicon film is etched using the resist pattern as a mask. Thereby, the gate electrode GE is formed on the gate insulating film GINS. Thereafter, the resist pattern is removed.
次いで、半導体基板ＳＵＢ上、埋込導電層ＣＮＬ上、素子分離膜ＳＩＮＳ上、及びゲート電極ＧＥ上にレジストパターン（図示せず）を形成し、このレジストパターンをマスクとして半導体基板ＳＵＢにｎ型の不純物をイオン注入する。これにより、ソース領域ＳＯＵ及びドレイン領域ＤＲＮが形成される。その後、レジストパターンを除去する。 Next, a resist pattern (not shown) is formed on the semiconductor substrate SUB, the buried conductive layer CNL, the element isolation film SINS, and the gate electrode GE. Using this resist pattern as a mask, an n-type is formed on the semiconductor substrate SUB. Impurities are ion-implanted. Thereby, the source region SOU and the drain region DRN are formed. Thereafter, the resist pattern is removed.
次いで、半導体基板ＳＵＢ上、埋込導電層ＣＮＬ上、素子分離膜ＳＩＮＳ上、及びゲート電極ＧＥ上にレジストパターン（図示せず）を形成し、このレジストパターンをマスクとして半導体基板ＳＵＢにｐ型の不純物をイオン注入する。これにより、高濃度領域ＤＩＦが形成される。その後、レジストパターンを除去する。 Next, a resist pattern (not shown) is formed on the semiconductor substrate SUB, the buried conductive layer CNL, the element isolation film SINS, and the gate electrode GE, and a p-type is formed on the semiconductor substrate SUB using the resist pattern as a mask. Impurities are ion-implanted. Thereby, the high concentration region DIF is formed. Thereafter, the resist pattern is removed.
次いで、半導体基板ＳＵＢ上、埋込導電層ＣＮＬ上、素子分離膜ＳＩＮＳ上、及びゲート電極ＧＥ上に、層間絶縁膜ＩＮＳＬを、例えばＣＶＤ法を用いて形成する。次いで、層間絶縁膜ＩＮＳＬに接続孔を形成し、この接続孔内に導体を埋め込む。これにより、第１コンタクトＣＯＮ１、第２コンタクトＣＯＮ２、及び第３コンタクトＣＯＮ３を形成する。 Next, an interlayer insulating film INSL is formed on the semiconductor substrate SUB, the buried conductive layer CNL, the element isolation film SINS, and the gate electrode GE by using, for example, a CVD method. Next, a connection hole is formed in the interlayer insulating film INSL, and a conductor is embedded in the connection hole. Thereby, the first contact CON1, the second contact CON2, and the third contact CON3 are formed.
その後、層間絶縁膜ＩＮＳＬ上に、必要な数の配線層を形成する。これらの配線層内には、配線ＩＮＣが含まれる。また、最上層の配線層には、電極パッドが形成される。 Thereafter, a necessary number of wiring layers are formed on the interlayer insulating film INSL. The wiring INC is included in these wiring layers. An electrode pad is formed on the uppermost wiring layer.
図７（ａ）は、半導体装置ＳＤにおける不純物プロファイルのシミュレーション結果を示す図であり、図７（ｂ）は、半導体装置ＳＤが図７（ａ）の不純物プロファイルを有する場合における、電位分布のシミュレーション結果を示す図である。図７（ｂ）に示すシミュレーションにお知恵、埋込導電層ＣＮＬには固定電位、例えばソース電位（接地電位）が印加されている。図７（ｂ）に示す結果から、埋込導電層ＣＮＬを設け、かつ埋込導電層ＣＮＬに固定電位を印加することにより、半導体基板ＳＵＢに電界が集中する部分は存在しなくなっている。従って、半導体装置ＳＤにおいて、ドレイン領域ＤＲＮとゲート電極ＧＥの間の耐圧を高めることができる。 FIG. 7A is a diagram showing a simulation result of the impurity profile in the semiconductor device SD, and FIG. 7B is a simulation of the potential distribution when the semiconductor device SD has the impurity profile in FIG. It is a figure which shows a result. In the simulation shown in FIG. 7B, a fixed potential, for example, a source potential (ground potential) is applied to the buried conductive layer CNL. From the result shown in FIG. 7B, by providing the buried conductive layer CNL and applying a fixed potential to the buried conductive layer CNL, there is no portion where the electric field concentrates on the semiconductor substrate SUB. Therefore, the breakdown voltage between the drain region DRN and the gate electrode GE can be increased in the semiconductor device SD.
なお、本実施形態においてドレイン領域ＤＲＮとゲート電極ＧＥの間の耐圧が高まるのは、埋込導電層ＣＮＬに固定電位が印加されることにより、ドリフト領域ＤＦＴ内に空乏層が形成されるためである。このような空乏層は、埋込導電層ＣＮＬがフローティング電位になっている場合には形成されない。 In the present embodiment, the breakdown voltage between the drain region DRN and the gate electrode GE is increased because a depletion layer is formed in the drift region DFT by applying a fixed potential to the buried conductive layer CNL. is there. Such a depletion layer is not formed when the buried conductive layer CNL is at a floating potential.
図８は、ドレイン−ゲート電極間の耐圧と、トランジスタのオン抵抗の相関を示すグラフである。点線は、埋込導電層ＣＮＬを設けない場合（比較例）の相関を示している。電力を制御するトランジスタにおいて、ドレイン領域とゲート電極の間の耐圧を高めることの他に、オン抵抗を低くすることも必要である。しかし、本図において点線で示すように、ドレイン領域とゲート電極の間の耐圧と、オン抵抗はトレードオフの関係にあるため、これらを両立することは難しい。これに対して実施形態に係る半導体装置ＳＤは、比較例と比較して、ドレイン領域とゲート電極の間の耐圧を維持しつつ、オン抵抗を低くすることができる。 FIG. 8 is a graph showing the correlation between the breakdown voltage between the drain and gate electrodes and the on-resistance of the transistor. The dotted line shows the correlation when the buried conductive layer CNL is not provided (comparative example). In a transistor for controlling power, in addition to increasing the breakdown voltage between the drain region and the gate electrode, it is necessary to reduce the on-resistance. However, as indicated by the dotted line in this figure, since the breakdown voltage between the drain region and the gate electrode and the on-resistance are in a trade-off relationship, it is difficult to achieve both. On the other hand, the semiconductor device SD according to the embodiment can reduce the on-resistance while maintaining the breakdown voltage between the drain region and the gate electrode, as compared with the comparative example.
以上、本実施形態によれば、素子分離膜ＳＩＮＳのうちゲート電極ＧＥとドレイン領域ＤＲＮの間に位置する部分（分離絶縁膜ＳＩＮＳ１）には、埋込導電層ＣＮＬが埋め込まれている。そして埋込導電層ＣＮＬには固定電位が印加されている。このため、ドリフト領域ＤＦＴには空乏層が形成されるため、ドレイン領域ＤＲＮとゲート電極ＧＥの間の耐圧は高くなる。 As described above, according to the present embodiment, the buried conductive layer CNL is buried in a portion (isolation insulating film SINS1) located between the gate electrode GE and the drain region DRN in the element isolation film SINS. A fixed potential is applied to the buried conductive layer CNL. For this reason, since a depletion layer is formed in the drift region DFT, the breakdown voltage between the drain region DRN and the gate electrode GE is increased.
また、キャリアがドリフト領域ＤＦＴ内を移動する際、ドリフト領域ＤＦＴにはホットキャリアが発生する。このホットキャリアの一部は分離絶縁膜ＳＩＮＳ１にトラップされる。ホットキャリアが分離絶縁膜ＳＩＮＳ１にトラップされると、分離絶縁膜ＳＩＮＳ１がドリフト領域ＤＦＴ内の電界分布に影響を与えてしまい、その結果、トランジスタの特性が変化してしまう。 Further, when carriers move in the drift region DFT, hot carriers are generated in the drift region DFT. A part of this hot carrier is trapped in the isolation insulating film SINS1. When hot carriers are trapped in the isolation insulating film SINS1, the isolation insulating film SINS1 affects the electric field distribution in the drift region DFT, and as a result, the transistor characteristics change.
これに対して本実施形態では、埋込導電層ＣＮＬはｐ型の半導体層であり、ｎ型のドレイン領域ＤＲＮに接している。このため、分離絶縁膜ＳＩＮＳ１にトラップされたキャリアが電子の場合、このキャリアはドレイン領域ＤＲＮを介して第３コンタクトＣＯＮ３に引き抜かれる。また、分離絶縁膜ＳＩＮＳ１にトラップされたキャリアが正孔の場合、このキャリアは第１コンタクトＣＯＮ１に引き抜かれる。従って、上記したトランジスタの特性変動を抑制できる。 On the other hand, in the present embodiment, the buried conductive layer CNL is a p-type semiconductor layer and is in contact with the n-type drain region DRN. Therefore, when the carriers trapped in the isolation insulating film SINS1 are electrons, the carriers are extracted to the third contact CON3 through the drain region DRN. Further, when the carriers trapped in the isolation insulating film SINS1 are holes, the carriers are extracted by the first contact CON1. Therefore, the above-described transistor characteristic fluctuation can be suppressed.
（第２の実施形態）
図９は、第２の実施形態に係る半導体装置ＳＤの構成を示す断面図である。本実施形態に係る半導体装置ＳＤは、素子分離膜ＳＩＮＳがＬＯＣＯＳ法を用いて形成されている点を除いて、第１の実施形態に係る半導体装置ＳＤと同様の構成である。
本実施形態によっても、第１の実施形態と同様の効果が得られる。
(Second Embodiment)
FIG. 9 is a cross-sectional view showing the configuration of the semiconductor device SD according to the second embodiment. The semiconductor device SD according to the present embodiment has the same configuration as that of the semiconductor device SD according to the first embodiment, except that the element isolation film SINS is formed using the LOCOS method.
According to this embodiment, the same effect as that of the first embodiment can be obtained.
（第３の実施形態）
図１０は、第３の実施形態に係る半導体装置ＳＤの構成を示す断面図である。図１１は図１０に示した半導体装置ＳＤの平面図である。本実施形態に係る半導体装置ＳＤは、埋込導電層ＣＮＬがドレイン領域ＤＲＮから離れており、分離絶縁膜ＳＩＮＳ１の側面がドレイン領域ＤＲＮに接している点を除いて、第１の実施形態又は第２の実施形態に係る半導体装置ＳＤと同様の構成である。
(Third embodiment)
FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device SD according to the third embodiment. FIG. 11 is a plan view of the semiconductor device SD shown in FIG. In the semiconductor device SD according to the present embodiment, the buried conductive layer CNL is separated from the drain region DRN, and the side surface of the isolation insulating film SINS1 is in contact with the drain region DRN, except for the first embodiment or the first embodiment. The configuration is the same as that of the semiconductor device SD according to the second embodiment.
本実施形態によっても、ドリフト領域ＤＦＴには空乏層が形成されるため、ドレイン領域ＤＲＮとゲート電極ＧＥの間の耐圧を高めることができる。なお、本実施形態においては、埋込導電層ＣＮＬはｎ型の半導体層であっても良い。 Also according to this embodiment, since a depletion layer is formed in the drift region DFT, the breakdown voltage between the drain region DRN and the gate electrode GE can be increased. In the present embodiment, the buried conductive layer CNL may be an n-type semiconductor layer.
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
ＣＯＮ１ 第１コンタクト
ＣＯＮ２ 第２コンタクト
ＣＯＮ３ 第３コンタクト
ＣＮＬ 埋込導電層
ＤＥＰ 凹部
ＤＦＴ ドリフト領域
ＤＩＦ 高濃度領域
ＤＲＮ ドレイン領域
ＧＥ ゲート電極
ＧＩＮＳ ゲート絶縁膜
ＩＮＣ 配線
ＩＮＳＬ 層間絶縁膜
ＰＲ レジストパターン
ＳＤ 半導体装置
ＳＩＮＳ 素子分離膜
ＳＯＵ ソース領域
ＳＵＢ 半導体基板
ＷＬ ウェル
CON1 First contact CON2 Second contact CON3 Third contact CNL Buried conductive layer DEP Recess DFT Drift region DIF High concentration region DRN Drain region GE Gate electrode GINS Gate insulating film INC Wiring INSL Interlayer insulating film PR Resist pattern SD Semiconductor device SINS Element Separation film SOU Source region SUB Semiconductor substrate WL Well
Claims (4)
前記半導体基板上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記半導体基板に形成されており、平面視で前記ゲート電極を挟んでいる第１導電型のソース領域及び第１導電型のドレイン領域と、
を備え、
前記ゲート電極と前記ドレイン領域の間隔は、前記ゲート電極と前記ソース領域の間隔よりも広く、
さらに、
前記半導体基板に設けられ、前記ゲート電極と前記ドレイン領域の間に位置する分離絶縁膜と、
前記分離絶縁膜に埋め込まれており、底部が前記分離絶縁膜の底部よりも上に位置している埋込導電層と、
前記半導体基板上に形成された層間絶縁膜と、
前記層間絶縁膜に埋め込まれ、前記埋込導電層に接続する第１コンタクトと、
を備える半導体装置。 A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A first conductivity type source region and a first conductivity type drain region formed on the semiconductor substrate and sandwiching the gate electrode in plan view;
With
The gap between the gate electrode and the drain region is wider than the gap between the gate electrode and the source region,
further,
An isolation insulating film provided on the semiconductor substrate and positioned between the gate electrode and the drain region;
A buried conductive layer embedded in the isolation insulating film and having a bottom located above the bottom of the isolation insulating film;
An interlayer insulating film formed on the semiconductor substrate;
A first contact embedded in the interlayer insulating film and connected to the embedded conductive layer;
A semiconductor device comprising:
前記埋込導電層は、第２導電型の半導体層であり、
前記埋込導電層は前記ドレイン領域に接している半導体装置。 The semiconductor device according to claim 1,
The buried conductive layer is a semiconductor layer of a second conductivity type,
The embedded conductive layer is a semiconductor device in contact with the drain region.
前記分離絶縁膜は前記ドレイン領域に接しており、
前記埋込導電層は前記ドレイン領域に接していない半導体装置。 The semiconductor device according to claim 1,
The isolation insulating film is in contact with the drain region;
A semiconductor device in which the buried conductive layer is not in contact with the drain region.
前記層間絶縁膜に埋め込まれ、前記ソース領域に接続する第２コンタクトと、
前記第１コンタクトと前記第２コンタクトを電気的に接続する配線と、
を備える半導体装置。 The semiconductor device according to claim 1,
A second contact embedded in the interlayer insulating film and connected to the source region;
Wiring for electrically connecting the first contact and the second contact;
A semiconductor device comprising:
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| JP2013087558A JP2014212203A (en) | 2013-04-18 | 2013-04-18 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2013087558A JP2014212203A (en) | 2013-04-18 | 2013-04-18 | Semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123681A (en) * | 2016-02-25 | 2017-09-01 | 瑞萨电子株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN108091681A (en) * | 2016-11-21 | 2018-05-29 | 瑞萨电子株式会社 | The manufacturing method of semiconductor devices and semiconductor devices |
| JP2019106554A (en) * | 2019-04-02 | 2019-06-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2023171454A1 (en) * | 2022-03-08 | 2023-09-14 | ローム株式会社 | Semiconductor device |
-
2013
- 2013-04-18 JP JP2013087558A patent/JP2014212203A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123681A (en) * | 2016-02-25 | 2017-09-01 | 瑞萨电子株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN108091681A (en) * | 2016-11-21 | 2018-05-29 | 瑞萨电子株式会社 | The manufacturing method of semiconductor devices and semiconductor devices |
| CN108091681B (en) * | 2016-11-21 | 2023-09-19 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP2019106554A (en) * | 2019-04-02 | 2019-06-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2023171454A1 (en) * | 2022-03-08 | 2023-09-14 | ローム株式会社 | Semiconductor device |
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