JP2010165894A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for controlling the degradation of pressure resistance and the change of a threshold voltage by gate pulse stress. <P>SOLUTION: A gate electrode GE is formed on a region in between a source region and a drift region DR via an insulation layer FO. A field plate FP extends over the gate electrode GE and the drift region DR and is electrically connected to the gate electrode GE. A dummy conductive layer DC is formed on the insulation layer FO between the field plate FP and the drift region DR and electrically connected to the source region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a lateral insulated gate field effect transistor.

  For example, a high-voltage lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used in plasma display panel (PDP) drivers and automobiles has a thick oxide film such as an isolation oxide film so that a high voltage can be input. Is used as a gate oxide film. An element having such a MOSFET portion is disclosed, for example, in Non-Patent Document 1 below.

T. Nitta et al., "Wide Voltage Power Device Implementation in 0.25μm SOI BiC-DMOS", Proceedings of the 18th International Symposium on Power Semiconductor Devices & IC's JUNE 4-8, 2006 Naples, Italy

  However, the MOSFET structure as described above has a problem that withstand voltage deterioration due to gate pulse stress is large. It is also important to suppress fluctuations in the threshold voltage.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device which can input a high voltage and can suppress breakdown voltage deterioration and threshold voltage fluctuation due to gate pulse stress. is there.

  The semiconductor device of this embodiment includes a semiconductor substrate, an insulating layer, a lateral insulated gate field effect transistor, a field plate, and a dummy conductive layer. The semiconductor substrate has a main surface. The insulating layer is selectively formed on the main surface of the semiconductor substrate. The lateral insulated gate field effect transistor is formed on a semiconductor substrate. This insulated gate field effect transistor includes a source region and a drain region, a drift region, and a gate electrode. The source region and the drain region are formed on the main surface of the semiconductor substrate on each side of the insulating layer. The drift region is connected to the drain region. The gate electrode is formed on a region sandwiched between the source region and the drift region with an insulating layer interposed. The field plate extends over the gate electrode and the drift region and is electrically connected to the gate electrode. The dummy conductive layer includes a first conductor formed on the insulating layer between the field plate and the drift region and electrically connected to the source region.

  According to the semiconductor device of the present embodiment, the first conductor electrically connected to the source region is formed between the field plate and the drift region. The fluctuation of the value voltage can be suppressed.

FIG. 4 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view of a portion along line II in FIG. 3. FIG. 2 is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention, showing the same layer as the gate electrode and a layer below it. FIG. 2 is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention, and is a plan view showing the same layer as the field plate and a layer below it. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is sectional drawing of the part which follows the II line | wire of FIG. FIG. 4 is a schematic cross-sectional view showing a second step of the method for manufacturing the semiconductor device in the first embodiment of the present invention, and is a cross-sectional view taken along a line II in FIG. 3. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is sectional drawing of the part which follows the II line | wire of FIG. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is sectional drawing of the part which follows the II line | wire of FIG. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is sectional drawing of the part which follows the II line | wire of FIG. FIG. 4 is a cross-sectional view schematically showing a configuration of a horizontal type high voltage insulated gate field effect transistor in which a field plate is electrically connected to a source region and does not have a dummy conductive layer, and is taken along line II in FIG. 3. It is sectional drawing corresponding to a part. FIG. 4 is a cross-sectional view schematically showing a configuration of a horizontal type high-voltage insulated gate field effect transistor in which a field plate is electrically connected to a gate electrode and does not have a dummy conductive layer, and is taken along line II in FIG. 3. It is sectional drawing corresponding to a part. FIG. 4 is a cross-sectional view schematically showing a configuration of a lateral high-breakdown-voltage insulated gate field effect transistor in which a field plate and a dummy conductive layer are electrically connected to a source region, in a portion along line II in FIG. 3. FIG. It is a figure which shows the result of the pressure | voltage resistant deterioration by gate pulse stress, Comprising: It is a figure which shows the relationship between the frequency | count of pulse stress application, and a pressure | voltage resistant deterioration amount. FIG. 4 is a first schematic cross-sectional view for explaining a prediction mechanism of breakdown voltage degradation due to gate pulse stress, and is a cross-sectional view corresponding to a portion along line II in FIG. 3. FIG. 4 is a second schematic cross-sectional view for explaining a prediction mechanism of breakdown voltage degradation due to gate pulse stress, and is a cross-sectional view corresponding to a portion along line II in FIG. 3. It is a 3rd schematic sectional drawing for demonstrating the prediction mechanism of the pressure | voltage resistant deterioration by gate pulse stress, and is sectional drawing corresponding to the part in alignment with the II line | wire of FIG. The current capability (drain current Ids) and threshold value in the case where the length ps of the dummy conductive layer is changed in the configuration of FIG. 1 and in the case where the length AGFP of the field plate is changed in the configuration of FIG. It is a figure which shows the relationship with the variation | change_quantity ((DELTA) Vth) of a voltage. FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention, and is a diagram showing a configuration when a dummy conductive layer has a plurality of conductors; It is sectional drawing corresponding to the part which follows.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
Referring to FIG. 1, the semiconductor device according to the present embodiment mainly includes a semiconductor substrate SU, a lateral high breakdown voltage insulated gate field effect transistor, a field plate FP, and a dummy conductive layer DC. .

  The semiconductor substrate SU has, for example, an SOI (Silicon On Insulator) structure, and has a configuration in which a support substrate SS, a BOX (Buried Oxide) layer BI, and a semiconductor layer SL are stacked in this order. Semiconductor layer SL has, for example, an n-type conductivity type.

  An insulating layer FO is selectively formed on the surface of the semiconductor substrate SU (the surface of the semiconductor layer SL). This insulating layer FO may be composed of an insulating layer for element isolation such as a field oxide film. The field oxide film is an oxide film formed by a LOCOS (Local Oxidation of Silicon) method. The insulating layer FO may be a thick insulating layer having a thickness of, for example, 400 nm or more other than the field oxide film, or may be an insulating layer filling the trench in the STI (Shallow Trench Isolation) structure. .

  The lateral high-voltage insulated gate field effect transistor is formed on the semiconductor substrate SU (semiconductor layer SL). This high breakdown voltage insulated gate field effect transistor mainly has drain regions PW1 and PR1, source regions PW2 and PR2, a drift region DR, and a gate electrode GE.

  The drain regions PW1 and PR1 and the source regions PW2 and PR2 are formed on the surface of the semiconductor substrate SU on both sides of the insulating layer FO. That is, drain regions PW1 and PR1 are formed on the surface of the semiconductor substrate SU (the surface of the semiconductor layer SL) at one end (right end in the drawing) of the insulating layer FO, and the other end ( Source regions PW2 and PR2 are formed on the surface of the semiconductor substrate SU at the left end in the drawing.

The drain region has a p-type well region PW1 and a p ⁺ region PR1 having a p-type impurity concentration higher than that of the p-type well region PW1. The p ⁺ region PR1 is formed on the surface of the semiconductor substrate SU where the insulating layer FO is not formed. p-type well region PW1 is adjacent to the p ⁺ region PR1, and is formed to surround the p ⁺ region PR1, partially located on the lower side of the insulating layer FO.

The source region has a p-type well region PW2 and a p ⁺ region PR2 having a p-type impurity concentration higher than that of the p-type well region PW2. The p ⁺ region PR2 is formed on the surface of the semiconductor substrate SU where the insulating layer FO is not formed. p-type well region PW2 is adjacent to the p ⁺ region PR2, and is formed to surround the lower p ⁺ region PR2, partially located on the lower side of the insulating layer FO.

The p ⁻ drift region DR is a p ⁻ region having a p type impurity concentration lower than that of the p type well region PW1. The p ⁻ drift region DR is adjacent to the p-type well region PW1 in the drain region, and is located at least on the source side of the drain region. Further, the portion of the p ⁻ drift region DR located on the source side with respect to the drain region is located directly below the insulating layer FO.

In the semiconductor layer SL, an n-type well region NW is formed so as to be adjacent to the side portion of the p-type well region PW2. In the semiconductor layer SL, an n ⁺ region NR is formed so as to be adjacent to the side portion of the p ⁺ region PR2 and to be adjacent to the upper portion of the n-type well region NW. A bottom n-type region BN is formed so as to be in contact with the bottoms of the n-type well region NW and the p-type well region PW2.

A silicide layer SC1 is formed on the p ⁺ region PR1, a silicide layer SC2 is formed on the p ⁺ region PR2, and a silicide layer SC3 is formed on the n ⁺ region NR. Each of these silicide layers SC1, SC2, SC3 is made of, for example, cobalt silicide (CoSi ₂ ).

Gate electrode GE is formed on the n ⁻ region of semiconductor layer SL sandwiched between p type well region PW2 and p ⁻ drift region DR and in contact with the upper surface of insulating layer FO. The entire gate electrode GE is in contact with the upper surface of the insulating layer FO.

The dummy conductive layer DC is formed on the p ⁻ drift region DR and in contact with the upper surface of the insulating layer FO. The dummy conductive layer DC is electrically connected to the source regions PW2 and PR2.

Each of the gate electrode GE and the dummy conductive layer DC has a stacked structure of, for example, a polycrystalline silicon layer doped with impurities (hereinafter referred to as a doped polysilicon layer) and a silicide layer made of, for example, tungsten silicide (WSi ₂ ). have.

  An insulating layer CI is formed on the upper surfaces of the gate electrode GE and the dummy conductive layer DC. A sidewall insulating layer SW is formed on each of the sidewalls of the gate electrode GE and the insulating layer CI and the sidewalls of the dummy conductive layer DC and the insulating layer CI. These insulating layers CI and sidewall insulating layers SW are made of, for example, a silicon oxide film using TEOS (Tetra Ethyl Ortho Silicate) as a raw material.

  An interlayer insulating layer II is formed on the semiconductor substrate SU (semiconductor layer SL) so as to cover the high breakdown voltage insulated gate field effect transistor. This interlayer insulating layer II is made of, for example, a silicon oxide film using TEOS as a raw material.

A drain wiring DI, a source wiring SI, and a field plate FP are formed on the upper surface of the interlayer insulating layer II. Drain wiring DI is electrically connected to drain regions PW1 and PR1 through plug conductive layer PL filling contact hole CH4. Source line SI is electrically connected to source regions PW2 and PR2 via plug conductive layer PL filling contact hole CH2. Source wiring SI is also electrically connected to n ⁺ region NR and n-type well region NW via plug conductive layer PL filling contact hole CH5.

Field plate FP is formed on the upper surface of interlayer insulating layer II so as to extend on p ⁻ drift region DR. Field plate FP is electrically connected to gate electrode GE via plug conductive layer PL filling contact hole CH3. The field plate FP is made of a metal layer made of a material containing aluminum, for example.

The dummy conductive layer DC is located between the field plate FP and the p ⁻ drift region DR. The dummy conductive layer DC is located on the source side (left side in the figure) with respect to the drain side end FPE of the field plate FP.

  Note that the thickness of the insulating layer FO is preferably equal to or greater than the thickness at which the insulating layer FO does not break down against the operating voltage. For example, when the operating voltage is 100 V, the thickness of the insulating layer FO is preferably 100 nm or more, and when the operating voltage is 200 V, the thickness of the insulating layer FO is preferably 200 nm or more. In addition, the upper limit of the thickness of the insulating layer FO is preferably about three times the film thickness that does not break down with respect to the operating voltage. For example, when the operating voltage is 100V, the upper limit of the thickness of the insulating layer FO is preferably 300 nm or less, and when the operating voltage is 200V, the upper limit of the thickness of the insulating layer FO is preferably 600 nm or less.

Referring to FIG. 2, p ⁺ region PR2 constituting the source region is formed so as to surround the periphery of n ⁺ region NR in plan view. The p ⁺ region PR1 constituting the drain region is formed so as to surround the p ⁺ region PR2 with the insulating layer FO interposed in plan view.

Gate electrode GE is formed so as to surround the periphery of p ⁺ region PR2 in plan view. The dummy conductive layer DC is formed so as to surround the gate electrode GE in plan view.

Referring to FIG. 3, source line SI extends from n ⁺ region NR and p ⁺ region PR2 so as to extend onto dummy conductive layer DC in plan view. Source wiring SI is electrically connected to n ⁺ region NR via a plug conductive layer filling contact hole CH5, and electrically connected to p ⁺ region PR2 via a plug conductive layer filling contact hole CH2. And electrically connected to the dummy conductive layer DC through a plug conductive layer filling the contact hole CH1. Thereby, the dummy conductive layer DC is electrically connected to the source regions PW2 and PR2 via the source wiring SI.

The drain wiring DI is formed on the p ⁺ region PR1 in a plan view and surrounds the source wiring SI. Drain wiring DI is electrically connected to p ⁺ region PR1 through a plug conductive layer filling contact hole CH4.

  The field plate FP is located on the outer peripheral side of the source wiring SI and on the inner peripheral side of the drain wiring DI in plan view. Thereby, the field plate FP is formed so as to surround the source wiring SI in a plan view. Field plate FP is electrically connected to gate electrode GE via a plug conductive layer filling contact hole CH3.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
Referring to FIG. 4, a wafer having an SOI structure, for example, is prepared as a semiconductor substrate SU. An insulating layer (field oxide film) FO is formed on the surface of the semiconductor substrate SU (surface of the semiconductor layer SL) by, for example, the LOCOS method.

Thereafter, ion implantation or the like is appropriately performed to form p-type well regions PW1 and PW2, an n-type well region NW, a bottom n-type region BN, and a p ⁻ drift region DR in the semiconductor layer SL. Ion implantation may be performed before the insulating layer FO.

  Thereafter, oxide film IN is formed on the surface of semiconductor layer SL, for example, by oxidation. Thereafter, a conductive layer PS and an insulating layer CI are sequentially stacked over the entire surface of the semiconductor layer SL.

  Conductive layer PS is formed, for example, to have a stacked structure of a doped polysilicon layer and a silicide layer. The insulating layer CI is formed of, for example, a silicon oxide film using TEOS as a raw material.

  Referring to FIG. 5, conductive layer PS and insulating layer CI are patterned by photolithography and etching techniques. Thereby, the gate electrode GE and the dummy conductive layer DC are formed from the conductive layer PS. Further, the oxide film IN is removed, and a part of the surface of the semiconductor layer SL is exposed.

Referring to FIG. 6, n ⁺ region NR is formed on the surface of n type well region NW by ion implantation or the like. Thereafter, an insulating layer SW made of, for example, a silicon oxide film using TEOS as a raw material is formed on the entire surface of the semiconductor layer SL. Thereafter, the insulating layer SW is removed by etching until at least the surface of the insulating layer CI is exposed. As a result, the insulating layer SW remains so as to cover the respective side walls of the gate electrode GE and the dummy conductive layer DC, and becomes the side wall insulating layer SW.

Referring to FIG. 7, p ⁺ regions PR1 and PR2 are formed on the surfaces of p-type well regions PW1 and PW2 by ion implantation or the like.

  Referring to FIG. 8, for example, a metal layer containing a refractory metal is formed on the entire surface of semiconductor layer SL. Thereafter, heat treatment such as RTA (Rapid Thermal Annealing) is performed. Thereby, the refractory metal reacts with the silicon of the semiconductor layer SL to form silicide layers SC1, SC2, and SC3. Thereafter, the unreacted metal layer is removed.

  Referring to FIG. 1, interlayer insulating layer II made of, for example, a silicon oxide film using TEOS as a raw material is formed on the entire surface of semiconductor layer SL. Contact holes CH1 to CH5 are formed in the interlayer insulating layer II by photolithography and etching techniques. Each of these contact holes CH1 to CH5 is filled with a plug conductive layer PL. A metal layer made of, for example, a material containing tungsten or a material containing aluminum is formed on interlayer insulating layer II. This metal layer is patterned by photolithography and etching techniques to form drain wiring DI, source wiring SI, field plate FP, and the like from the metal layer.

Thus, the semiconductor device of the present embodiment shown in FIG. 1 is manufactured.
Next, a description will be given of a method and results of measuring the breakdown voltage deterioration amount and the threshold voltage fluctuation amount due to gate pulse stress in the semiconductor devices of this embodiment and the comparative example.

  First, regarding the breakdown voltage degradation amount due to gate pulse stress, the configuration of the present embodiment shown in FIG. 1 and the configurations of three types of comparative examples shown in FIGS. 9 to 11 were examined.

  The configuration of FIG. 9 is different from the configuration of the present embodiment shown in FIG. 1 in that the field plate is integrated with the source wiring SI to be at the source potential and the dummy conductive layer is not provided. Is different.

  10 differs from the configuration of the present embodiment shown in FIG. 1 in that no dummy conductive layer is provided.

  Further, the configuration of FIG. 11 is different from the configuration of the present embodiment shown in FIG. 1 in that the field plate is integrated with the source wiring SI to become the source potential and the dummy conductive layer is connected to the source wiring SI. And the source potential is different.

  9 to 11 are substantially the same as those of the first embodiment shown in FIG. 1, and therefore, the same elements are denoted by the same reference numerals and the description thereof is omitted.

  With respect to the above four configurations (configurations shown in FIGS. 1 and 9 to 11), the breakdown voltage degradation due to gate pulse stress was measured by the following method.

(A1) The off breakdown voltage was measured.
(A2) Gate stress was applied in pulses.

(A3) The off breakdown voltage was measured.
(A4) The above (A2) and (A3) were repeated.

  FIG. 12 shows the result of the breakdown voltage degradation amount due to the gate pulse stress measured by the above method. From the results of FIG. 12, it was found that the breakdown voltage degradation is increased by the gate pulse stress in each configuration of FIG. 9 and FIG. 11, but the breakdown voltage is hardly deteriorated by the gate pulse stress in each configuration of FIG.

This result is considered to be due to the following reasons.
For example, in the configuration shown in FIG. 9, the field plate is integrated with the source wiring SI to become the source potential. In the off state of this configuration, as shown in FIG. 13, the source potential Vs is 0 V, the drain potential Vd is −BV, the gate potential Vg is 0 V, and the potential Vback of the support substrate SS is Vd. In this case, an electric field is generated in the horizontal direction in the figure between the source region and the drain region. In view of this, by using the source wiring SI as a field plate and applying a potential of Vd to the support substrate SS, the horizontal electric field in the figure is controlled to be uniform.

  However, as shown in FIG. 14, when a pulse stress is applied to the gate electrode GE, polarization occurs in the interlayer insulating layer II due to an electric field applied between the gate electrode GE and the source wiring SI. Due to this polarization, the negative charge is biased on the source wiring SI side (upper side in the figure) of the interlayer insulating layer II, and the positive charge is biased on the gate electrode GE side (lower side in the figure) of the interlayer insulating layer II. Part.

  As shown in FIG. 15, positive charges biased downward in the drawing of the interlayer insulating layer II due to the above-described polarization act on the drift region DR. As a result, the horizontal electric field applied between the source region and the drain region becomes non-uniform. It is considered that the breakdown voltage has deteriorated due to the above. In addition, it is considered that the breakdown voltage of the configuration of FIG. 11 has deteriorated for the same reason.

  On the other hand, in the configuration shown in FIGS. 10 and 1, the field plate FP has a gate potential. As a result, the above-mentioned polarization does not occur, so it is considered that the breakdown voltage hardly deteriorated.

  Next, the amount of variation in threshold voltage was examined for the configuration of the present embodiment shown in FIG. 1 in which the above breakdown voltage degradation hardly occurred and the configuration of the comparative example shown in FIG.

  The amount of variation in the threshold voltage for the above two configurations (the configurations shown in FIGS. 1 and 10) was measured by the following method.

(B1) The drain current Ids and the threshold voltage Vth were measured.
(B2) A stress voltage of Vg (gate potential) = Vd (drain potential) was applied for a certain period of time.

(B3) The drain current Ids and the threshold voltage Vth were measured.
Further, the above measurement is performed by changing the width ps of the dummy conductive layer DC shown in FIG. 1, and the width AGFP from the drain side end of the field plate FP in FIG. 10 to just above the end of the gate electrode GE is changed. And measured.

  FIG. 16 shows the result of the fluctuation amount of the threshold voltage measured by the above method. From the results of FIG. 16, it was found that the variation in threshold voltage (ΔVth) could not be suppressed much, although the increase in current capability could be suppressed by changing the field plate width AGFP in the configuration of FIG. 10. On the other hand, in the configuration of FIG. 1, it was found that by increasing the width ps of the dummy conductive layer DC, it is possible to suppress an increase in current capability and to suppress a threshold voltage fluctuation amount (ΔVth).

  This is considered because the electric field of the field plate FP can be shielded by the dummy conductive layer DC by providing the dummy conductive layer DC between the field plate FP and the drift region DR.

  As described above, according to the configuration of the present embodiment shown in FIG. 1, it is possible to suppress breakdown voltage deterioration and threshold voltage fluctuation due to gate pulse stress.

Next, functions and effects of the semiconductor device of this embodiment will be described.
In this embodiment mode, a thick insulating layer FO such as an element isolation insulating layer is used for the gate insulating layer as shown in FIG. 1, so that a high voltage can be input. Further, by providing the field plate FP, the electric field concentration in the drift region DR can be reduced. Further, since the field plate FP is at the gate potential, the current capability can be improved.

  Further, when the current capability is improved, hot carriers are usually easily generated, so that the number of trapped carriers in the insulating layer FO increases, and the characteristic variation such as threshold voltage increases. However, in the present embodiment, the electric field from the field plate FP can be shielded by the dummy conductive layer DC having the source potential disposed between the field plate FP and the drift region DR. Thereby, even if the current capability is improved as shown in FIG. 16, the fluctuation of the threshold voltage can be reduced as compared with the configuration of FIG.

  Further, in this embodiment, since the electric field from the field plate FP can be shielded by the dummy conductive layer DC having the source potential, the amount of breakdown voltage degradation due to the gate pulse stress can be reduced as shown in FIG.

  In the present embodiment, the current capability can also be adjusted by changing the width ps and arrangement position of the dummy conductive layer DC.

  In the configuration of the present embodiment shown in FIG. 1, when the dummy conductive layer DC is located on the drain side with respect to the drain side end FPE of the field plate FP, the breakdown voltage is lowered. However, in this embodiment, since the dummy conductive layer DC is located on the source side with respect to the drain side end portion FPE of the field plate FP, such a decrease in breakdown voltage does not occur.

(Embodiment 2)
Referring to FIG. 17, the configuration of the semiconductor device of the present embodiment is different from that of the first embodiment shown in FIG. 1 in that the dummy conductive layer DC includes two conductors DC1 and DC2. It differs in that it has a conductor. Both the conductor DC1 and the conductor DC2 are electrically connected to the source region. An insulating layer CI is formed on the upper surface of each of the conductor DC1 and the conductor DC2, and a sidewall insulating layer SW is formed on the side surface.

  Since the configuration other than this is almost the same as the configuration of the first embodiment, the same elements are denoted by the same reference numerals and the description thereof is omitted.

  In the present embodiment, since the dummy conductive layer DC includes the conductor DC1 and the conductor DC2, the current capability can be adjusted more finely than in the first embodiment.

(Embodiment 3)
Referring to FIG. 17, the configuration of the semiconductor device of the present embodiment is different from that of the first embodiment shown in FIG. 1 in that the dummy conductive layer DC includes two conductors DC1 and DC2. It differs in that it has a conductor. A conductor DC1 on the side close to the gate electrode GE is electrically connected to the source region. The conductor DC2 far from the gate electrode GE is in a floating potential state. That is, the conductor DC2 arranged on the drain region side of the conductor DC1 has a floating potential. An insulating layer CI is formed on the upper surface of each of the conductor DC1 and the conductor DC2, and a sidewall insulating layer SW is formed on the side surface.

  Since the configuration other than this is almost the same as the configuration of the first embodiment, the same elements are denoted by the same reference numerals and the description thereof is omitted.

  In the present embodiment, since the dummy conductive layer DC includes the conductor DC1 and the conductor DC2, the current capability can be adjusted more finely than in the first embodiment.

  In addition, the conductor DC2 having a floating potential can suppress deterioration due to formation of trap sites due to film quality of the interlayer insulating layer II or moisture entering from the upper layer.

(Embodiment 4)
Referring to FIG. 17, the configuration of the semiconductor device of the present embodiment is different from that of the first embodiment shown in FIG. 1 in that the dummy conductive layer DC includes two conductors DC1 and DC2. It differs in that it has a conductor. The conductor DC1 on the side close to the gate electrode GE is in a floating potential state. The conductor DC2 on the side far from the gate electrode GE is electrically connected to the source region. That is, the conductor DC1 disposed on the gate electrode GE side of the conductor DC2 has a floating potential. An insulating layer CI is formed on the upper surface of each of the conductor DC1 and the conductor DC2, and a sidewall insulating layer SW is formed on the side surface.

  Since the configuration other than this is almost the same as the configuration of the first embodiment, the same elements are denoted by the same reference numerals and the description thereof is omitted.

  In the present embodiment, since the dummy conductive layer DC includes the conductor DC1 and the conductor DC2, the current capability can be adjusted more finely than in the first embodiment.

  Further, the conductor DC1 having a floating potential can suppress deterioration due to formation of trap sites due to film quality of the interlayer insulating layer II or moisture entering from the upper layer.

(Embodiment 5)
In the second to fourth embodiments, the case where the dummy conductive layer DC includes the two conductors DC1 and DC2 has been described. However, the dummy conductive layer DC may include three or more conductors. In this case, if at least one of the three or more conductors has a source potential, the other conductors may have a source potential or a floating potential.

  Since dummy conductive layer DC has three or more conductors, the current capacity can be adjusted more finely than in the first embodiment.

  In addition, since the dummy conductive layer DC has a floating potential conductor, deterioration due to formation of trap sites due to film quality of the interlayer insulating layer II or moisture entering from the upper layer can be suppressed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor device including a lateral insulated gate field effect transistor.

BI BOX layer, BN bottom n-type region, CH1 to CH5 contact hole, CI, FO insulating layer, DC dummy conductive layer, DC1, DC2 conductor, DI drain wiring, DR drift region, FP field plate, GE gate electrode, II Interlayer insulating layer, IN oxide film, NR n ⁺ region, NW n-type well region, PL plug conductive layer, PR1, PR2 p ⁺ region, PS conductive layer, PW1, PW2 p-type well region, SC1 to SC3 silicide layer, SI Source wiring, SL semiconductor layer, SS support substrate, SU semiconductor substrate, SW side wall insulating layer.

Claims (4)

A semiconductor substrate having a main surface;
An insulating layer selectively formed on the main surface of the semiconductor substrate;
A lateral insulated gate field effect transistor formed on the semiconductor substrate;
The insulated gate field effect transistor is
A source region and a drain region formed on the main surface of the semiconductor substrate on each of both sides of the insulating layer;
A drift region connected to the drain region;
A gate electrode formed on the region sandwiched between the source region and the drift region with the insulating layer interposed therebetween, further extending on the gate electrode and the drift region, and electrically connected to the gate electrode A field plate connected to the
A semiconductor device comprising: a dummy conductive layer including a first conductor formed on the insulating layer between the field plate and the drift region and electrically connected to the source region.   The semiconductor device according to claim 1, wherein the dummy conductive layer further includes a second conductor electrically connected to the source region.   The semiconductor device according to claim 1, wherein the dummy conductive layer further includes a second conductor having a floating potential arranged on the gate electrode side of the first conductor.   The semiconductor device according to claim 1, wherein the dummy conductive layer further includes a second conductor having a floating potential disposed on the drain region side of the first conductor.

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