JP6317727B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  In trench-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the ratio of channel resistance to the on-resistance is high, so the channel density is increased by miniaturization and other measures to reduce the on-resistance. I came. Once a low on-resistance is achieved to some extent by increasing the channel density, the drift layer is now required to have a low resistance.

  As a MOSFET structure for realizing a low resistance of the drift layer, there are a field plate structure (hereinafter also referred to as FP structure), a super junction structure (hereinafter also referred to as SJ structure), and the like. In any structure, since the depletion layer formed in the drift layer can be extended more widely, the impurity concentration of the drift layer can be increased, and a high breakdown voltage can be obtained. When this type of MOSFET is an n-channel element, generally, the drift layer contains an n-type impurity, and the base layer where the channel is formed contains a p-type impurity.

  However, when the concentration of the n-type impurity contained in the drift layer exceeds a certain concentration, the mobility of the drift layer may decrease rapidly. In this type of MOSFET, a p-type impurity larger than the amount of n-type impurities is implanted into the surface of the drift layer, and a base layer having a conductivity type different from that of the drift layer is formed on the surface of the drift layer. For this reason, the base layer originally contains substantially the same amount of n-type impurities as the n-type impurities contained in the drift layer. Therefore, in the example of the n-channel MOSFET, the n-type impurity concentration contained in the base layer may affect the resistance of the channel formed in the base layer.

JP 2009-253139 A

  The problem to be solved by the present invention is to provide a semiconductor device with lower on-resistance.

The semiconductor device of the embodiment is a semiconductor device having a trench gate structure, which is of a first conductivity type, and the impurity concentration distribution of the first conductivity type includes a drift layer having a region having a substantially constant first concentration ; A base layer of a second conductivity type provided immediately above the drift layer and in contact with the drift layer, including the impurity of the first conductivity type, and the impurity concentration distribution of the first conductivity type is substantially constant. A base layer having a region of the second concentration, a source layer of a first conductivity type selectively provided on a surface of the base layer, a drain electrode electrically connected to the drift layer, and the source A source electrode electrically connected to the layer; a gate electrode in contact with the base layer via an insulating film; and provided between the gate electrode and the drain electrode, and the drift layer is interposed between the gate electrode and the drain electrode. Field to touch With a rate electrode, said field plate electrode is electrically connected to the source electrode, the second concentration of said first conductivity type impurity contained in the base layer, the contained in the drift layer The first conductivity type impurity concentration is lower than the first concentration of the first conductivity type impurity , and the first conductivity type impurity concentration continuously changes from the second concentration to the first concentration between the base layer and the drift layer. and the impurity concentration of the first conductivity type included in the drift layer is ^{1 × 10 16 (atoms / cm} 3) or more.
In addition, the semiconductor device of the embodiment is a semiconductor device having a trench gate type structure, which is of a first conductivity type, and the impurity concentration distribution of the first conductivity type has a drift having a region having a substantially constant first concentration. And a second conductivity type base layer provided in contact with the drift layer immediately above the drift layer, including the first conductivity type impurity, and the impurity concentration distribution of the first conductivity type is: A base layer having a region having a substantially constant second concentration; a source layer of a first conductivity type selectively provided on a surface of the base layer; the base layer reaching the drift layer from the source layer; A gate electrode that is in contact with an insulating film through the insulating layer, a pillar-shaped second conductivity type semiconductor layer that is connected to the base layer and extends from the surface to the inside of the drift layer, and is electrically connected to the drift layer Drain electrode , And a source electrode electrically connected to said source layer, said second concentration of said first conductivity type impurity contained in the base layer of the first conductivity type contained in said drift layer The impurity concentration of the first conductivity type is lower than the first concentration of impurities, and continuously changes from the second concentration to the first concentration between the base layer and the drift layer, and the drift layer The impurity concentration of the first conductivity type contained in is 1 × 10 ¹⁶ (atoms / cm ³ ) or more.

2A and 2B are schematic views of the semiconductor device according to the first embodiment, in which FIG. 1A is a schematic plan view, and FIG. 2B is a schematic cross-sectional view at an XY position of FIG. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of a semiconductor device. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of a semiconductor device. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of a semiconductor device. 4A and 4B are schematic diagrams of a semiconductor device according to a reference example, in which FIG. 5A is a schematic cross-sectional view and an impurity concentration profile, and FIG. It is a graph which shows the change of. It is a graph which shows the change of the mobility in a channel when changing the n-type impurity concentration contained in the base layer in 1st Embodiment. It is a figure for demonstrating the relationship between the impurity concentration contained in a silicon crystal layer, and a mobility. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a second embodiment and an impurity concentration profile.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

(First embodiment)
1A and 1B are schematic views of the semiconductor device according to the first embodiment. FIG. 1A is a schematic plan view, and FIG. 1B is a schematic cross-sectional view at an XY position of FIG. is there.

  The impurity concentration profile shown on the right side of the cross-sectional schematic diagram of the semiconductor device is the impurity concentration of the n-type impurity in the base layer, the drift layer, and the drain layer along the line AB in the schematic cross-sectional diagram.

  The semiconductor device 1 according to the first embodiment is a MOSFET having a trench gate structure. As an example of the MOSFET, an n-channel MOSFET is illustrated.

The semiconductor device 1 has an n ^{+ -type} drain layer 10, and an n-type drift layer 11 is provided on the drain layer 10. A p-type base layer 12 is provided on the drift layer 11. An n ^{+ -type} source layer 13 is selectively provided on the surface of the base layer 12. A p-type contact layer 15 is selectively provided on the surface of the base layer 12 so as to be adjacent to the source layer 13. The p-type impurity concentration contained in the contact layer 15 is higher than the value obtained by subtracting the n-type impurity concentration from the p-type impurity concentration contained in the base layer 12. For example, the contact layer 15 functions as a hole extraction layer for maintaining a high avalanche resistance.

  In the semiconductor device 1, a gate electrode 22 is provided through a gate insulating film 21 in a trench 20 that penetrates the source layer 13 and the base layer 12 and reaches the drift layer 11. In the trench 20, a field plate electrode (buried electrode) 26 is further provided via a field plate insulating film 25. The field plate electrode 26 is located below the gate electrode 22.

  The trench 20 and the source layer 13 are arranged in a stripe shape when viewed from the direction perpendicular to the main surface of the drain layer 10. The pitch of the trenches 20 in a direction substantially perpendicular to the direction in which the trenches 20 extend in a stripe shape (a direction in which the plurality of trenches 20 are periodically arranged) is, for example, 1.5 μm or less.

  In the semiconductor device 1, the drain electrode 50 is connected to the drain layer 10. As a result, the drain electrode 50 is electrically connected to the drift layer 11. A source electrode 51 is electrically connected to the source layer 13 and the contact layer 15. The field plate electrode 26 is electrically connected to the source electrode 51.

The n-type impurity concentration contained in the base layer 12 is lower than the n-type impurity concentration contained in the drift layer 11. The n-type impurity concentration contained in the drift layer 11 is 1 × 10 ¹⁶ (atoms / cm ³ ) or more. In the embodiment, the n ^{+ type} , the n type may be the first conductivity type, and the p type may be the second conductivity type. Examples of the first conductivity type impurity include arsenic (As) and phosphorus (P). In the embodiment, arsenic (As) having a lower diffusion coefficient in a high temperature state is preferentially used. Examples of the second conductivity type impurity include boron (B).

The main component of the drain layer 10, the drift layer 11, the base layer 12, and the source layer 13 is, for example, silicon (Si). The main component of the gate electrode 22 and the field plate electrode 26 is, for example, polysilicon (poly-Si). The material of the gate insulating film 21 and the field plate insulating film 25 is, for example, silicon oxide (SiO ₂ ).

Since the semiconductor device 1 is provided with the field plate electrode 26 under the gate electrode 22, the gate-drain capacitance is reduced. In addition, since the electric field is easily concentrated on the bottom of the trench 20, the electric field concentration at the interface between the base layer 12 and the drift layer 11 is reduced. Furthermore, the provision of the field plate electrode 26 makes it easy for the depletion layer formed in the drift layer 11 to spread. Thereby, the semiconductor device 1 has a high breakdown voltage. In the semiconductor device 1, the entire drift layer 11 can be depleted even if the n-type impurity concentration contained in the drift layer 11 is 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more.

  Thus, in the semiconductor device 1, the field plate electrode 26 is provided, and the n-type impurity concentration contained in the drift layer 11 is set high. Thereby, the semiconductor device 1 maintains a high breakdown voltage. Furthermore, the semiconductor device 1 has a low resistance drift layer 11.

A method for manufacturing the semiconductor device 1 will be described.
2 to 4 are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device.

First, as shown in FIG. 2A, a semiconductor stacked body 19A including a drain layer 10, a drift layer 11, and a low concentration drift layer 11a is prepared. The drift layer 11 is provided on the drain layer 10, and the low concentration drift layer 11 a is provided on the drift layer 11. The n-type impurity concentration contained in the drift layer 11 a is lower than the n-type impurity concentration contained in the drift layer 11. The n-type impurity concentration contained in the drift layer 11 is 1 × 10 ¹⁶ (atoms / cm ³ ) or more.

  In the semiconductor stacked body 19A, the drain layer 10, the drift layer 11, and the drift layer 11a are formed by epitaxial growth.

  Next, as shown in FIG. 2B, p-type impurities are ion-implanted into the drift layer 11a. As a result, a semiconductor stacked body 19B including the drain layer 10, the drift layer 11 provided on the drain layer 10, and the base layer 12 provided on the drift layer 11 is prepared.

  In the semiconductor stacked body 19B, since the n-type impurity concentration contained in the drift layer 11a is lower than the n-type impurity concentration contained in the drift layer 11, the n-type impurity concentration contained in the base layer 12 is 11 is lower than the n-type impurity concentration contained in 11.

  Next, as shown in FIG. 2C, a mask member 80 is selectively formed on the surface of the base layer 12, and an etching process is performed on the semiconductor stacked body 19 </ b> B opened from the mask member 80. Etching is RIE (Reactive Ion Etching). Thereby, a trench 20 that penetrates the base layer 12 and reaches the drift layer 11 is formed.

  Next, as shown in FIG. 3A, a field plate insulating film 25 is formed in the trench 20 by thermal oxidation. Subsequently, a field plate electrode 26 is formed in the trench 20 through a field plate insulating film 25 by CVD (Chemical Vapor Deposition). The field plate electrode 26 is embedded in the trench 20 and also formed on the base layer 12.

  Next, as shown in FIG. 3B, the field plate electrode 26 is etched back. Thereby, the field plate electrode 26 is adjusted to a predetermined height. Further, the upper field plate insulating film 25 is removed from the field plate electrode 26 by etch back.

  Next, as shown in FIG. 4A, a gate insulating film 21 is formed on the field plate electrode 26 in the trench 20 by thermal oxidation. Subsequently, in the trench 20, the gate electrode 22 is formed by CVD through the gate insulating film 21. The gate electrode 22 is etched back as necessary and adjusted to a predetermined height. Thereafter, the excess gate insulating film 21 formed on the base layer 12 is removed.

  Next, as shown in FIG. 4B, a mask member 81 that covers the base layer 12 and the gate electrode 22 is formed. A part of the base layer 12 adjacent to the trench 20 is opened from the mask member 81. Then, n-type impurities are ion-implanted into the surface of the base layer 12 opened from the mask member 81. Thereby, the source layer 13 is selectively formed on the surface of the base layer 12 so as to be in contact with the gate insulating film 21. If necessary, the contact layer 15 may be selectively formed on the surface of the base layer 12 by ion implantation. Subsequently, the mask member 81 on the gate electrode 22 is left as an interlayer insulating film, and the other excess mask member 81 is removed.

  Thereafter, as shown in FIG. 1B, a source electrode 51 electrically connected to the source layer 13 and the field plate electrode 26 and a drain electrode 50 electrically connected to the drift layer 11 are formed. To do. The semiconductor device 1 is formed by such a manufacturing process.

  The effects of the semiconductor device 1 will be described with reference to a semiconductor device according to a reference example.

In the semiconductor device 1, for example, when the pitch of the trenches 20 is 1.5 μm, the n-type impurity concentration contained in the drift layer 11 is 1.0 × 10 ¹⁶ (atoms / cm ³ ) and has a breakdown voltage of 35 V or more. . When the pitch of the trenches 20 is narrower than 1.5 μm, the breakdown voltage is maintained even if the n-type impurity concentration contained in the drift layer 11 is further increased.

However, when the concentration of the n-type impurity contained in the drift layer 11 is 1.0 × 10 ¹⁶ (atoms / cm ³ ) or higher, the withstand voltage is maintained, but the mobility in the drift layer 11 starts to decrease. One of the factors may be that when the impurity concentration of the drift layer 11 becomes excessive, carriers are not easily scattered by the impurities.

  5A and 5B are schematic diagrams of a semiconductor device according to a reference example, where FIG. 5A is a schematic cross-sectional view and an impurity concentration profile, and FIG. 5B is a graph when n-type impurity concentration included in the base layer is changed. It is a graph which shows the change of the mobility in a channel.

  The impurity concentration profile shown on the right side of the cross-sectional schematic diagram of the semiconductor device is the impurity concentration of the n-type impurity in the base layer 12, the drift layer 11, and the drain layer 10 along the line AB in the schematic cross-sectional diagram. .

  The semiconductor device 100 according to the reference example is a MOSFET having a trench gate structure. The semiconductor device 100 is an n-channel MOSFET and includes a field plate electrode 26. In the semiconductor device 100, the base layer 120 is formed by ion implantation on the surface of the drift layer 11 having a uniform impurity concentration. The drift layer 11 is formed by epitaxial growth. For this reason, as shown in FIG. 5A, the n-type impurity concentration contained in the base layer 120 is substantially the same as the n-type impurity concentration contained in the drift layer 11.

  In an n-channel MOSFET, the on-resistance of the drift layer 11 is generally inversely proportional to mobility and carrier density. In addition, in a high-concentration n-type semiconductor layer such as the drain layer 10, the carrier density and the n-type impurity amount are considered to be the same amount. Therefore, when the impurity concentration is increased, the on-resistance tends to decrease.

  However, the carriers in the channel formed in the base layer 12 are minority carriers in the inversion layer. The amount of minority carriers is determined by the thickness of the gate insulating film 21, the voltage applied to the gate electrode 22, and the like. The amount of minority carriers does not depend on the n-type impurity concentration contained in the base layer 12. Therefore, in the channel formed in the base layer 12, even if the n-type impurity concentration increases, the carrier density does not change and only the mobility may decrease. That is, if the n-type impurity concentration contained in the base layer 12 is too high, not only the drift layer 11 but also the channel resistance may increase.

  FIG. 5B shows a change in mobility in the channel when the n-type impurity concentration contained in the base layer is changed. FIG. 5B is obtained by simulation.

The horizontal axis in FIG. 5B represents the horizontal distance (μm) in the base layer 120. The lateral distance (μm) is the distance from the boundary A ′ between the trench 20 and the drift layer 11 to the position B. The vertical axis | shaft of FIG.5 (b) is a mobility (cm < ² > / V * s).

Line A is an example when the n-type impurity concentration is 1.0 × 10 ¹⁶ (atoms / cm ³ ). Line B is an example when the n-type impurity concentration is 8.0 × 10 ¹⁶ (atoms / cm ³ ). Line C is an example when the n-type impurity concentration is 2.0 × 10 ¹⁷ (atoms / cm ³ ). The impurity concentration contained in the base layer 120 in each line is set so that the threshold voltage has the same value.

  FIG. 5B shows that the mobility of a channel formed in the base layer 120 decreases as the n-type impurity concentration increases. That is, when the n-type impurity concentration contained in the base layer 120 becomes excessive, the channel mobility decreases.

  On the other hand, FIG. 6 is a graph showing a change in mobility in the channel when the n-type impurity concentration contained in the base layer in the first embodiment is changed. FIG. 6 is obtained by simulation.

The horizontal axis in FIG. 6 is the distance (μm) in the horizontal direction of the base layer 12. The lateral distance (μm) is a distance from the boundary A ′ between the trench 20 and the drift layer 11 in the base layer 12 to the position B. The vertical axis | shaft of FIG.6 (b) is a mobility (cm < ² > / V * s).

6, the n-type impurity concentration contained in the drift layer 11 is 2.0 × 10 ¹⁷ (atoms / cm ³ ), and the n-type impurity concentration contained in the base layer 12 is 1.0 × 10. ^This is an example at ¹⁶ (atoms / cm ³ ). Line E is an example in which both the n-type impurity concentrations contained in drift layer 11 and base layer 12 are 1.0 × 10 ¹⁶ (atoms / cm ³ ). Line F is an example in which the n-type impurity concentration in the drift layer 11 and the base layer 12 is both 2.0 × 10 ¹⁷ (atoms / cm ³ ).

  It can be seen that the line D and the line E are substantially overlapped. This is because the n-type impurity concentration contained in the base layer 12 is the same. However, if the n-type impurity concentration contained in the base layer 12 is increased as shown by the line F, the mobility of the channel is lowered.

  On the other hand, even if the n-type impurity concentration contained in the base layer 12 is the same, the resistance of the drift layer 11 decreases in the line D where the n-type impurity concentration contained in the drift layer 11 is increased compared to the line E. In other words, even if the n-type impurity concentration contained in the drift layer 11 is increased as in the line D, the n-type impurity concentration contained in the drift layer 11 is changed to the n-type impurity concentration contained in the base layer 12. If it is lower than that, the mobility of the line E having the low impurity concentration from the drift layer 11 to the base layer 12 is the same.

In the embodiment, when the n-type impurity concentration contained in the drift layer 11 is 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more, the drift layer 11 contains more than the n-type impurity concentration contained in the drift layer 11. The n-type impurity concentration is set low. Thereby, the mobility of the channel is not lowered, and an increase in channel resistance can be suppressed.

When the n-type impurity concentration contained in the drift layer 11 is smaller than 1.0 × 10 ¹⁶ (atoms / cm ³ ), the on-resistance of the drift layer 11 may be lowered. Therefore, the n-type impurity concentration contained in the drift layer 11 is desirably 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more.

  FIG. 7 is a diagram for explaining the relationship between the concentration of impurities contained in the silicon crystal layer and the mobility. FIG. 7 shows an example of the relationship between the concentration of impurities contained in the silicon crystal layer and the mobility (EFLabuda and JTClemens, “Integrated Ciruit Technology”, REKirk and DFOthmer, Eds., Encyclopedia). of Chemical Technology, Wiley, New York, 1980.).

The horizontal axis in FIG. 7 is the impurity concentration (atoms / cm ³ ), and the right vertical axis is the mobility (cm ² / V · s). μ _n is the relationship between n-type impurity concentration and mobility, and μ _p is the relationship between p-type impurity concentration and mobility. From FIG. 7, the mobility is substantially constant in the range where the impurity concentration is smaller than 1.0 × 10 ¹⁶ (atoms / cm ³ ). When the impurity concentration is in the range of 1.0 × 10 ¹⁶ (atoms / cm ³ ) to 1.0 × 10 ¹⁹ (atoms / cm ³ ), the mobility starts to gradually decrease. When the impurity concentration is higher than 1.0 × 10 ¹⁹ (atoms / cm ³ ), the decrease in mobility is saturated.

Therefore, in the embodiment, the concentration of the n-type impurity contained in the drift layer 11 is set to a range of 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more and 1.0 × 10 ¹⁹ (atoms / cm ³ ) or less. May be. It is contained in the base layer 12 rather than the n-type impurity concentration contained in the drift layer 11 in the range of 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more and 1.0 × 10 ¹⁹ (atoms / cm ³ ) or less. The n-type impurity concentration may be set low.

(Second Embodiment)
FIG. 8 is a schematic cross-sectional view of the semiconductor device according to the second embodiment and an impurity concentration profile.

  The impurity concentration profile shown on the right side of the cross-sectional schematic diagram of the semiconductor device is the impurity concentration of the n-type impurity in the base layer, the drift layer, and the drain layer along the line AB in the schematic cross-sectional diagram.

  The semiconductor device 2 according to the second embodiment is a MOSFET having a trench gate structure. As an example of the MOSFET, an n-channel MOSFET is illustrated. The semiconductor device 2 has a super junction structure.

  The semiconductor device 2 has a drain layer 10, and a drift layer 11 is provided on the drain layer 10. A base layer 12 is provided on the drift layer 11. A source layer 13 is selectively provided on the surface of the base layer 12.

The n-type impurity concentration contained in the base layer 12 is lower than the n-type impurity concentration contained in the drift layer 11. The n-type impurity concentration contained in the drift layer 11 is 1 × 10 ¹⁶ (atoms / cm ³ ) or more.

  In the semiconductor device 2, a gate electrode 22 is provided through a gate insulating film 21 in a trench 20 that penetrates the source layer 13 and the base layer 12 and reaches the drift layer 11.

  In the semiconductor device 2, a p-type semiconductor layer 12 p is provided from the surface to the inside of the drift layer 11. The upper end of the semiconductor layer 12p is connected to the base layer 12. The shape of the semiconductor layer 12p is a pillar shape. Since the semiconductor layer 12p has a pillar shape, the drift layer 11 adjacent to the semiconductor layer 12p has a pillar shape. The semiconductor device 2 includes a super junction structure in which pillar-shaped drift layers 11 and pillar-shaped semiconductor layers 12 p are alternately and periodically arranged on the drain layer 10.

  In the semiconductor device 2, a p-type contact layer 15 is selectively provided on the surface of the base layer 12 so as to be adjacent to the source layer 13. The contact layer 15 is located above the semiconductor layer 12p. The p-type impurity concentration contained in the contact layer 15 is higher than the value obtained by subtracting the n-type impurity concentration contained in the base layer 12 from the p-type impurity concentration contained in the base layer 12.

  A drain electrode 50 is connected to the drain layer 10. A drain electrode 50 is electrically connected to the drift layer 11. A source electrode 51 is electrically connected to the source layer 13 and the contact layer 15.

  In the semiconductor device 2, since the super junction structure is provided, the depletion layer is extended in a direction substantially parallel to the main surface of the drain layer 10 from the interface between the p-type semiconductor layer 12 p and the n-type drift layer 11. Can do. Thereby, the depletion layer formed in the drift layer 11 becomes easy to spread. As a result, the semiconductor device 2 has a high breakdown voltage.

In the semiconductor device 2, since the depletion layer formed in the drift layer 11 easily spreads, the n-type impurity concentration contained in the drift layer 11 can be set high. For example, in the semiconductor device 2, even if the n-type impurity concentration contained in the drift layer 11 is 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more, the entire drift layer 11 can be depleted. Since the drift layer 11 has a high concentration, the resistance of the drift layer 11 decreases.

As described above, the semiconductor device 2 is included in the drift layer 11 when the n-type impurity concentration included in the drift layer 11 is 1.0 × 10 ¹⁶ (atoms / cm ³ ) or more, as in the semiconductor device 1. The n-type impurity concentration contained in the base layer 12 is set lower than the n-type impurity concentration. Thereby, the mobility of the channel is not lowered, and an increase in channel resistance can be suppressed.

  In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

  In the embodiment, the super junction structure forming process can be performed using any process such as a process of repeating ion implantation and embedded crystal growth and a process of changing an acceleration voltage.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 2, 100 Semiconductor device, 10 Drain layer, 11, 11a Drift layer, 12, 120 Base layer, 12p Semiconductor layer, 13 Source layer, 15 Contact layer, 19A, 19B Semiconductor stacked body, 20 Trench, 21 Gate insulating film , 22 gate electrode, 25 field plate insulating film, 26 field plate electrode, 50 drain electrode, 51 source electrode, 80, 81 mask member

Claims (4)

A trench gate type semiconductor device comprising:
A drift layer having a region of a first conductivity type, wherein the impurity concentration distribution of the first conductivity type has a substantially constant first concentration ;
A base layer of a second conductivity type provided immediately above the drift layer and in contact with the drift layer, including the first conductivity type impurity, and the impurity concentration distribution of the first conductivity type is substantially constant. A base layer having a region of a second concentration ;
A first conductivity type source layer selectively provided on the surface of the base layer;
A drain electrode electrically connected to the drift layer;
A source electrode electrically connected to the source layer;
A gate electrode in contact with the base layer via an insulating film;
A field plate electrode provided between the gate electrode and the drain electrode and in contact with the drift layer via the insulating film;
With
The field plate electrode is electrically connected to the source electrode;
The second concentration of the first conductivity type impurity contained in the base layer is lower than the first concentration of the first conductivity type impurity contained in the drift layer;
The impurity concentration of the first conductivity type continuously changes from the second concentration to the first concentration between the base layer and the drift layer,
An impurity concentration of the first conductivity type included in the drift layer is 1 × 10 ¹⁶ (atoms / cm ³ ) or more. A trench gate type semiconductor device comprising:
A drift layer having a region of a first conductivity type, wherein the impurity concentration distribution of the first conductivity type has a substantially constant first concentration ;
A base layer of a second conductivity type provided immediately above the drift layer and in contact with the drift layer, including the first conductivity type impurity, and the impurity concentration distribution of the first conductivity type is substantially constant. A base layer having a region of a second concentration ;
A first conductivity type source layer selectively provided on the surface of the base layer;
A gate electrode that reaches the drift layer from the source layer and is in contact with the base layer through an insulating film;
A pillar-shaped second conductivity type semiconductor layer connected to the base layer and provided from the surface to the inside of the drift layer;
A drain electrode electrically connected to the drift layer;
A source electrode electrically connected to the source layer;
With
The second concentration of the first conductivity type impurity contained in the base layer is lower than the first concentration of the first conductivity type impurity contained in the drift layer;
The impurity concentration of the first conductivity type continuously changes from the second concentration to the first concentration between the base layer and the drift layer,
An impurity concentration of the first conductivity type included in the drift layer is 1 × 10 ¹⁶ (atoms / cm ³ ) or more. A contact layer of a second conductivity type is further selectively provided on the surface of the base layer so as to be adjacent to the source layer,
The impurity concentration of the second conductivity type included in the contact layer is less than the value obtained by subtracting the impurity concentration of the first conductivity type included in the base layer from the impurity concentration of the second conductivity type included in the base layer. high,
The semiconductor device according to claim 1, wherein the contact layer is connected to the source electrode.   3. The impurity concentration distribution of the first conductivity type in the direction from the drain electrode to the source electrode is constant in the region where the impurity concentration distribution of the first conductivity type in the drift layer is constant. The semiconductor device described.

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