JP2570742B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2570742B2 JP2570742B2 JP62130929A JP13092987A JP2570742B2 JP 2570742 B2 JP2570742 B2 JP 2570742B2 JP 62130929 A JP62130929 A JP 62130929A JP 13092987 A JP13092987 A JP 13092987A JP 2570742 B2 JP2570742 B2 JP 2570742B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- gate
- drain
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置、特にデュアルゲートの電界効
果トランジスタに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly to a dual-gate field-effect transistor.
本発明は、デュアルゲートのパワーMOSトランジスタ
であり、半導体基板のトレンチに絶縁膜を介して積層し
て形成した第１のゲート電極は、ドレイン領域に対応し
て形成し、また第２のゲート電極は、チャネル領域に対
応して形成することにより、高耐圧化と高出力化を図る
ことができるようにしたものである。The present invention relates to a dual-gate power MOS transistor, wherein a first gate electrode formed by laminating in a trench of a semiconductor substrate via an insulating film is formed corresponding to a drain region, and a second gate electrode is formed. Are formed so as to correspond to the channel region, so that high breakdown voltage and high output can be achieved.
〔従来の技術〕 従来安定で高利得の高周波増幅を行なうことができる
MOS FETとして、ソース領域とドレイン領域の間に縦続
的に２つのゲートを形成した、デュアルゲートMOS FET
が提案されている。[Prior art] Conventionally stable, high-gain high-frequency amplification can be performed
Dual gate MOS FET with two gates cascaded between source and drain regions as MOS FET
Has been proposed.
近年、従来のデュアルゲートMOS FETを更に高耐圧、
且つ高出力とすることが要請されている。本発明は斯る
点に鑑みて、このような要請を実現させることができる
新規な構造を有するデュアルゲートMOS FETを提供する
ものである。In recent years, conventional dual-gate MOS FETs have higher breakdown voltage,
In addition, high output is required. In view of the above, the present invention provides a dual gate MOS FET having a novel structure capable of realizing such a demand.
本発明に係る半導体装置においては、半導体基板
（１）に形成されたトレンチ（８）の側壁にソース領域
（18）、チャネル領域（13）及びドレイン領域（11）を
形成し、チャネル領域（13）はトレンチ（８）の深さ方
向において、ソース領域（18）と接する側を高濃度領域
（５）とし、ドレイン領域（11）は高濃度領域（１）と
低濃度領域（２）を有し、低濃度領域（２）がトレンチ
（８）の側壁に対応してチャネル領域（13）に接してな
り、トレンチ（８）内にはゲート絶縁膜（９）を介して
第１と第２のゲート電極（10），（12）を積層して形成
し、第１のゲート電極（10）はドレイン領域（11）の低
濃度領域（２）に対応して形成し、この第１のゲート電
極（10）でドレイン抵抗を制御し、第２のゲート電極
（12）はチャネル領域（13）に対応して形成し、第２の
ゲート電極（12）でスイッチング動作をすることを特徴
とする。In the semiconductor device according to the present invention, the source region (18), the channel region (13), and the drain region (11) are formed on the side wall of the trench (8) formed in the semiconductor substrate (1), and the channel region (13) is formed. ) Is a high-concentration region (5) on the side in contact with the source region (18) in the depth direction of the trench (8), and the drain region (11) has a high-concentration region (1) and a low-concentration region (2). The low-concentration region (2) is in contact with the channel region (13) corresponding to the side wall of the trench (8), and the first and second regions are formed in the trench (8) via the gate insulating film (9). The first gate electrode (10) is formed corresponding to the low concentration region (2) of the drain region (11), and the first gate electrode (10) is formed by laminating the first gate electrode (10) and (12). The drain resistance is controlled by the electrode (10), and the second gate electrode (12) corresponds to the channel region (13). And a switching operation is performed by the second gate electrode (12).
本発明によれば、トランジスタを縦型に形成するた
め、高密度化が図られ、高出力を得ることができる。ま
た、第２のゲート電極（12）とドレイン領域（11）間の
容量Cdgが、第１のゲート電極（10）があることによ
り、ない場合と比べて小さくすることができるため、高
周波特性が良くなる。According to the present invention, since the transistor is formed in a vertical type, high density can be achieved and high output can be obtained. In addition, since the capacitance Cdg between the second gate electrode (12) and the drain region (11) can be reduced by the presence of the first gate electrode (10) as compared with the case without the first gate electrode (10), high-frequency characteristics are reduced. Get better.
図面を参照して本発明の実施例をその製法例と共に説
明する。An embodiment of the present invention will be described with reference to the drawings together with an example of its manufacturing method.
先ず第１図Ａに示すように、0.01〜0.1ΩcmのN+型（1
00）Si基板（１）に1017〜1018atom/ccのＮ型Si層
（２）と1015〜1017atom/ccのP-型Si層（３）をエピタ
キシャル成長により形成する。First, as shown in FIG. 1A, an N + type (1 to 0.01 Ωcm)
00) An N-type Si layer (2) of 10 17 to 10 18 atom / cc and a P - type Si layer (3) of 10 15 to 10 17 atom / cc are formed on the Si substrate (1) by epitaxial growth.
次に第１図Ｂに示すように、SiO2層（４）又はホトレ
ジスト層等をマスクにしてＰ型不純物を拡散して1016〜
1018atom/ccのＰ領域（５）を形成し、次に連続してＮ
型不純物を拡散して1020atom/cc以上のN+領域（６）を
形成する。このようにP-層（３）とN+領域（６）の間に
Ｐ領域（５）を形成し、またＮ層（２）の下の基板
（１）をN+とすることにより空乏層の拡がりを抑えるこ
とができ、N+領域（６）（ソース領域）とN+基板（１）
（ドレイン領域）とが短い距離で高耐圧（30〜200V）に
することが可能になる。Next, as shown in FIG. 1 B, SiO 2 layer (4) or the photoresist layer or the like as a mask by diffusing P-type impurity 10 16 -
A P region (5) of 10 18 atom / cc is formed, and then N
The N + region (6) of 10 20 atom / cc or more is formed by diffusing the type impurity. Thus P - layer (3) and a depletion layer by forming a P region (5) between the N + region (6), and also N layer substrate (1) under (2) and N + Of the N + region (6) (source region) and the N + substrate (1).
(Drain region) and a high withstand voltage (30 to 200 V) at a short distance.
次に第１図Ｃに示すように、N+領域（６）を分離する
ように、そして高耐圧を得るためにN+基板（１）に達す
るようにSiO2層（７）をマスクしてRIEによりSiの穴掘
りを行ってトレンチ（８）を形成する。Next, as shown in FIG. 1C, the SiO 2 layer (7) is masked so as to separate the N + region (6) and reach the N + substrate (1) in order to obtain a high breakdown voltage. A trench (8) is formed by digging a hole in Si by RIE.
次に第１図Ｅに示すように、トレンチ（８）内壁のダ
メージ層を除去した後、ゲート酸化膜（９）（またはSi
O2/Si3N4/SiO2等でもよい）を形成する。次にこのトレ
ンチ（８）内に多結晶シリコンより成る第１のゲート電
極（10）をドレイン領域（11）に対応するように形成
し、またこの第１のゲート電極（10）の上にゲート酸化
膜（９）を介して同じく多結晶シリコンより成る第２の
ゲート電極（12）をチャネル領域（13）及びソース領域
（18）の一部分に対応するように形成する。この第１の
ゲート電極（10）は、数ボルトの正の電圧を印加し、MO
Sトランジスタのオン抵抗及び第２のゲート電極（12）
とドレイン領域（11）間の容量を小さくする機能を持
つ。即ち、第１のゲート電極（10）をドレイン領域（1
1）に対し正にバイアスすることによってドレイン領域
（11）のＮ層（２）の表面、つまりトレンチ（８）の側
壁側の表面がアキュミレーション状態となり、ドレイン
抵抗が低減し、MOSトランジスタのオン抵抗が下がる。
また、第１のゲート電極（10）があることによって、第
２のゲート電極（12）とドレイン領域（11）とのオーバ
ーラップ容量が小さくなる。そして、第２のゲート電極
（12）により、トランジスタのスイッチング動作をす
る。この後、PSG（リン・シリケート・ガラス）層（1
4）を形成し、窓明けを行った後、A1より成るソース電
極（15）を形成し、また裏面側にはドレイン電極（16）
を形成して、本実施例に係るデュアルゲートのMOSトラ
ンジスタ（17）を作製する。なお、第１図Ｄにおいて両
ソース領域（18）の間にP-層（３）の一部が表面に露出
してソース電極（15）と接続しているが、第１図Ｂに示
す工程でSiO2層（４）の幅とＰ型不純物の拡散を制御す
ることにより、Ｐ領域（５）のみを表面に露出させてソ
ース電極（15）と接続させることができる。Next, as shown in FIG. 1E, after removing the damaged layer on the inner wall of the trench (8), the gate oxide film (9) (or Si) is removed.
O 2 / Si 3 N 4 / SiO 2 or the like). Next, a first gate electrode (10) made of polysilicon is formed in the trench (8) so as to correspond to the drain region (11), and a gate is formed on the first gate electrode (10). A second gate electrode (12) also made of polycrystalline silicon is formed via an oxide film (9) so as to correspond to a part of the channel region (13) and a part of the source region (18). The first gate electrode (10) applies a positive voltage of several volts and
ON resistance of S transistor and second gate electrode (12)
It has the function of reducing the capacitance between the gate electrode and the drain region (11). That is, the first gate electrode (10) is connected to the drain region (1).
By applying a positive bias to 1), the surface of the N layer (2) of the drain region (11), that is, the surface of the trench (8) on the side wall side is in an accumulation state, the drain resistance is reduced, and the MOS transistor ON resistance decreases.
In addition, the presence of the first gate electrode (10) reduces the overlap capacitance between the second gate electrode (12) and the drain region (11). Then, the switching operation of the transistor is performed by the second gate electrode (12). After this, the PSG (phosphorus silicate glass) layer (1
After forming 4) and opening the window, a source electrode (15) made of A1 is formed, and a drain electrode (16) is formed on the back side.
Is formed to manufacture the dual-gate MOS transistor (17) according to the present embodiment. In FIG. 1D, a part of the P − layer (3) is exposed on the surface between the two source regions (18) and connected to the source electrode (15). By controlling the width of the SiO 2 layer (4) and the diffusion of the P-type impurity, only the P region (5) can be exposed to the surface and connected to the source electrode (15).
第２図はこのトランジスタ（17）の平面図を示す。同
図で（19）は、第１のゲート電極（10）のコンタクト
部、（20）は第２のゲート電極（12）のコンタクト部で
ある。トレンチ（８）による縦型構造によって、高密度
化が図れ、且つ四面にチャネル領域（13）が形成される
ので、平面的にみて単位面積当りの出力が大きくでき
る。FIG. 2 shows a plan view of the transistor (17). In the figure, (19) is a contact portion of the first gate electrode (10), and (20) is a contact portion of the second gate electrode (12). The vertical structure with the trenches (8) can increase the density and form the channel regions (13) on all four sides, so that the output per unit area can be increased in plan view.
第３図は本発明に係るトランジスタの等価回路図を示
す。同図で、（31）はドレイン、（32）はソース、（3
3）は第１のゲート、（34）は第２のゲートである。FIG. 3 shows an equivalent circuit diagram of the transistor according to the present invention. In the figure, (31) is the drain, (32) is the source, (3
3) is a first gate, and (34) is a second gate.
本発明によれば、２重拡散法によってN+ソース領域
（18）の周囲にＰ領域（５）を形成し、更にP-層（３）
に続くドレイン領域（11）をＮ層（２）及びN+基板
（１）として形成することにより、ソース領域（18）と
N+ドレイン領域（11）とを短い距離で高耐圧化すること
ができる。また、P-層（３）とＮ層（２）との接合面が
平面であり、曲面ではないので、高耐圧が得られる。ト
ランジスタの高密度化を図ることができるため、単位面
積当たりの出力を大きくすることが可能になる。Ｎドレ
イン領域（11）と第１のゲート電極（10）により、耐圧
を劣化させないでトランジスタのオン抵抗を改善するこ
とができる。gm∝W/L（W:チャネル幅、L:チャネル長）
の関係があるが、本発明によれば４面のチャネル領域が
形成されることになるので、gmが大きくなる。そして、
ｆ∝gm/Cdgの関係があることにより、第２のゲート電極
（12）とドレイン領域（11）間の容量が、第１のゲート
電極（10）の存在により、これがない場合と比べて小さ
くすることができるため、高周波特性が良くなる。According to the present invention, a P region (5) is formed around an N + source region (18) by a double diffusion method, and a P − layer (3) is formed.
The source region (18) is formed by forming the drain region (11) following the above as an N layer (2) and an N + substrate (1).
The breakdown voltage can be increased with the N + drain region (11) over a short distance. In addition, since the joining surface between the P − layer (3) and the N layer (2) is flat and not curved, a high breakdown voltage can be obtained. Since the density of the transistor can be increased, the output per unit area can be increased. With the N drain region (11) and the first gate electrode (10), the on-resistance of the transistor can be improved without deteriorating the breakdown voltage. gm∝W / L (W: channel width, L: channel length)
However, according to the present invention, since four channel regions are formed, gm increases. And
Due to the relationship of f∝gm / Cdg, the capacitance between the second gate electrode (12) and the drain region (11) is smaller than that without the first gate electrode (10) due to the presence of the first gate electrode (10). Therefore, the high frequency characteristics are improved.
第１図は実施例の工程図、第２図は実施例の平面図、第
３図は実施例の回路図である。 （１）はSi基板、（２）はＮ層、（３）はP-層、（５）
はＰ領域、（６）はN+領域、（８）はトレンチ、（９）
はゲート酸化膜、（10）は第１のゲート電極、（11）は
ドレイン領域、（12）は第２のゲート電極、（13）はチ
ャネル領域、（18）はソース領域である。FIG. 1 is a process diagram of the embodiment, FIG. 2 is a plan view of the embodiment, and FIG. 3 is a circuit diagram of the embodiment. (1) Si substrate, (2) N layer, (3) P - layer, (5)
Is a P region, (6) is an N + region, (8) is a trench, (9)
Is a gate oxide film, (10) is a first gate electrode, (11) is a drain region, (12) is a second gate electrode, (13) is a channel region, and (18) is a source region.
Claims (1)
ソース領域、チャネル領域及びドレイン領域が形成さ
れ、 上記チャネル領域は上記トレンチの深さ方向において、
ソース領域と接する側を高濃度領域とし、 上記ドレイン領域は高濃度領域と低濃度領域を有し、該
低濃度領域が上記トレンチの側壁に対応して上記チャネ
ル領域に接してなり、 上記トレンチ内にはゲート絶縁膜を介して第１と第２の
ゲート電極が積層して形成され、 上記第１のゲート電極は、上記ドレイン領域の低濃度領
域に対応して形成され、該第１のゲート電極でドレイン
抵抗を制御し、 上記第２のゲート電極は、上記チャネル領域に対応して
形成され、該第２のゲート電極でスイッチング動作をす
る ことを特徴とする半導体装置。A source region, a channel region, and a drain region are formed on sidewalls of a trench formed in the semiconductor substrate, wherein the channel region is formed in a depth direction of the trench.
The side in contact with the source region is a high-concentration region, the drain region has a high-concentration region and a low-concentration region, and the low-concentration region is in contact with the channel region corresponding to a side wall of the trench. First and second gate electrodes are formed by laminating via a gate insulating film. The first gate electrode is formed corresponding to the low-concentration region of the drain region. A semiconductor device, wherein a drain resistance is controlled by an electrode, and the second gate electrode is formed corresponding to the channel region, and performs a switching operation with the second gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62130929A JP2570742B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62130929A JP2570742B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor device |
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| Publication Number | Publication Date |
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| JPS63296282A JPS63296282A (en) | 1988-12-02 |
| JP2570742B2 true JP2570742B2 (en) | 1997-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62130929A Expired - Fee Related JP2570742B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor device |
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| JP (1) | JP2570742B2 (en) |
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| JPS53142189A (en) * | 1977-05-17 | 1978-12-11 | Matsushita Electronics Corp | Insulating gate type field effect transistor |
| JPS61234066A (en) * | 1985-04-10 | 1986-10-18 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-05-27 JP JP62130929A patent/JP2570742B2/en not_active Expired - Fee Related
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|---|---|
| JPS63296282A (en) | 1988-12-02 |
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