JPH051084Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a semiconductor device, and particularly to a substrate structure of a field effect transistor (FET) for obtaining high output and high frequency.

<Prior Art> FETs having an offset gate structure and a V-groove source grounding structure as shown in FIG. 1 have been proposed as FETs designed to achieve high output and high frequency. In other words, it has a (100) plane orientation with a high impurity concentration.
P type epitaxial layer 2 on p ⁺ silicon substrate 1
An n ^- drift region 3 with a low impurity concentration is formed in succession to the n ⁺ drain region 4 on the surface of the p-type epitaxial layer 2, and the n ^- drift region 3 and
This is an FET in which the p-type substrate region between the n ⁺ source region 5 and the gate region is the p-type substrate region. where n ⁺ source area 5
In order to reduce the source resistance and source inductance, selective etching is performed using the (100) plane orientation to form a V-groove 6 that reaches from the epitaxial 2 surface to the high impurity concentration substrate 1.
A metal film such as Al is deposited on the surface of the source electrode 7.
is formed and connected to ground together with the electrode on the back surface of the substrate 1. The drain electrode 8 is located at n ⁺ in the drift region.
The gate electrode 9 is formed connected to the region 4, and the gate electrode 9 is n ^-
It is formed on a substrate located between drift region 3 and n ⁺ source region 5 with a thin gate oxide film 10 interposed therebetween.

In the FET with the above structure, the source and drain regions are formed in a relatively thin epitaxial layer, so if the concentration of the epitaxial layer 2 is low, punch-through will occur between the source and drain, and if the concentration is high, The problem was that voltage breakdown occurred at the drain, and in any case, it was difficult to obtain a sufficiently high withstand voltage.

<Purpose of the invention> This invention eliminates the drawbacks of the conventional FETs mentioned above,
The present invention provides an FET that can improve high-frequency characteristics by reducing drain capacitance and also improve high-output characteristics by increasing drain breakdown voltage.

<Example> An n-channel MOSFET will be explained in detail.

In Fig. 2, a p-type epitaxial layer 2 is formed on a high impurity concentration p ⁺ substrate 1 with a (100) surface orientation. The silicon other than the portion that will become the drain region of the p-type epitaxial layer 2 is directly etched, or the selective oxidation (LOCOS) method is used to suppress oxidation of the drain region portion and etch the other oxidized regions, thereby making the substrate surface of the drain region portion higher than the other substrate surfaces. That is, a protrusion 11 is formed in advance on the surface of the epitaxial layer 2 so that the portion of the substrate that will form the drain region is spaced farther from the high impurity concentration substrate 1 than the other regions.
Next, an n ^- region 3 for a low concentration drift region is formed by ion implantation or the like, except for the portion that will become the gate, including the protruding portion 11. A window is opened by etching in the oxide film 12 that covers the protruding portion 11 on the n ^- region 3 where the drain region is to be formed.
forming an n ⁺ region 13 on the exposed ^n- region 3 by polysilicon or selective epitaxy;
Further, a metal film such as Al is deposited to form the drain electrode 8. After the epitaxial layer 2 is etched to form the protrusion 11, the source region 5 is formed by forming a high concentration of n-type impurities in a predetermined region of the epitaxial layer 2, then removing almost the center of the n ⁺ region for the source region with an anisotropic etching solution, and forming ^a V
A groove 6 is formed. A conductor 7 such as Al is deposited on the surface of the V-groove 6 to form a source electrode. The source electrode 7 is connected to the ground together with the back electrode of the p ⁺ substrate 1. The source region having the groove 6 is
The gate electrode 9 is formed on the substrate between the drift region 3 and the source region 5. The gate electrode 9 is formed at a suitable point in the process of fabricating the MOSFET.

In the FET with the above structure, the drain region is formed at a position farther from the p ⁺ substrate, which has a higher impurity concentration than in the conventional structure, and this greatly contributes to improving the breakdown voltage and frequency characteristics of the FET.

Embodiment 2 In this embodiment, an n ⁻ layer is separately deposited to provide a distance between the p ⁺ substrate 1 and the drain region.

In FIG. 3, the epitaxial 2 surface of a (100) semiconductor substrate having a p ⁺ onp type structure as in the previous embodiment is coated with a low impurity concentration except for the gate region.
An ⁿ -drift region 3 is formed. A window is opened in a part of the oxide film 12 covering the n ^- drift region 3 (the part that will become the drain region), and an n ^- epitaxial layer 14 with a low impurity concentration is selectively deposited through the window,
Increase the distance from p ⁺ board 1 side. deposited
n ^- layer 14 surface is highly concentrated and n ⁺ drain region 1
5 and a drain electrode 8 is formed. V groove 6
The source region 5 and gate portion 9 having the structure are formed in the same manner as in the previous embodiment. of the structure
The FET is formed by adding a continuous n ^- layer of the same conductivity type and the same or different concentration on the n ^- drift region, and by increasing the distance from the p ⁺ substrate 1 by this n ^- layer. and improve the characteristics.

<Effect> As described above, in the FET structure of the present invention, a part of the surface of the drift region is formed higher than other parts, and a drain region is formed on the part of the surface of the drift region formed higher. , the drain region can be further separated from the highly doped substrate, resulting in higher drain withstand voltage, less punch-through, and even higher output possible.In addition, the reduction in drain capacitance further improves high-frequency characteristics. A high output high frequency transistor can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional device, FIG. 2 is a sectional view of one embodiment of the present invention, and FIG. 3 is a sectional view of another embodiment of the present invention. 1...p ⁺ substrate, 2...p type epitaxial layer,
3...n ^- drift region, 6... V groove, 7... source electrode, 8... drain electrode, 9... gate electrode, 11... convex portion, 13, 15... n ⁺ drain region, 14... …n ^-layer .

Claims (1)

[Claim for Utility Model Registration] A (100) silicon substrate in which an epitaxial layer of the same conductivity type is formed on a high impurity concentration substrate, and an epitaxial layer of the opposite conductivity type located between the drain region and gate region formed on the silicon substrate. A field effect transistor comprising a drift region with a low impurity concentration and a source electrode formed in a V-groove surface with a depth reaching from the substrate surface of the source region to the high impurity concentration substrate and grounded together with the high impurity concentration substrate, A part of the surface of the drift region is formed higher than other parts, a drain region is formed on the part of the surface of the drift region formed higher, and a distance between the surface of the other part of the drift region and the high impurity concentration substrate surface. A high-output high-frequency transistor characterized in that the distance between the drain region and the highly impurity-concentrated substrate surface is formed larger than that of the above-described high-power high-frequency transistor.