JPS59119046U - High power high frequency transistor - Google Patents

High power high frequency transistor

Info

Publication number
JPS59119046U
JPS59119046U JP1379383U JP1379383U JPS59119046U JP S59119046 U JPS59119046 U JP S59119046U JP 1379383 U JP1379383 U JP 1379383U JP 1379383 U JP1379383 U JP 1379383U JP S59119046 U JPS59119046 U JP S59119046U
Authority
JP
Japan
Prior art keywords
region
impurity concentration
drain
substrate
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1379383U
Other languages
Japanese (ja)
Other versions
JPH051084Y2 (en
Inventor
滝野 孝則
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP1379383U priority Critical patent/JPS59119046U/en
Publication of JPS59119046U publication Critical patent/JPS59119046U/en
Application granted granted Critical
Publication of JPH051084Y2 publication Critical patent/JPH051084Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来装置の断面図、第2図は本考案による一実
施例の断面図、第3図は本考案による他の実施例の断面
図である。 1:p子基板、2:p型エピタキシャル層、3:n−ド
リフト領域、6:V溝、7:ソース電極、8ニドレイン
電極、9:ゲート電極、11:凸部、13゜15:n+
ドレイン領域、14:n一層。
FIG. 1 is a sectional view of a conventional device, FIG. 2 is a sectional view of one embodiment of the present invention, and FIG. 3 is a sectional view of another embodiment of the present invention. 1: p-substrate, 2: p-type epitaxial layer, 3: n-drift region, 6: V groove, 7: source electrode, 8 drain electrode, 9: gate electrode, 11: protrusion, 13° 15: n+
Drain region, 14:n single layer.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)高不純物濃度基板に同一導電型のエピタキシャル
層を形成した(100)シリコン基板と、該シリコン基
板に形成されたドレイン領域とゲート領域間に位置する
逆導電型の低不純物濃度のドリフト領域と、ソース領域
の基板表面から高不純物濃度基板に達する深さの■溝面
に形成され、且つ高不純物濃度基板と共に接地されるソ
ース電極とを備えてなる電界効果トランジスタにおいて
、ドリフト領域上にドレイン領域を形成し、ドリフト領
域表面と高不純物濃度基板面との間階に比べて上記ドレ
イン領域表面と高不純物濃度基板面との間隔を大きく形
成してなることを特徴とする高出力高周波トランジスタ
(1) A (100) silicon substrate in which an epitaxial layer of the same conductivity type is formed on a high impurity concentration substrate, and a low impurity concentration drift region of the opposite conductivity type located between the drain region and gate region formed on the silicon substrate. In a field effect transistor, a drain is formed on the drift region, and a source electrode is formed in a groove surface with a depth reaching from the substrate surface of the source region to the high impurity concentration substrate and is grounded together with the high impurity concentration substrate. A high-power high-frequency transistor characterized in that a region is formed, and the distance between the drain region surface and the high impurity concentration substrate surface is larger than the distance between the drift region surface and the high impurity concentration substrate surface.
(2)前記ドレイン領域を形成するドリフト領域に対し
て他の周辺のドリフト領域は選択エツチングによって除
去され、ドレイン形成部に比べて薄いエピタキシャル層
部にドリフト領域を形成シ、選択エツチングされないエ
ピタキシャル部にドレインが形成されてなる請求の範囲
第1項記載の高出力高周波トランジスタ。
(2) The other drift regions surrounding the drift region forming the drain region are removed by selective etching, and the drift region is formed in the epitaxial layer portion that is thinner than the drain forming region. 2. The high output high frequency transistor according to claim 1, wherein a drain is formed.
(3)前記ドレイン領域を堆積するドリフト領域は選択
的に低濃度不純物層が堆積されてなり、高不純物濃度基
板からの距離を大きくしたことを特徴とする請求の範囲
第1項記載の高出力高周波トランジスタ。
(3) The high output according to claim 1, characterized in that the drift region in which the drain region is deposited is formed by selectively depositing a low concentration impurity layer, and the distance from the high impurity concentration substrate is increased. High frequency transistor.
JP1379383U 1983-01-31 1983-01-31 High power high frequency transistor Granted JPS59119046U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1379383U JPS59119046U (en) 1983-01-31 1983-01-31 High power high frequency transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1379383U JPS59119046U (en) 1983-01-31 1983-01-31 High power high frequency transistor

Publications (2)

Publication Number Publication Date
JPS59119046U true JPS59119046U (en) 1984-08-11
JPH051084Y2 JPH051084Y2 (en) 1993-01-12

Family

ID=30145170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1379383U Granted JPS59119046U (en) 1983-01-31 1983-01-31 High power high frequency transistor

Country Status (1)

Country Link
JP (1) JPS59119046U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100979A (en) * 1973-01-31 1974-09-24
JPS508484A (en) * 1973-05-21 1975-01-28
JPS53108382A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100979A (en) * 1973-01-31 1974-09-24
JPS508484A (en) * 1973-05-21 1975-01-28
JPS53108382A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH051084Y2 (en) 1993-01-12

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