JPS6099553U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6099553U
JPS6099553U JP16126884U JP16126884U JPS6099553U JP S6099553 U JPS6099553 U JP S6099553U JP 16126884 U JP16126884 U JP 16126884U JP 16126884 U JP16126884 U JP 16126884U JP S6099553 U JPS6099553 U JP S6099553U
Authority
JP
Japan
Prior art keywords
source
gate electrode
drain contact
semiconductor substrate
contact regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16126884U
Other languages
Japanese (ja)
Inventor
伸夫 佐々木
元雄 中野
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP16126884U priority Critical patent/JPS6099553U/en
Publication of JPS6099553U publication Critical patent/JPS6099553U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はショートチャンネル特性を説明す
る断面図およびグラフ、第3図は本考案  ・の実施例
を示す断面図、第4図は別途提案し−た素子の構造を示
す断面図である。 図面で4はゲート電極、2はソース領域、3はドレイン
領域、9はソースコンタクト領域、10はドレインコン
タクト領域、5は絶縁膜、1は半導体基板、11.12
は高不純物濃度層である。
Figures 1 and 2 are cross-sectional views and graphs explaining short channel characteristics, Figure 3 is a cross-sectional view showing an embodiment of the present invention, and Figure 4 is a cross-sectional view showing the structure of a separately proposed element. It is. In the drawing, 4 is a gate electrode, 2 is a source region, 3 is a drain region, 9 is a source contact region, 10 is a drain contact region, 5 is an insulating film, 1 is a semiconductor substrate, 11.12
is a high impurity concentration layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基板の表面に絶縁層を介して被着されたゲート電
極、該ゲート電極の両側に該ゲート電極より離して半導
体基板に形成されたソース、ドレイン各コンタクト領域
、該ゲート電極とソース、ドレイン各コンタクト領域と
の間の半導体基板表面の絶縁層に開口した窓を通して不
純物注入で半導体基板に形成され、ソース、ドレイン各
コンタクト領域より浅いソース、ドレイン各領及び該領
域の直下に形成された空乏層抑止用の高不純物濃度層を
備えることを特徴とする半導体装置。
A gate electrode deposited on the surface of a semiconductor substrate via an insulating layer, source and drain contact regions formed on both sides of the gate electrode at a distance from the gate electrode, and a source and drain contact region between the gate electrode and the source and drain. A depletion layer formed in the semiconductor substrate by impurity implantation through a window opened in the insulating layer on the surface of the semiconductor substrate between the contact region and shallower than the source and drain contact regions and directly below the source and drain contact regions. A semiconductor device characterized by comprising a high impurity concentration layer for suppression.
JP16126884U 1984-10-25 1984-10-25 semiconductor equipment Pending JPS6099553U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16126884U JPS6099553U (en) 1984-10-25 1984-10-25 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16126884U JPS6099553U (en) 1984-10-25 1984-10-25 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6099553U true JPS6099553U (en) 1985-07-06

Family

ID=30354467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16126884U Pending JPS6099553U (en) 1984-10-25 1984-10-25 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6099553U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049182A (en) * 1999-12-16 2007-02-22 Spinnaker Semiconductor Inc System and method of mosfet device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49105495A (en) * 1973-02-07 1974-10-05
JPS508484A (en) * 1973-05-21 1975-01-28
JPS5023989A (en) * 1973-07-02 1975-03-14
JPS5121481A (en) * 1974-08-14 1976-02-20 Matsushita Electric Ind Co Ltd Mos gatadenkaikokatoranjisuta

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49105495A (en) * 1973-02-07 1974-10-05
JPS508484A (en) * 1973-05-21 1975-01-28
JPS5023989A (en) * 1973-07-02 1975-03-14
JPS5121481A (en) * 1974-08-14 1976-02-20 Matsushita Electric Ind Co Ltd Mos gatadenkaikokatoranjisuta

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049182A (en) * 1999-12-16 2007-02-22 Spinnaker Semiconductor Inc System and method of mosfet device

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