JPH0786424A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the parasitic resistance between a buried well layer and a formed electrode, by arranging an impurity layer whose concentration is higher than that of an element isolation region, between a buried well layer and the surface of a substrate, in a region where well contact is obtained. CONSTITUTION:A field oxide film 2 is formed on a silicon substrate 1. In the case of an N-channel, boron is implanted with energy of 200KeV or larger to obtain ion concentration of 10<12>-10<13>cm-<2>. In the case of a P-channel, phosphorus is implanted with energy of 400KeV or larger to obtain the same concentration. Thereby a buried well layer 3 is formed. A resist layer 7 masking the region except the vicinity of a well contact region and an element isolation region is formed. An intermediate impurity layer 4 is formed on the buried well layer by implanting ions of about 10<12>cm-<2>, with energy lower than or equal to the implantation energy at the time of forming a buried well in the mask. Thereby the resistance of a high resistance layer remaining between a retrograde well layer and the substrate surface can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a buried well layer formed by high energy ion implantation and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, in integrated circuit devices, CMs have been used because of their advantages such as high noise margin and low power consumption.
The importance of OS type semiconductor devices is increasing. However,
Along with the miniaturization, latch-up caused by a parasitic thyristor formed in a portion adjacent to the constituent NMOS type transistor and PMOS type transistor has become a serious problem. Therefore, in order to solve this problem, a method has been proposed in which a so-called retrograde well having a high-concentration region at the bottom of the well is formed to reduce the amplification factor of a parasitic bipolar transistor and thereby reduce latch-up. . For example, in the method disclosed in Japanese Patent Laid-Open No. 2-305468, a field oxide film 2 is formed on a silicon substrate 1 by a normal selective oxidation method for element isolation as shown in FIG. As shown in the same figure, in order to prevent field inversion in the portion 4a below the field oxide film, in the case of boron, depending on the field oxide film thickness, 1
00-200 KeV, phosphorous 300-600 KeV
Ion implantation of about 10 ¹² to 10 ¹³ cm ^{-2 is performed} with the energy of. Next, as shown in FIG. 4B, in order to form a high-concentration region 3 at the bottom peculiar to the retrograde well, a high energy of 2 MeV for boron and 3 MeV for phosphorus is formed at a depth of about 2 to 4 μm. Ion implantation is performed. After that, appropriate ion implantation is performed on the impurity layer 4 and the intermediate region 5 between the high concentration region 3 and the region 6 shallower than the impurity layer 4.

[0003]

In the conventional retrograde well formation process described above, the impurity layer 4 for increasing the field inversion voltage and the deep high-concentration layer 3 have a concentration of 10 ¹⁷ cm ³
Although it has the above-mentioned impurity concentration, the intermediate region between the both ion-implanted layers has a structure in which a low-concentration layer of about 10 ¹⁶ cm ^-3 remains. Therefore, although the resistance at the bottom of the well is lowered, the substrate surface on which the extraction electrode for the well potential is formed,
The low-impurity region 5 is inserted as a high-resistance layer between the deep high-concentration layers 3, which causes a problem that the effect of lowering the well resistance in the deep region of the substrate is offset. As a countermeasure against this, it is conceivable to increase the concentration of the intermediate region 5 over the entire well region, but since this method also increases the impurity concentration under the source and drain diffusion layers of the transistor, it is said that the extra parasitic capacitance increases dramatically. There are drawbacks.

[0004]

SUMMARY OF THE INVENTION The present invention is a complementary MOS.
In a semiconductor device having a field effect transistor, N
A buried well layer composed of a high-concentration deep P-type ion implantation layer and a deep N-type ion implantation layer is formed in advance in the transistor formation portions of the channel and P-channel, respectively.
At least the region of the semiconductor substrate in contact with each well formed by the both ion-implanted layers,
The semiconductor device has a structure in which an impurity layer having the same conductivity type as that of the deep ion implantation layer having a higher concentration than that of the element formation region is provided between the deep ion implantation layer and the surface of the substrate.
In a method of manufacturing a semiconductor device having a MOS structure, a step of forming a field oxide film in a desired region of a semiconductor substrate, a step of forming a buried well layer using ion implantation in a deep region of the substrate, A region of the well region where the well potential is applied includes the deep buried well layer and a step of forming an impurity layer having the same conductivity type as that of the buried well layer having a higher concentration than that of the element formation region between the deep buried well layer and the substrate surface. It is a method of manufacturing a semiconductor device.

[0005]

In the present invention, there is a buried well layer formed by high energy implantation, and an impurity layer having a higher concentration than that of the element forming region is disposed between the buried well layer and the substrate surface in at least the well contact region. With this structure, the resistance of the high-resistance layer remaining between the retrograde well layer and the substrate surface can be lowered, and the latch-up can be strengthened.

[0006]

Embodiments of the present invention will be described with reference to the drawings. In the following description, for the sake of simplicity, the well structure of both conductivity types will be described with reference to the same drawing. FIG. 1 shows the structure of a retrograde well according to one embodiment of the present invention. Buried well layer 3 composed of a deep ion implantation layer in the well region
Are formed and the well contact is made in the region 5,
An intermediate impurity layer 4 is formed between the buried well layer 3 and the substrate surface. In this case, the deep buried well layer 3 is a deep P-type ion implantation layer in the N channel region,
In the P channel region, the impurity layer 4 formed of a deep N type ion implantation layer and in the middle of each well is formed to have the same conductivity type as that of each buried well layer 3. Next, the manufacturing method of the present invention will be described with reference to FIGS. First, as shown in FIG. 2A, after forming the field oxide film 2 on the silicon substrate 1, in the case of N-channel, for example, boron is 200 KeV or more, and in the case of P-channel, phosphorus is energy of 400 KeV or more. 10 in each area
Ions are implanted at about ¹² to 10 ¹³ cm ^-2 to form a buried well layer 3. The ion implantation into each well formation planned region is performed only in a desired region using a resist mask (not shown) formed by ordinary photolithography or the like.

Next, as shown in FIG. 2B, a resist layer 7 for masking the vicinity of the well contact region and the region other than the element isolation region is formed by using photolithography or the like, and this is used as a mask to perform the implantation for forming the buried well. Ion implantation of about 10 ¹² cm ^-2 is performed at an energy level lower than the energy to form the intermediate impurity layer 4 on the buried well layer. After that, activation annealing of the ion-implanted impurity layer is performed, and then, in the usual process, necessary elemental channel doping or the like is performed in the element formation planned region to complete the element. Impurity profiles of the device formation planned region 6 and the wellcon formation planned region 5 obtained by this method are shown in FIGS. 3 (a) and 3 (b). In this embodiment, the intermediate impurity concentration in the well contact region can be reduced as compared with the conventional example, and the substrate concentration in the element forming region can be made low until the buried well layer, so that the impurity scattering in the channel layer of the transistor is small, Moreover, a high-performance transistor with a small substrate bias effect can be obtained. In the above-described embodiment, when the resist mask 7 for forming the intermediate impurity layer 4 is formed in a pattern in which the well contact forming region and the channel region of the transistor are formed together as shown in FIG. 2C. There is an advantage that the wellcon intermediate layer can be formed and the channel doping of the transistor can be performed in one lithography process. The device cross section thus obtained is shown in FIG. Further, FIG. 5A shows the impurity profile along the AA ′ cross section and the BB ′ cross section of FIG. 5D.
It shows in (b). In this embodiment, the source and drain n
^Since the substrate impurity concentration of the ⁺ layer 9 can be lowered as shown in FIG. 5A, a transistor having a small parasitic diffusion layer capacitance can be obtained in a simplified process.

[0008]

As described above, according to the present invention, in a semiconductor device having a buried well layer formed by high-energy implantation, an impurity layer having a higher concentration than that of an element forming region is formed in at least a well contact region. By placing it between the buried well layer and the substrate surface,
The parasitic resistance between the buried well layer and the installation electrode can be reduced without adversely affecting the device characteristics, and a high-speed semiconductor device that is resistant to latch-up can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing the manufacturing method of the present invention.

FIG. 3 is an impurity concentration profile when formed according to FIG.

FIG. 4 is a sectional view showing a conventional example.

5 is an impurity profile of the process sectional view of FIG. 2;

[Explanation of symbols]

 1 Silicon Substrate 2 Field Oxide Film 3 Buried Well Layer 4 Intermediate Impurity Layer

Claims (2)

[Claims] 1. In a semiconductor device having a complementary MOS field effect transistor, a high-concentration deep P-type ion implantation layer and a high-concentration deep N-type ion implantation layer are formed in N-channel and P-channel transistor forming portions, respectively.
At least in the region of the semiconductor substrate in contact with each well formed by the deep ion implantation layer, between the deep ion implantation layer and the substrate surface, the deep ions having a higher concentration than the element formation region are formed. A semiconductor device having a structure in which an impurity layer having the same conductivity type as the injection layer is provided. 2. A method of manufacturing a semiconductor device having a complementary MOS field effect transistor, wherein a step of forming a field oxide film in a desired region of a semiconductor substrate and an ion formation in a well formation planned region of each of N channel and P channel are performed. Forming a buried well layer made of a P-type impurity layer and an N-type impurity layer in a deep region of the substrate by implantation, and forming the deep buried well layer and the substrate in at least a well potential region of the well region. A step of forming an impurity layer having the same conductivity type as that of the buried well layer having a higher concentration than that of the element forming region between the surface and the surface of the element forming region.