JPH02133967A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set two different threshold value voltages by one MOS transistor by so forming a floating gate electrode that the overlapping region between a source diffused layer and a drain diffused layer is different. CONSTITUTION:A semiconductor device is composed of a MOS transistor formed of an Si board 1 having source and drain diffused layers 2 and 3, a floating gate electrode 4 disposed through a gate insulating film 6, and a control gate electrode 5 disposed through an insulating film 7, and the electrode 4 is so disposed that the overlapping region 3a between the layers 2 and 3 is larger than the overlapping region 2a. Accordingly, a capacity CFS formed between the gate electrode and the source diffused layer is different from that CFD formed between the gate electrode and the drain diffused layer, the bias condition at the source side at the time of operation is replaced with that at the drain side to obtain two threshold value voltages for one transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field This invention relates to semiconductor devices, more specifically MOS transistors. By utilizing the different characteristics, one MOS transistor can generate two different
The present invention provides a floating gate type semiconductor device having a threshold voltage of .

(b) Problems to be solved by the prior art and the invention In a normal MOS transistor, for example, as shown in FIG.
Si substrate 2 with 3! Since the gate electrode 25 is disposed on the top via the 5ift film 24, the same characteristics will be obtained even if the bias conditions during operation are switched between the source side and the drain side. Only one threshold voltage could be set.

(C) Means for Solving the Problems This invention has source and drain diffusion layers of a second conductivity type in the surface region of a semiconductor substrate of a first conductivity type, and a gate insulating film is provided between at least the two diffusion layers. In a floating gate MOS transistor, a floating gate electrode is formed through an insulating film, and a control gate electrode is further formed through an insulating film. It is formed so that it is different from the above.

For example, (i) as shown in FIG. 1, the overlap region 3a between the floating gate electrode 4 and the drain diffusion layer 3 is set wider from the top of the overlap region 2a with the source diffusion layer 2, or (ii) as shown in FIG. As shown, the thickness of the gate oxide film 6a sandwiched between the floating gate electrode 14 and the drain diffusion layer 3 is defined as the floating gate i!
Gate oxide film 6 sandwiched between Ji 14 and source diffusion layer 2
The capacitances of the overlap regions 2a and 3a are made different by forming the overlap regions 2a and 3a thinner.

(D) Function The present invention provides a floating gate il! by forming the floating gate electrode of a floating gate type MOS transistor so that the overlapping regions with the source diffusion layer and the drain diffusion layer are different. The capacitance ff1crs between the electrode and the source diffusion layer and the capacitance cpa between the floating gate electrode and the drain diffusion layer can be set to different values, and by exchanging the bias conditions during operation between the source side and the drain side, one Two different threshold voltages can be set using the MOS transistor.

(e) Examples The present invention will be described in detail below based on embodiments shown in the figures.

Note that this invention is not limited by this.

1.2 shows an embodiment of a semiconductor device according to the present invention, FIG. 1 is a cross-sectional view of a MOS transistor having a floating gate, and FIG. 2 is an equivalent circuit diagram of the MOS transistor of FIG. 1. .

In FIG. 1, the semiconductor device includes an Si substrate 1 having source and drain diffusion layers 2 and 3, and a gate insulating film 6 made of 5i (L) on a channel region Ia formed between both the diffusion layers 2 and 3. Floating gate arranged through (rloating gate)
It mainly consists of a floating gate MOS transistor composed of an electrode 4 and a control gate electrode 5 disposed through an insulating film 7 of the floating gate electrode.

Furthermore, the floating gate electrode 4 has an overlap region 3a with respect to the overlap regions 2a and 3a (indicated by diagonal lines) with the source diffusion layer 2 and drain diffusion layer 3.
is set larger than the overlap area 2a.

Note that 7 is an insulating film made of a silicon oxide film formed by the CVD method.

In the transistor having the above configuration, the source diffusion layer 2, drain diffusion layer 3, floating gate electrode 4, and control gate electrode 5 are each capacitively coupled, so that C+(Vr-vc)"Cro(Vr-Vo)" CFs(
VE-Vs)”Cra(Vr-Vb)・0
. . . If ■ holds true and transforms, Crt++Crs+C++Cra Next, consider the bias conditions during operation shown below (IO2).

(1) The transistor characteristics at the potential v5-0 of the source diffusion layer 2 and the potential Vo-Vcc of the drain diffusion layer 3 are as follows: The floating gate voltage at which the transistor starts to turn on is VFT, and the threshold voltage is 2A. Then, CFD+CFS+CI+CFB is obtained.On the other hand, (2) The transistor characteristics at the potential Vs-Vcc of the two source diffusion layers and the potential VD=O of the drain diffusion layer 3 are as follows.
If the floating gate voltage at which the transistor starts to turn on is FT, and the threshold voltage is Vrs, then Cro+Crs+C++CFe is obtained.

Therefore, from ■■ becomes.

CFD CFS Vts VTD= VCC・・・・・・
・It becomes ■.

Therefore, by setting CFD f-Crs, Vts+V
ta, and by exchanging the bias conditions during operation between the source side and the drain side, different threshold values can be obtained as shown in the equation 0.0.

Here, C1: floating gate voltage 1! ! Capacitance CFs between source diffusion layer 2 and control gate electrode 5: source diffusion layer 2 and floating gate electrode 4
Capacitance between CFD Nidrain diffusion layer 3 and floating gate electrode 4 Capacitance CFEI: Capacitance between substrate l and floating gate electrode 4 VC: Potential of control gate electrode 5 vs = Potential of source diffusion layer 2 Vo of Nidrain diffusion layer 3 Potential ■B Potential Vcc of the two substrates 1: Power supply voltage ■Fo: This is the floating gate voltage of the floating gate electrode 4 when the transistor starts to turn on.

In addition, in formula (■), by setting the capacitance values of Cro, Crs, and C+, 2
threshold voltage VT5. Each VTD can be set individually. Furthermore, even when the capacitance difference between Cro and Cvs is small, the optimal threshold voltage width (=V↑s VTD) can be set by the interelectrode capacitance 31 Cr, so it can be applied to fine transistors.

FIG. 3 shows an embodiment of the pond of this invention.

In this case as well, in the MOS transistor consisting of the floating gate 1i pole 14 and the control gate electrode 5 that controls the channel, the capacitance ff1c+s between the floating gate electrode 14 and the source diffusion layer 2 and the capacitance ff1c+s between the floating gate electrode 14 and the drain diffusion layer 3 are determined. By making the capacitance CFD asymmetric by setting the overlap regions 2a and 3a to different sizes, a threshold voltage of 2g can be set with one MOS transistor.
The same effects as in the above embodiment are achieved.

In each of the above embodiments, a two-layer gate electrode structure is shown, but it can also be applied to a gate electrode structure with two or more layers. In this case, the capacitance between the first layer gate electrode and the source and drain diffusion layers is It can also be applied to structures with asymmetrical structures.

(f) Effects of the invention As described above, according to the present invention, the floating gate M
By arranging the floating gate electrode of the OS transistor so that the overlap regions with the source diffusion layer and the drain diffusion layer have different sizes,
The capacitance Cvs formed between the floating gate electrode and the source diffusion layer is different from the capacitance Cvs formed between the floating gate electrode and the drain diffusion layer.
Thereby, by exchanging the bias conditions during operation between the source side and the train side, two threshold voltages can be obtained for one MOS transistor. Furthermore, the difference between the overlap regions 2a and 3a is small, and the capacitance Crs
Even if the difference between
A MOS transistor suitable for miniaturization can be realized.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration showing one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram thereof, Fig. 3 is an explanatory diagram of the configuration of another embodiment of the invention, and Fig. 4 is a conventional example. It is a configuration explanatory diagram. 1... S+ substrate, 2... Source diffusion layer, 2a... Overlapping region of floating gate electrode and source diffusion layer, 3... Drain diffusion layer , 3a...Overlapping region of floating gate electrode and drain diffusion layer, 4.14...Floating gate electrode, 5.
...Control gate electrode, 6...Gate insulating film. Agent: Shinta Nogawa, Patent Attorney

Claims (1)

[Claims] 1. A source and drain diffusion layer of a second conductivity type is provided in a surface region of a semiconductor substrate of a first conductivity type, a floating gate electrode is formed at least between the two diffusion layers via a gate insulating film, and an insulating film is further formed. 1. A floating gate MOS transistor having a control gate electrode formed therebetween, wherein a capacitance between the floating gate electrode and a source diffusion layer is different from a capacitance between the floating gate electrode and the drain diffusion layer.