JPH0786422A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of electrode of a transistor constituting the circuit of a semiconductor device, and improve the level of integration. CONSTITUTION:An N-type MOSFET is connected with an MOS type JFET in series, and a circuit (inverter) is formed. The MOS type JFET has electrodes 3, 6b whose area is equal to the area of electrodes 4, 6a of the N-type MOSFET, and has an electrode 13 which faces the electrode 6b. The MOS type JFET operates as a switching element wherein the channel width (a depletion layer) is controlled by the electrode 6b, 13. As compared with the case where the N-type MOSFET is connected with a P-type MOSFET in series, the area of the electrodes 3, 6b are small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as IC and LSI.

[0002]

2. Description of the Related Art FIG. 5 shows the structure of a conventional semiconductor device.
FIG. 5A is a diagram schematically showing a cross section of a switch element generally called a CMOS inverter, in which 1 is a p-type semiconductor substrate on which an electronic circuit is formed and 2 is a p-type semiconductor substrate.
N-type impurity regions 3a, 3a formed on the n-type semiconductor substrate 1
b is a high-concentration p-type impurity region formed in the n-type impurity region 2, 4a and 4b are high-concentration n-type impurity regions formed in the p-type semiconductor substrate 1, and 5 is a gate electrode 6a, 6b and a p-type semiconductor substrate. A gate insulating film such as SiO ₂ for insulating 1 from each other and 6a and 6b are gate electrodes formed on the gate insulating film 5.

The n-type impurity region 2, the high-concentration p-type impurity regions 3a and 3b, and the gate electrode 6a are p-type MOSFs.
ET (Metal Oxide Semiconductor Field Effect Trans
istor). On the other hand, the semiconductor substrate 1, the high-concentration n-type impurity regions 4a and 4b, and the gate electrode 6a are the n-type MOS.
Configure FET. 7 is a p-type MOSFET and an n-type MO
A gate wiring for connecting a common voltage to the gate electrodes 6a and 6b of the SFET, and 8 for a p-type M
Drain electrode of OSFET (high concentration p-type impurity region 3
a) and the drain electrode (high-concentration n-type impurity region 4a) of the n-type MOSFET, and output wirings for extracting an output from these, 9 and 10 are p-type MOS, respectively.
FET source electrode (high-concentration p-type impurity region 3b), n
-Type MOSFET source electrode (high-concentration n-type impurity region 4
Power supply wiring for supplying power to b). Further, FIG. 5B shows a plan view of a conventional semiconductor device. For simplicity, the wirings 7 to 10 are not shown in the figure.

The operation of the conventional semiconductor device will be described below with reference to FIG. In the CMOS circuit composed of the p-type MOSFET and the n-type MOSFET of FIG. 5, the power supply wiring 10 of the p-type semiconductor substrate 1 is grounded (0 V).
Then, a power supply voltage (for example, 5 V) is applied to the power supply wiring 9. Then, when 0 V is applied to the gate wiring 7, the n-type MOSFE
T turns off and the p-type MOSFET turns on. Therefore, the same power supply voltage (5 V) as that of the power supply wiring 9 is output to the output wiring 8.

On the other hand, when 5 V is applied to the gate wiring 7, the n-type MOSFET is turned on and p is reversed, contrary to the above case.
The type MOSFET is turned off, and the same ground voltage (0 V) as that of the power supply wiring 10 is output to the output wiring.

By the way, in the CMOS type circuit, the current flowing through the transistor hardly flows when the output does not change, and flows mainly when the output changes. That is, when the gate wiring 7 becomes 0V, p-type MOSFE
Output current flows through T, while gate wiring 7 is 5V
Then, the output current flows through the n-type MOSFET.

As described above, the element having the CMOS structure shown in FIG. 4 is an inverter circuit which outputs a signal having a polarity opposite to that of the input.

[0008]

The conventional semiconductor device is
It is configured as described above, and when switching, p
The same current must flow through the type MOSFET and the n-type MOSFET. However, holes, which are carriers of p-type MOSFET, have lower mobility than electrons, which are carriers of n-type MOSFET, and their operating speeds are not the same.
There is a difference in current density. Therefore, as shown in FIG. 5B, the areas of the drain electrode 3a, the source electrode 3b, and the gate electrode 6b of the p-type MOSFET are smaller than the areas of the drain electrode 4a, the source electrode 4b, and the gate electrode 6a of the n-type MOSFET. By increasing the mobility according to the ratio, the currents are made almost the same and the switching speeds are made equal. However, the large-area electrode for this purpose has been an obstacle to improving the degree of integration of the semiconductor device.

The present invention has been made in order to solve the above-mentioned problems, and the switching speed is made equal without increasing the area of the electrode of one of the transistors forming the internal circuit, and the degree of integration is high. The purpose is to obtain a semiconductor device that can be manufactured.

[0010]

A semiconductor device according to a first aspect of the present invention includes a MOS transistor provided on a semiconductor substrate,
A first electrode having substantially the same area as the electrode of the MOS transistor is provided on the first surface of the semiconductor substrate provided with the MOS transistor, and the first electrode is provided.
On the second surface of the semiconductor substrate facing the surface of the first substrate.
And a MOS type junction field effect transistor provided with a second electrode facing the electrode.

According to another aspect of the semiconductor device of the present invention, the MOS transistor provided on the semiconductor substrate and the electrode of the MOS transistor on the first surface of the semiconductor substrate provided with the MOS transistor are substantially the same. And a second electrode is provided only on a portion of the second surface of the semiconductor substrate which faces the first surface and which faces the first electrode. And a junction field effect transistor.

According to another aspect of the semiconductor device of the present invention, the first electrode is provided on the p-type region of the first surface of the semiconductor substrate, and the second surface of the semiconductor substrate opposite to the first surface is provided. A hole-conducting MOS-junction field effect transistor having a second electrode facing the first electrode, and a third electrode on the n-type region of the first surface of the semiconductor substrate. An electron-conducting MOS-junction field-effect transistor which is provided and has a fourth electrode facing the third electrode on the second surface.

According to another aspect of the semiconductor device of the present invention, an impurity region is formed on a first surface of a semiconductor substrate, and a MOS transistor provided on the impurity region and a MOS transistor on the impurity region are formed. A first electrode having substantially the same area as the electrode is provided, and a second electrode facing the first electrode is provided on the second surface of the semiconductor substrate facing the first surface. And a hole conduction MOS type junction field effect transistor.

[0014]

According to another aspect of the present invention, there is provided an MO type transistor including a MOS type transistor and a first electrode connected in series to the MOS type transistor and having an area substantially the same as the electrode of the MOS type transistor.
The S-junction field effect transistor constitutes an internal circuit of the semiconductor device.

According to a second aspect of the present invention, a MOS type transistor and a first electrode connected in series with the MOS type transistor and having substantially the same area as the electrode of the MOS type transistor are provided, and the MOS type transistor is opposed to the first electrode. The hole-conducting MOS-type junction field-effect transistor having the second electrode only in the portion to be formed constitutes an internal circuit of the semiconductor device.

According to a third aspect of the invention, a hole-conducting MOS type junction field effect transistor formed in a p-type region on the semiconductor substrate and an n-type region on the semiconductor substrate connected in series thereto. The electron-conducting MOS-junction field-effect transistor formed in (1) constitutes an internal circuit of the semiconductor device.

According to a fourth aspect of the invention, a MOS transistor formed on an impurity region formed on a semiconductor substrate and a MOS transistor connected in series to the MOS transistor and having an area substantially the same as the electrode of the MOS transistor are provided. M with one electrode
The OS type junction field effect transistor constitutes an internal circuit of the semiconductor device.

[0018]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 (a) is a cross-sectional view of an inverter according to the present invention, in which 1 is a p-type semiconductor substrate on which an electronic circuit is formed, 3a and 3b are p-type semiconductor substrates 1
Of the high-concentration p-type impurity regions 4a and 4b formed on the p-type semiconductor substrate 1 and the high-concentration n-type impurity regions 5a of the p-type semiconductor substrate 1 for insulating the gate electrodes 6a and 6b from the p-type semiconductor substrate 1. A gate insulating film made of SiO ₂ or the like, 6a and 6b are gate electrodes formed on the gate insulating film 5, 11 is a gate wiring for applying a voltage to the electrode 13, 12 is an electrode 13 and p
An insulating film such as SiO ₂ for insulating from the type semiconductor substrate 1, 13 is an electrode provided facing the gate electrode 6b.

Here, the p-type semiconductor substrate 1, the high-concentration p-type impurity regions 3a and 3b, the gate electrode 6b, and the electrode 13 are n.
normally-OFF type MOS junction field effect transistor (Metal Oxide Semiconductor Junction Fie
ld Effect Transistor, hereinafter referred to as MOS type JFET). On the other hand, the semiconductor substrate 1 and the high concentration n-type impurity region 4
The points a, 4b and the gate electrode 6a constitute an n-type MOSFET as in the case of the conventional example. 7 is a MOS type JF
ET and n-type MOSFET gate electrodes 6a and 6b are connected to the gate wiring for applying a common voltage to them, and 8 is a drain electrode (high concentration p
Type impurity region 3a) and the drain electrode of the n-type MOSFET (high-concentration n-type impurity region 4a) are connected to each other, and output wirings 9 and 10 for extracting their outputs are respectively the source electrodes (high Power supply wiring for supplying power to the concentration p-type impurity region 3b) and the source electrode (high-concentration n-type impurity region 4b) of the n-type MOSFET. 1B is a plan view of the semiconductor device of this embodiment. In the figure, the wirings 7 to 10 are not shown for simplicity.

Next, the operation of the semiconductor device of this embodiment will be described with reference to FIG. MOS type JF in Figure 1
The circuit composed of the ET and the n-type MOSFET is different from the conventional CMOS circuit. Here, the power supply wiring 10 of the p-type semiconductor substrate 1 is grounded (0 V), and the power supply wiring 9 is supplied with a power supply voltage (for example, 5 V). Then, when 0 V is applied to the gate wirings 7 and 11, the n-type MOSFET becomes O
The FF is turned on, and the MOS type JFET is turned on. Therefore,
The power supply voltage is output to the output wiring 8.

Next, when 5 V is applied to the gate wirings 7 and 11, the n-type MOSFET is turned on contrary to the above case. On the other hand, MOS type JFET is a voltage V _in applied from the gate electrode 6a and the electrode 13., a depletion layer is generated in the inside of the p-type semiconductor substrate (20 in FIG. 2). Then, the depletion layer 20 is extended in accordance with the increase of the voltage V _in, usually,
The width is expanded to the maximum depletion layer width W _m shown by the following equation. _{W m = {4εkT · ln (} N A / n i) / qN A} 1/2 ε: dielectric constant of the semiconductor substrate (S _i) n _i: a semiconductor substrate (S
_i ) intrinsic concentration k: Boltzmann constant N _A : substrate concentration q: elementary charge amount T: absolute temperature For example, when N _A = 1 × 10 ¹⁶ / cm ³ , W _m ≈0.
It is 3 μm.

Therefore, the gate insulating film 5 and the insulating film 12
Between the maximum depletion layer width W _m and the maximum depletion layer width W _m (2 W _m ) or less, when an appropriate voltage is applied as shown in FIG.
The depletion layer 20 extends from the insulating layers on both sides, so that the channel is turned off. Therefore, the MOS type JFET is OF
Then, 0 V is output to the output wiring 8.

In the above operation, the speed at which the output of the output wiring 8 changes from 0V to the power supply voltage increases as the current flowing through the MOS type JFET increases. MOS type JFET
In comparison with a conventional p-type MOSFET, since a very large current can flow through an electrode having a relatively small area, as shown in FIG. 1 (b), the area of the electrode of the MOS type JFET (3a in FIG. 3b, 6b) is made equal to the area of the electrode of the n-type MOSFET (4a, 4b, 6a in the same figure), the switching speed can be made equal. Therefore, according to this embodiment, while having a finer structure than the conventional one,
A switch element (inverter in this embodiment) whose speed performance does not change can be configured.

Example 2. In the above embodiment, the electrode 1
Although 3 is formed on the entire surface facing the gate electrodes 6a and 6b, it may be formed only on the part facing the gate electrode 6b constituting the MOS JFET as shown in FIG. The operation of the MOS JFET in this case is the same as that of the first embodiment. In FIG. 3, the insulating film 12 is formed only in the portion facing the gate electrode 6b, and the electrode 13a is formed so as to overlap therewith. The electrode 13a functions as the control electrode of the MOS type JFET similarly to the electrode 13 of the first embodiment. On the other hand, an electrode 13b is formed facing the gate electrode 6a of the n-type MOSFET. This electrode 13b
Is for grounding the p-type semiconductor substrate 1.

In this embodiment, since the insulating film 12 is formed not on the entire surface but on a part thereof, the insulating film 12 is formed by implantation of oxygen.
When forming, the process can be easily performed in a short time. Furthermore, the electrode 13b allows the p-type semiconductor substrate 1 to be formed.
Can be easily grounded.

Example 3. Further, in the above embodiment, the n-type M
I used OSFET, but instead of this, electron conduction M
OS type JFET may be used. To this end, as shown in FIG. 4, an n-type impurity region 13 is formed in a part of the p-type semiconductor substrate 1, that is, a part where the high-concentration n-type impurity regions 4a and 4b and the gate electrode 6a are formed.

Since a MOS type JFET capable of passing a very large current is used instead of the n type MOSFET, an even faster inverter can be obtained.

In the above description, the case where the p-type semiconductor substrate 1 is used has been described as an example, but the same effect can be obtained even when the p-type semiconductor region is formed on the n-type semiconductor substrate. To be

[0029]

According to the first aspect of the present invention, a MOS transistor and a hole-conducting MOS junction field effect transistor having a second electrode having substantially the same area as the electrode of the MOS transistor are provided. Since the internal circuit of the semiconductor device is configured, the structure of the transistor can be made fine and the degree of integration can be improved.

According to the second aspect of the present invention, the MOS type transistor and the second electrode having substantially the same area as the electrode of the MOS type transistor are provided, and the third electrode is provided only in the portion facing the electrode. Since the internal circuit of the semiconductor device is constituted by the hole-conducting MOS type junction field effect transistor provided, the structure of the transistor can be made finer, the degree of integration can be improved, and the manufacturing process can be facilitated.

According to the invention of claim 3, the MO of hole conduction is
S-junction field effect transistor and electron-conducting MOS
Since the internal circuit of the semiconductor device is configured by the type junction field effect transistor, the structure of the transistor can be made finer, the degree of integration can be improved, and high-speed operation can be performed.

According to the invention of claim 4, the impurity region is formed on the semiconductor substrate, and the MO formed on the impurity region.
Since the internal circuit of the semiconductor device is composed of the S-type transistor and the MOS-type junction field effect transistor, p
In either case of the n-type or n-type semiconductor substrate, the structure of the transistor can be made fine and the degree of integration is improved.

[Brief description of drawings]

FIG. 1 is a sectional view and a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a principle diagram illustrating an operation of a MOS junction field effect transistor.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

5A and 5B are a cross-sectional view and a plan view of a conventional semiconductor device.

[Explanation of symbols]

 1 p-type semiconductor substrate 3 high-concentration p-type impurity region 4 high-concentration n-type impurity region 5 gate insulating film 6 gate electrode 7 gate wiring 8 output wiring 9, 10 electrode wiring 11 gate wiring 12 insulating film 13 electrode 14 n-type impurity area

Claims (4)

[Claims] 1. A semiconductor device including an internal circuit configured by connecting two transistors in series, comprising: a MOS transistor provided on a semiconductor substrate;
A first electrode having substantially the same area as the electrode of the MOS transistor is provided on the first surface of the semiconductor substrate provided with the OS type transistor, and the semiconductor substrate facing the first surface is provided. A semiconductor device comprising: a MOS-type junction field effect transistor having a second electrode provided on the second surface so as to face the first electrode. 2. A semiconductor device having an internal circuit configured by connecting two transistors in series, comprising: a MOS transistor provided on a semiconductor substrate;
A first electrode having substantially the same area as the electrode of the MOS transistor is provided on the first surface of the semiconductor substrate provided with the OS type transistor, and the semiconductor substrate facing the first surface is provided. A semiconductor device comprising a MOS junction field effect transistor having a second electrode provided only on a portion of the second surface facing the first electrode. 3. A semiconductor device including an internal circuit configured by connecting two transistors in series, wherein a first electrode is provided on a p-type region of a first surface of a semiconductor substrate, and the first electrode is provided. A MOS-junction field effect transistor of hole conduction, in which a second electrode facing the first electrode is provided on a second surface of the semiconductor substrate facing the surface, and a first face of the semiconductor substrate. And an electron-conducting MOS-junction field effect transistor in which a third electrode is provided on the n-type region and a fourth electrode facing the third electrode is provided on the second surface. A semiconductor device characterized by the above. 4. A semiconductor device having an internal circuit configured by connecting two transistors in series, wherein an impurity region is formed on a first surface of a semiconductor substrate, and a MOS transistor is provided on the impurity region. A first electrode having substantially the same area as the electrode of the MOS transistor is provided on the impurity region, and the first electrode is provided.
On the second surface of the semiconductor substrate facing the surface of the first substrate.
And a MOS type junction field effect transistor provided with a second electrode facing the electrode.