JPH0590515A - Voltage transfer circuit - Google Patents

Abstract

PURPOSE:To improve cutoff characteristics, and reduce a 'threshold value drop' at the time of voltage transfer, by connecting in series a plurality of MIS FET's whose gate electrodes are shorted, making the threshold value of the most input side MIS FET a depletion type, and making its gate insulating film thicker than other ones. CONSTITUTION:In an insulated-gate field-effect transistor MIS FET type semiconductor device which transfers drain potential to a source electrode, a depletion type MIS FET T1 and an enhancement type MIS FET T2 are formed. The gate film thickness d1 of the MIS FET T1 and the gate film thickness d2 of the MIS FET T2 are set in a relation d1>=d2. The gate length L1 of the MIS FET T1 and the gate length L2 of the MIS FET T2 are set in the relation L1>=L2. The MIS FET T1 is so designed that the threshold value is negative when a voltage is applied as a substrate bias at the time of voltage transfer. Thereby transfer is realized without a 'threshold value drop' in a point A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage transfer circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In order to set the transfer efficiency (ratio between output voltage and input voltage) to 1 in a voltage transfer circuit using MISFET, when the gate potential based on the input voltage is n channel MISFET, It must be larger than the threshold value and smaller than the threshold value in the case of p-channel MISFET. In this section, n-channel enhancement type (current does not flow when a gate voltage is not applied) M
The characteristics are explained by taking a conventional example using an ISFET, and the problem is shown in the next section.

7 and 8 are an example of a plan pattern diagram (FIG. 7A) and a sectional view (FIG. 7B) of a voltage transfer circuit using an n-channel enhancement type MISFET, and an equivalent circuit thereof, respectively. It is a figure (FIG. 8). L ₉ , d ₉ , V _in , V _out , and V _G shown in each figure mean the gate length, the gate insulating film thickness, the input voltage, the output voltage, and the gate voltage, respectively. In this circuit, V _{in is changed} to V ₁ , V ₂ , V
FIG. 9 shows V _out as a function of V _G −V _in when it is changed to ₃ (where V ₁ > V ₂ > V ₃ > 0 V). As can be seen from this figure, V _G -V _in required to set the transfer efficiency to 1 increases as V _in increases. Further, when V _in = V _G , V _in −V _out is V
_The larger _in , the larger. That is, when expressed using the symbols in FIG. 9, V _th1 > V _th2 > V _th3 , v ₁ > v ₂
> V ₃ . This is explained as follows.

FIG. 10 shows the MI used in the circuit of FIG.
This shows the substrate bias effect of the SFET, and it can be seen that the threshold value increases as the value of the reverse bias between the source and the substrate increases. (Φ _B in the figure is the Fermi potential based on the intrinsic Fermi potential of the substrate.) Even in the voltage transfer circuit that we are thinking about, there is a reverse bias between the source and the substrate, and the absolute value of that value is It is equal to the transfer voltage. That is, the MISFETs in the circuit are equivalently operating in the state where the substrate bias of −V _in is applied. Therefore, the larger the V _in , the larger the threshold value, and the transfer efficiency becomes 1
A larger V _G is needed to achieve Also V _in
= V _G , V _out is V _G −V _out (= V _in −
V _out ) is determined to be equal to the threshold when a substrate bias of -V _out is applied. Therefore, V _in (=
As V _G ) increases, V _out also increases, and as a result, V _in −
V _out also becomes large.

From the above, it can be concluded as follows. In the voltage transfer circuit using the n-channel MISFET,
(1) In order to set the transfer efficiency to 1, a gate voltage higher than the input voltage by the threshold value is required. (2) When the gate voltage is made equal to the input voltage, the output voltage becomes a value smaller than the input voltage by the threshold value (hereinafter, this phenomenon may be referred to as “threshold drop”). Exists. Moreover, during the transfer operation of this circuit, it is equivalent to M
Since the ISFET is in the state where the substrate bias is applied, the threshold value becomes large especially when the input voltage is large, and these problems become remarkable.

In order to solve the above problem, it is understood that the threshold value when the substrate bias is applied is small. For this reason, particularly in a high-voltage (up to 20 V) transfer circuit, the insulation film thickness of the MISFET is reduced, and the depletion type MISFET is used instead of the enhancement type.
The method of using is conventionally adopted. The effectiveness of these methods can be easily understood from the substrate bias effect shown in FIG. However, in practice, each method has drawbacks as described below.

[0007]

That is, in the method of reducing the thickness of the gate insulating film, since the input voltage is directly applied to both ends of the gate insulating film during non-transfer, the higher the transfer voltage is, the higher the film thickness is. Can not be thinned and the effect does not improve so much. As a specific numerical example, when the input voltage of 20 V is transferred, the gate insulating film has a thickness of about 60.
nm is required, so even if 20 V is applied to the gate, it is ~ 15
Only V is transferred. (In order to set the transfer efficiency to 1, a gate voltage of ~ 26V may be applied.
It is not a very effective method because it requires consideration of the transistor surface breakdown voltage and drain breakdown voltage. Further, the method using the depletion type transistor has a drawback that an output voltage is generated even during non-transfer and the cutoff characteristic is not good. For example, if the input voltage is 2
When 0V and 0V are applied to the gate voltage, ~ 4V is output. An object of the present invention is to reduce the "threshold drop" of the output voltage, which has a good cut-off characteristic and has been a problem in the conventional high voltage transfer circuit.

[0008]

A voltage transfer circuit according to the present invention comprises a plurality of MISFETs whose gate electrodes are electrically short-circuited.
Are connected in series, only the threshold value of the MISFET closest to the input side is of depletion type, and the gate insulating film is thicker than the other MISFETs.

[0009]

According to the present invention, it is possible to obtain a voltage transfer circuit having a good cut-off characteristic and having a smaller "threshold drop" when a high voltage is transferred as compared with the conventional example.

[0010]

Embodiments of the present invention will be described with reference to the drawings.
1 and 2 are a plan pattern view (FIG. 1A), a cross-sectional view (FIG. 1B), and an equivalent circuit diagram thereof, respectively, of an embodiment using an n-channel MISFET. T in the figure
Reference numeral 1 is a depletion type MISFET, and T2 is an enhancement type MISFET. When the gate insulating film thicknesses of T1 and T2 are d ₁ and d ₂ , respectively, d ₁ ≧ d ₂ is satisfied. Further, when the gate lengths of T1 and T2 are L ₁ and L ₂ , respectively, L ₁ ≧ L ₂ holds. The reason for lengthening L ₁ is to prevent punch through of T 1.
In the figure, reference numeral 10 is a gate terminal, 11 is an input terminal, 1
2 indicates an output terminal.

First, the operation during non-transfer will be described.
FIG. 3A shows the applied voltage during non-transfer. Since T1 is a depletion type, even if the gate voltage is 0 V, it is not cut off and the potential at the point A rises. However, since T2 is an enhancement type, if the gate voltage is 0, no voltage is transferred to the output terminal. The potential V _A at this time point A, if designed to "threshold is greater than -V _H when -V _H is applied as the substrate bias" to T1, when the gate voltage is 0V Since it operates in the saturation region, V _A <
It becomes V _H. Therefore, since the voltage applied to the gate insulating film thickness of T2 can be made smaller than V _H , d ₁ > d ₂
However, no dielectric breakdown occurs. (Since V _H is applied to the gate insulating film of T1, the same thickness as the conventional example is used.)

Next, the operation during voltage transfer will be described.
FIG. 3B shows an applied voltage during voltage transfer. If designed T1 a "threshold when -V _H is applied as the substrate bias becomes negative" way, V _H is transferred without "threshold voltage drop" to point A .. Next, considering the threshold value of T2, since the gate insulating film of T2 is thin, it is not easily affected by the substrate bias (see FIG. 11), and the “threshold drop” of the output voltage should be reduced as compared with the conventional example. You can

Here, a numerical sequence for transferring 20 V will be described. The gate insulating film thickness and the gate length of T ₁ and T ₂ are d ₁ = 60 nm, d ₂ = 20 nm, L ₁ = 3 μm, and
L ₂ = 1.4 μm. The threshold value of T1 is designed to be -5V when no substrate bias is applied, and -1V when a substrate bias of -20V is applied. The threshold value of T2 is designed to be ˜0.5 V when the substrate bias is not applied, and ˜2 V when the -20 V substrate bias is applied. (When d ₂ = 60 nm as in the conventional case, the threshold value at a substrate bias of −20 V is −5 V.) Therefore, when this circuit is used, the output is −18 V.
V transferred. In the conventional example described above, the output is 15V.
Considering that it can only be transferred, "threshold drop" is ~ 3
V has been improved. Also, point A is ~ 4 when not transferred.
Although it becomes V, it is cut off by T2, so that the cutoff characteristic is also good. At this time, the gate insulating film of T2 has about 4
Since only V is applied, there is no problem in terms of withstand voltage even when d ₂ = 20 nm.

The present invention is not limited to the above embodiments, but various modifications can be made. For example, as the gate insulating film of the second-stage transistor, a material having a large dielectric constant may be used instead of reducing the thickness. Further, by changing the number of stages of the transistors according to the transmission voltage, it is possible to apply to the transfer of higher voltage. Furthermore, a circuit using a p-channel transistor is also conceivable.

In the present invention, in addition to the embodiment of the preceding paragraph,
Several variants are possible and will be briefly described below. The operation and the operating principle in any of the examples are the same as those in the above-described embodiments, and therefore will be omitted.

FIG. 4 shows a plane pattern view (FIG. 4A) and a sectional view (FIG. 4B) of the second embodiment.
In the figure, T3 is a depletion type MISFET and T4 is an enhancement type MISFET. In the figure, L3, L4, d3,
d4 indicates the respective gate length and gate insulating film thickness, and L3 ≥L4 and d3 ≥d4 are satisfied, as in the first embodiment (the embodiment in the preceding paragraph). The feature of this embodiment is that the gates of T3 and T4 are formed by electrode materials of different layers, that is, the first layer electrode material gate 13 and the second layer electrode material gate 14, and they are short-circuited at the gate terminal. It is a point. The operation is similar to the previous example.

FIG. 5 shows a plan view pattern (FIG. 5A) and a sectional view (FIG. 5B) of the third embodiment.
This example is different from the above two examples in that it is composed of one transistor. T in the figure
Reference numerals 5 and T6 denote regions in the channel, which are formed by the first layer electrode material 15 and the second layer electrode material 16, respectively, and both are short-circuited by the gate terminal at the contact portion on the field insulating film 17. Assume that the threshold value of the T5 region is negative and the threshold value of the T6 region is positive, and the length and the gate insulating film thickness of each region are L ₅ , L ₆ , d ₅ , and d.
_{When set to 6} , L ₅ ≧ L ₆ and d ₅ ≧ d ₆ are established. The operation is similar to the above two examples.

FIG. 6 shows a plan view pattern (FIG. 6A) and a sectional view (FIG. 6B) of the fourth embodiment.
In the figure, T7 and T8 indicate regions in the channel. T7
It is assumed that the threshold value of the region is negative and the threshold value of the T8 region is positive, and the length and gate insulating film thickness of each region are L ₇ ,
When L ₈ , d ₇ , and d ₈ are set, L ₇ ≧ L ₈ , d ₇ ≧ d ₈
Has been established. The operation is similar to the above three examples.

[0019]

As described above, according to the present invention,
The cutoff characteristic is good, and the “threshold drop” when a high voltage is transferred can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram relating to FIG.

FIG. 3 is a circuit diagram showing a potential relationship during voltage non-inversion (a) and during voltage transfer (b) in the circuit of FIG.

FIG. 4 is a plane pattern and a sectional view showing a second embodiment of the present invention.

FIG. 5 is a plane pattern and a cross-sectional view showing a third embodiment of the present invention.

FIG. 6 is a plan view and a sectional view showing a fourth embodiment of the present invention.

7A and 7B are a plane pattern and a cross-sectional view thereof for explaining a conventional example.

FIG. 8 is a circuit diagram relating to FIG.

9 is a characteristic diagram showing V _out as a function of V _G −V _in when V _in is a parameter _in the circuit shown in FIG. 8.

10 is an explanatory diagram showing a relationship between a substrate bias and a threshold value of the MISFET shown in FIG.

FIG. 11: MISF with different gate insulating film thickness and operation type
FIG. 6 is a characteristic diagram showing a relationship between a substrate bias of ET and a threshold value.

[Explanation of symbols]

10 gate terminal 11 input terminal 12 output terminal T1 depletion type MISFET T2 enhancement type MISFET d ₁ , d ₂ gate insulating film thickness

Claims (5)

[Claims] 1. In an insulated gate field effect transistor (MISFET) type semiconductor device for transferring a drain potential to a source electrode, a plurality of MISFETs in which respective gate electrodes are electrically short-circuited are connected in series.
Only the ISFET is a depletion type in which a current flows when a gate voltage is not applied, and the gate insulating film of the MISFET is thicker than the gate insulating films of other MISFETs. circuit. 2. The gate length of at least one MISFET among a plurality of transistors according to claim 1,
A voltage transfer circuit having a gate length different from that of other transistors. 3. The voltage transfer circuit according to claim 2, wherein the transistor having the longest gate length among the transistors is present on the most input side of the series connection. 4. An M for transferring a drain potential to a source electrode
A voltage transfer circuit characterized in that in an ISFET type semiconductor device, only a region near a drain of a channel is a depletion type, and a gate insulating film in that region is thicker than other portions. 5. The voltage transfer circuit according to claim 5, wherein the gate of the MISFET is formed of a plurality of layers of different electrode materials.