JPS6054791B2 - Composite field effect transistor - Google Patents
Composite field effect transistorInfo
- Publication number
- JPS6054791B2 JPS6054791B2 JP52132730A JP13273077A JPS6054791B2 JP S6054791 B2 JPS6054791 B2 JP S6054791B2 JP 52132730 A JP52132730 A JP 52132730A JP 13273077 A JP13273077 A JP 13273077A JP S6054791 B2 JPS6054791 B2 JP S6054791B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- conductivity type
- type region
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title claims description 19
- 239000002131 composite material Substances 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000011810 insulating material Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 本発明は電界効果トランジスタに関するものである。[Detailed description of the invention] The present invention relates to field effect transistors.
従来の絶縁ゲート型電界効果トランジスタ（ＭＯＳＦＥ
Ｔ）の一例を第１図に示す。Conventional insulated gate field effect transistor (MOSFE)
An example of T) is shown in FIG.
Ｐ型半導体基板５１上のＮ型エピタキシャル層５２にＰ
型領域５４とＮ゛型領域５７とを有し、さらにＰ型領域
５４中にはＮ゛型領域５６を有している。Ｎ゛型領域５
６とＮ型エピタキシャル層５２とにかけてＰ型領域５４
上に絶縁膜５３とゲート電極５９とを被着している。こ
れはＮ゛型領域を５７をドレイン、Ｎ＋型領域５６をソ
ース、ゲート電極５９を第１ゲート、Ｐ型領域５４とＰ
型半導体基板５１を第２ゲートとする絶縁ゲート型電界
効果トランジスタ（以下ＭＯＳＥＦＴという）で、チャ
ンネル領域とソース領域を同一の拡散窓で拡散出来るた
め非常にチャンネル長が短くしたがつて相互コンダクタ
ンス胛の大きな特性のＭＯＳＥＦＴを作ることが可能で
ある。P is applied to the N-type epitaxial layer 52 on the P-type semiconductor substrate 51.
It has a type region 54 and an N-type region 57, and further has an N-type region 56 in the P-type region 54. N-type region 5
6 and the N-type epitaxial layer 52, the P-type region 54
An insulating film 53 and a gate electrode 59 are deposited thereon. This includes an N type region 57 as a drain, an N+ type region 56 as a source, a gate electrode 59 as a first gate, a P type region 54 and a P
This is an insulated gate field effect transistor (hereinafter referred to as MOSEFT) that uses the type semiconductor substrate 51 as the second gate.Since the channel region and the source region can be diffused in the same diffusion window, the channel length is extremely short and the transconductance band is short. It is possible to create a MOSEFT with large characteristics.
しカルチャンネル長をあまり短くすると耐圧が低くなる
ためＮ型エピタキシャル層５２の不純物濃度を下げてこ
のＮ型領域へ・の空乏層の伸びを大きくしてやり、ドレ
イン・ソース間耐圧を高くするようにしなければならな
い。しカルＮ型エピタキシャル層５２の不純物濃度をあ
まり下げるとドレインの抵抗が大きくなりオン抵抗が増
加し特性上あまり好ましくない。一方第２図は接合型電
界効果トランジスタ（以下、Ｊ−ＦＥＴという）の一例
を示したものである。これはＰ型半導体基板６１上のＮ
型エピタキシャル層６２にドレイン領域６７とソース領
域となるＮ゛型領域６６とこれらの間に存し第１ゲート
領域となるＰ型領域６４とを有し、Ｐ型半導体基板６１
は第２ゲート領域として用いたものである。このような
構造のＪ−ＦＥＴの場合上記ＭＯＳ、ＥＦＴに比べてチ
ャンネル長を短くすることは出来ないためあまり相互コ
ンダクタンス胛を大きくすることはできないが、空乏層
をＮ型エピタキシャル層６２（チャンネル領域）とＰ型
領域６４（第１ゲート領域）並びにＰ型半導体基板６１
（第２ゲート領域）の両方に伸びるようにしてやればＮ
型エピタキシャル層６２の不純物濃度を極端に下げなく
てもドレイン・ソース間耐圧を十分に大きくすることが
可能であり、低オン抵抗、高耐圧を実現出来る。本発明
は絶縁ゲート型電界効果トランジスタ（ＭＯＳＥＦＴ）
と接合型電界効果トランジスタ（Ｊ−ＦＥＴ）を複合化
し、ドレイン・ソース間のオン抵抗ＲＤｓ（０Ｎ）を大
きくせずに、大きな相互コンダクタンスＧｍと高いドレ
イン●ソース間耐旺追Ｖ。However, if the total channel length is too short, the breakdown voltage will decrease, so it is necessary to lower the impurity concentration of the N-type epitaxial layer 52 and increase the extension of the depletion layer into this N-type region, thereby increasing the drain-source breakdown voltage. Must be. If the impurity concentration of the N-type epitaxial layer 52 is lowered too much, the resistance of the drain increases and the on-resistance increases, which is not very desirable in terms of characteristics. On the other hand, FIG. 2 shows an example of a junction field effect transistor (hereinafter referred to as J-FET). This is the N on the P-type semiconductor substrate 61.
The type epitaxial layer 62 has a drain region 67, an N-type region 66 which becomes a source region, and a P-type region 64 which exists between these and becomes a first gate region, and a P-type semiconductor substrate 61.
is used as the second gate region. In the case of a J-FET with such a structure, the channel length cannot be made shorter than that of the above-mentioned MOS and EFT, so the mutual conductance cannot be made too large. ), P-type region 64 (first gate region), and P-type semiconductor substrate 61
(Second gate region) If you make it extend to both sides, N
It is possible to sufficiently increase the drain-source breakdown voltage without extremely lowering the impurity concentration of the type epitaxial layer 62, and low on-resistance and high breakdown voltage can be achieved. The present invention is an insulated gate field effect transistor (MOSEFT)
By combining a junction field effect transistor (J-FET) and a junction field effect transistor (J-FET), it has a large mutual conductance Gm and high drain-source resistance V without increasing the on-resistance RDs (0N) between the drain and source.
，を同時に満足し、さらにまた帰還容量Ｃｒｓｓ及び出
力容量ＣＯｓｓをも小さくすることを目的としたもので
ある。このことにより電界効果トランジスタは信頼度が
高まり高耐圧大電力化が可能となり、さらに高周波高出
力用途としてすぐれた性能のものが得られる。次に図面
を参照して本発明をより詳細に説明すする。, and also to reduce the feedback capacitance Crss and the output capacitance COss. This increases the reliability of field-effect transistors, enables them to withstand high voltages and increase power consumption, and provides excellent performance for high-frequency, high-output applications. Next, the present invention will be explained in more detail with reference to the drawings.
第３図は本発明の基本的実施例を示したもので、Ｐ型半
導体基板７１のＮ型エピタキシャル層７２にＮ＋型領域
７７とＰ型領域７４とを有し、このＰ型領域７４内には
さらにＮ＋型領域７６が形成されている。FIG. 3 shows a basic embodiment of the present invention, in which an N type epitaxial layer 72 of a P type semiconductor substrate 71 has an N+ type region 77 and a P type region 74. Furthermore, an N+ type region 76 is formed.
これらＮ＋型領域７６，７７およびＰ型領域７４は環状
の同心円を形成している。Ｎ＋型領域７６で囲まれる部
分上には絶縁膜７３を介してゲート電極７９が形成され
ている。この半導体装置は等価的に第４図の如く動作す
る。すなわちＮ＋型領域７７をドレインＤ，Ｐ型領域７
４をゲートＧ２絶縁膜７３下のＮ型エピタキシャル層７
２の表面をソースとする接合型電界効果トランジスタは
第４図のＦＥＴ−２を構成しており、さらにＮ＋型領域
７６をソースＳ、電極７９を第１ゲートＧ１、絶縁膜７
３下のＮ型エピタキシャル層７２の表面をドレインとす
る絶縁ゲート型電界効果トランジスタは第４図のＦＥＴ
一１を構成しており、これらＦＥＴ−１とＦＥＴ−２と
は絶縁膜７３下のエピタキシャル層７２の表面．で直列
に接続された構造となつている。このような複合型の電
界効果トランジスタではＦＥＴ−１のドレイン●ソース
間にかかる電圧の最高値はＦＥＴ−２のピンチオフ電圧
に等しいので、ＦＥＴ−２のピンチオフ電圧をＦＥＴ−
１のドーレイン・ソース間耐圧より低くなるようにし、
ＦＥＴ−２のドレイン●ソース間耐圧を十分に大きくし
てやれば、全体の耐圧を大きく出来る。These N+ type regions 76, 77 and P type region 74 form annular concentric circles. A gate electrode 79 is formed on the portion surrounded by the N+ type region 76 with an insulating film 73 interposed therebetween. This semiconductor device operates equivalently as shown in FIG. That is, the N+ type region 77 is used as the drain D, and the P type region 7 is used as the drain D.
4 is the N-type epitaxial layer 7 under the gate G2 insulating film 73
A junction field effect transistor whose source is the surface of the insulating film 7 constitutes the FET-2 shown in FIG.
The insulated gate field effect transistor whose drain is the surface of the N-type epitaxial layer 72 below 3 is the FET shown in FIG.
These FET-1 and FET-2 form the surface of the epitaxial layer 72 under the insulating film 73. The structure is connected in series. In such a composite field effect transistor, the maximum value of the voltage applied between the drain and source of FET-1 is equal to the pinch-off voltage of FET-2, so the pinch-off voltage of FET-2 is
The drain-source breakdown voltage is set to be lower than the drain-source breakdown voltage of 1.
If the drain-source breakdown voltage of FET-2 is made sufficiently large, the overall breakdown voltage can be increased.
ただしオン抵抗を大きくしないためにＦＥＴ−２のオン
抵抗はＦＥＴ−１のオン抵抗よりも十分に小さくする必
要がある。したがつて上記条件を満足するように設計し
てやればＦＥＴ−１で決まる胛と低イオン抵抗でＦＥＴ
−１の耐圧とＦＥＴ−２の耐圧との和にほぼ等しい耐圧
をもつた高耐圧電界効果トランジスタを作ることが可能
である。また構造上ドレインをゲート１間の容卜連Ｒｓ
ｓとドレインとソース間容量ＣＯｓｓを小さくすること
も可能である。本発明の一具体的実施例を第５図によつ
て説明する。However, in order not to increase the on-resistance, the on-resistance of FET-2 must be made sufficiently smaller than the on-resistance of FET-1. Therefore, if the design satisfies the above conditions, it will be possible to create an FET with low ionic resistance and the same value determined by FET-1.
It is possible to produce a high-voltage field effect transistor having a breakdown voltage approximately equal to the sum of the breakdown voltage of -1 and the breakdown voltage of FET-2. Also, due to the structure, the drain is connected between gate 1 and Rs.
It is also possible to reduce s and the drain-source capacitance COss. A specific embodiment of the present invention will be described with reference to FIG.
第５Ａ図はＰ型半導体基板の上にＮ型半導体領域を有す
るエピタキシャル・ウェハーであり、基板１はＰ型不純
物基板（例えば１０１４〜１０１６ａｔ０ｍｓ／ｃ！ｌ
）、領域２はＮ型エピタキシャル層（例えば１０１４〜
１０１６ａｔ０ｍｓ／Ｃｒｌ）、厚さ数μｍ〜１０数μ
ｍ程度）である。FIG. 5A shows an epitaxial wafer having an N-type semiconductor region on a P-type semiconductor substrate, and the substrate 1 is a P-type impurity substrate (for example, 1014 to 1016 at0 ms/c!l).
), region 2 is an N-type epitaxial layer (e.g. 1014~
1016at0ms/Crl), thickness of several μm to several tens of μm
m).
このエピタキシャルウェハー上に不純物拡散に対するマ
スク層３（例えば熱酸化膜等）を形成する。次に第５Ｂ
図に示すようにゲート２のＰ型不純物を拡散するための
窓を開けＰ型領域４を形成する。A mask layer 3 (for example, a thermal oxide film, etc.) for impurity diffusion is formed on this epitaxial wafer. Next, 5th B
As shown in the figure, a window for diffusing the P-type impurity of the gate 2 is opened to form a P-type region 4.
この場合ゲート２の拡散はＦＥＴ−１の耐圧よりＦＥＴ
−２のピンチオフ電圧が低く、ＦＥＴ−１のオン抵抗よ
りもＦＥＴ−２のオン抵抗が低くなるようにする必要が
ある。その後、マスク層（例えば熱酸化膜等）を全面に
形成した後、第５Ｃ図に示すようにＰ型不純物拡散層４
の部分と一方の部分は重なるが他方はＰ型不純物層４の
領域から十分離して不純物層４の影響を受けないような
拡散窓を開け第２のＰ型不純物層５を形成する。In this case, the diffusion of gate 2 is higher than the withstand voltage of FET-1.
It is necessary to ensure that the pinch-off voltage of FET-2 is low and that the on-resistance of FET-2 is lower than that of FET-1. Thereafter, after forming a mask layer (for example, a thermal oxide film, etc.) on the entire surface, a P-type impurity diffusion layer 4 is formed as shown in FIG. 5C.
A second P-type impurity layer 5 is formed by opening a diffusion window in which one portion overlaps with the other, but is sufficiently separated from the region of the P-type impurity layer 4 so as not to be affected by the impurity layer 4.
さらに第５Ｄ図に示すように領域７を拡散するための窓
を開けＮ型不純物領域６と領域７を同時に形成する。Furthermore, as shown in FIG. 5D, a window for diffusing region 7 is opened and N-type impurity region 6 and region 7 are formed simultaneously.
ここで領域６がソース、領域７がドレインとなり、領域
５と領域６の拡散の広がりの差がＦＥＴ−１のチャンネ
ル長となる。しかるのち、第５Ｅ図に示すように所望の
厚さの絶縁物層８を領域２と６の間の領域５の表面部分
の上に形成し、さらに電極９（ゲート１）、電極１０（
ソース７）、電極１１（ドレイン）、電極１２（ゲート
２″）を形成し全工程を終了する。Here, region 6 becomes the source, region 7 becomes the drain, and the difference in diffusion spread between regions 5 and 6 becomes the channel length of FET-1. Thereafter, as shown in FIG. 5E, an insulating layer 8 of a desired thickness is formed on the surface portion of the region 5 between the regions 2 and 6, and an electrode 9 (gate 1) and an electrode 10 (
A source 7), an electrode 11 (drain), and an electrode 12 (gate 2'') are formed, and the entire process is completed.
本実施例は前号ＥＴ−２のゲート２に相当する部分をソ
ース電極と短絡した場合について述べたが、独立に引き
出しゲート２″と共にＦＥＴのピンチフオ電圧をコント
ロールすることが出来ることは明らかである。第６Ａ図
は第５Ａ図と同様Ｐ型半導体基板２１の上にＮ型エピタ
キシャル層２２があるエピタキシャル・ウェハーであり
、基板２１はＰ型不純物基板（例えば１０１４〜１０１
６ａｔ０ｍｓ／Ｃｌｌ）、エピタキシャル層２２はＮ型
エピタキシャル層（例えば１０１４〜１０１６ａｔ０ｍ
ｓ／ｄ１厚さ数μｍ〜１０数μｍ程度）である。In this example, the case where the part corresponding to the gate 2 of ET-2 in the previous issue was short-circuited with the source electrode was described, but it is clear that the pinch-off voltage of the FET can be controlled independently in conjunction with the extraction gate 2''. 6A is an epitaxial wafer having an N-type epitaxial layer 22 on a P-type semiconductor substrate 21, similar to FIG. 5A, and the substrate 21 is a P-type impurity substrate (for example, 1014 to 101
6at0ms/Cll), and the epitaxial layer 22 is an N-type epitaxial layer (for example, 1014 to 1016at0m
s/d1 thickness of several μm to about 10-odd μm).
このＮエピタキシャルウェハー上に不純物拡散に対する
マスク層２３（例えば熱酸化膜等）を形成する。次に第
６Ｂ図に示すように部分的に開孔し、更にゲート２（領
域２４）を形成するための窓以外の窓にマスク層２３″
を形成する。A mask layer 23 (for example, a thermal oxide film, etc.) for impurity diffusion is formed on this N epitaxial wafer. Next, as shown in FIG. 6B, holes are partially opened, and a mask layer 23'' is formed on the windows other than those for forming gate 2 (region 24).
form.
マスク層２３とは異なるものを用い、マスク層２３″を
選択的に除去できるもの（例えばフォトレジスタ材、Ｓ
ｉ３Ｎ４等）を用いる。しかるのち第６Ｃ図のようにＰ
型領域２４を形成する。A material different from the mask layer 23 is used to selectively remove the mask layer 23'' (for example, a photoresist material, S
i3N4 etc.). Then, as shown in Figure 6C, P
A mold region 24 is formed.
これも第５Ｂ図と同様ＦＥＴ−１の耐圧よりＦＥＴ−２
のピンチオフ電圧が低く、ＦＥＴ一１のオン抵抗よりも
ＦＥＴ−２のオン抵抗が低くなるように領域２４を形成
する。その後、マスク層２３″を除去し、第６Ｄ図のご
とくＮ型不純物層２６，２『，２７を形成する。This is also similar to Figure 5B, since the withstand voltage of FET-1 is
The region 24 is formed such that the pinch-off voltage of FET-2 is low and the on-resistance of FET-2 is lower than that of FET-1. Thereafter, the mask layer 23'' is removed, and N-type impurity layers 26, 2'', 27 are formed as shown in FIG. 6D.
この場合領域２６がソース領域２７がドレインに相当し
、領域２６と２『の間の領域２４の間隔がＦＥＴ−１の
チャンネル長に相当する。このように領域２６″をもう
けることによりＦＥＴ−２のピンチオフ電圧とＦＥＴ−
１のチャンネル長を独立に決めることができる。最後に
第６Ｅ図のように所望の厚さの絶縁物層２８を領域２６
と２６″の間の領域２４の表面部分の上に形成し、さら
に電極２９（ゲート１）、電極３０（ソース）、電極３
１（ドレイン）、電極３２（ゲート２０を形成し全工程
を終了する。In this case, the region 26 corresponds to the source region 27 and the drain, and the distance between the regions 26 and 2' corresponds to the channel length of the FET-1. By providing the region 26'' in this way, the pinch-off voltage of FET-2 and the FET-
1 channel length can be determined independently. Finally, as shown in FIG.
electrode 29 (gate 1), electrode 30 (source), electrode 3
1 (drain) and electrode 32 (gate 20) are formed to complete the entire process.
本具体的実施例は第５図の場合と同様前記ＦＥＴ一２の
ゲート２に相当する部分をソース電極と短絡した場合に
ついて述べているが、独立に引き出しゲート２″と共に
ＦＥＴ−２のピンチオア電圧をコントロールできること
は明らかである。第７図は更に他の具体的実施例でＦＥ
Ｔ−２のゲート２とゲート２″を拡散層によつて内部で
短ｊ絡した場合である。This specific example describes the case where the portion corresponding to the gate 2 of the FET-2 is shorted to the source electrode as in the case of FIG. 5, but the pinch-or voltage of the FET-2 is It is clear that it is possible to control the FE.
This is a case where gate 2 and gate 2'' of T-2 are internally shorted by a diffusion layer.
Ｐ型半導体基板４１上にはＮ型エピタキシャル層４２を
有し、このＮ型エピタキシャル層４２にこのエピタキシ
ャル層４２を四角く囲むように半導体基板４１に達する
Ｐ＋型領域４０を形成している。またこのＮ型エピタキ
シャル層にはＮ＋型領域４６とそれぞれ平行に形成され
ているこれらＮ＋型領域４６，４７とＰ型領域４４は対
称的に左側部分にも形成されている。この２つのＮ＋型
領域４６を連結するように絶縁物４３とゲート電極４９
とが形成されている。この具体的実施例は２つのＮ＋型
領域４７がドレインＤｌ２つのＮ＋型領域がソースＳ１
ゲート電極４９が第１ゲートＧ１、２つのＰ型領域４４
とこれにＰ＋型領域を介して接続されるＰ型半導体基板
を第２ゲートＧ２とする複合型電界効果トランジスタと
して動作する。以上具体例をＮチャンネル型の場合につ
いて述べたが、Ｐチャンネル型の場合にも全く適用可能
であることは明らかである。An N-type epitaxial layer 42 is provided on a P-type semiconductor substrate 41, and a P+-type region 40 reaching the semiconductor substrate 41 is formed in this N-type epitaxial layer 42 so as to squarely surround this epitaxial layer 42. Further, in this N-type epitaxial layer, these N+-type regions 46 and 47, which are formed parallel to the N+-type region 46, and the P-type region 44 are also formed symmetrically on the left side. An insulator 43 and a gate electrode 49 are connected to connect these two N+ type regions 46.
is formed. In this specific embodiment, two N+ type regions 47 are drain D1 and two N+ type regions 47 are source S1.
The gate electrode 49 is the first gate G1, and the two P-type regions 44
The second gate G2 operates as a composite field effect transistor having a P type semiconductor substrate connected thereto via a P+ type region as a second gate G2. Although the specific example has been described above for an N-channel type, it is clear that it is completely applicable to a P-channel type as well.
第１図は従来の絶縁ゲート型電界効果トランジスタの構
造の一例を示す断面図である。
第２図は従来の接合型電界効果トランジスタの構造の一
例を示す断面図である。第３図は本発明の一実施例を示
す断面図である。第４図は本発明の一実施例の等価回路
図である。第５図Ａ上は本発明の一具体的実施例を製造
工程順に示す断面図である。第６図Ａ上本発明の他の具
体的実施例を製造工程順に示す断面図である。第７図は
本発明の更に他の具体的実施例を示す図である。Ｎ＋・
・・・・・Ｎ型高濃度不純物領域、Ｎ・・・・・・Ｎ型
不純物領域、Ｐ・・・・・・Ｐ型不純物領域、Ｓ・・・
・・・ソース、Ｄ・・・・・・ドレイン、Ｇ１・・・・
・・ゲート１、Ｇ２・・・・・・ゲート２、Ｇ２″・・
・・・・ゲート２″、１，２１，４１，５１，６１，７
１・・・・・・Ｐ型半導体基板、２，２２，４２，５２
，６２，７２・・・・・・Ｎ型エピタキシャル層、３，
２３，４３，５３，６３，７３・・・・・・酸化膜、４
，２４，４４，５４，６４，７４・・・・・・Ｐ型領域
、６，２６，４６，５６，６６，７６・・・・・・Ｎ＋
型領域、７，２７，４７，５７，６７，７７・・・・・
・Ｎ＋型領域、９，２９，４９，５９，７９・・・・・
・ゲート電極。FIG. 1 is a cross-sectional view showing an example of the structure of a conventional insulated gate field effect transistor. FIG. 2 is a sectional view showing an example of the structure of a conventional junction field effect transistor. FIG. 3 is a sectional view showing one embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of an embodiment of the present invention. The upper part of FIG. 5A is a sectional view showing a specific embodiment of the present invention in the order of manufacturing steps. FIG. 6A is a sectional view showing another specific embodiment of the present invention in the order of manufacturing steps; FIG. 7 is a diagram showing still another specific embodiment of the present invention. N+・
...N-type high concentration impurity region, N...N-type impurity region, P...P-type impurity region, S...
...Source, D...Drain, G1...
...Gate 1, G2...Gate 2, G2''...
...Gate 2'', 1, 21, 41, 51, 61, 7
1...P-type semiconductor substrate, 2, 22, 42, 52
, 62, 72...N-type epitaxial layer, 3,
23, 43, 53, 63, 73...Oxide film, 4
, 24, 44, 54, 64, 74...P type region, 6, 26, 46, 56, 66, 76...N+
Type area, 7, 27, 47, 57, 67, 77...
・N+ type region, 9, 29, 49, 59, 79...
・Gate electrode.
Claims (1)
を有し、該第１の反対導電型領域内に第１の一導電型領
域を有し、該第１の一導電型領域内に第２の反対導電型
領域を有し、さらに前記第１の反対導電型領域と前記第
２の反対導電型領域との間にかさまれた前記第１の導電
型領域の表面上に絶縁物層と該絶縁物層上に導電性電極
を有し、前記一導電型半導体基板と前記第１の一導電型
領域をゲートとしかつ前記一導電型半導体基板と前記第
１の一導電型領域の間の前記第１の反対導電型領域をチ
ャンネルとする接合型電界効果トランジスタと、前記第
２の反対導電型領域をソースとし、前記導電性電極をゲ
ートとしかつ前記第１の反対導電型領域をドレインとす
る絶縁ゲート型電界効果トランジスタとを直列接続した
構造の複合型電界効果トランジスタ。1 having a first opposite conductivity type region on the upper part of one conductivity type semiconductor substrate, having a first one conductivity type region within the first opposite conductivity type region, and having a first one conductivity type region within the first one conductivity type region; a second opposite conductivity type region, and further comprising an insulating material on the surface of the first conductivity type region interposed between the first opposite conductivity type region and the second opposite conductivity type region. layer and a conductive electrode on the insulating layer, the one-conductivity type semiconductor substrate and the first one-conductivity type region are used as gates, and the one-conductivity type semiconductor substrate and the first one-conductivity type region are connected to each other. a junction field effect transistor having the first opposite conductivity type region between as a channel, the second opposite conductivity type region as a source, the conductive electrode as a gate, and the first opposite conductivity type region as a gate; A composite field effect transistor with a structure in which an insulated gate field effect transistor serving as a drain is connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52132730A JPS6054791B2 (en) | 1977-11-04 | 1977-11-04 | Composite field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52132730A JPS6054791B2 (en) | 1977-11-04 | 1977-11-04 | Composite field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5466078A JPS5466078A (en) | 1979-05-28 |
| JPS6054791B2 true JPS6054791B2 (en) | 1985-12-02 |
Family
ID=15088241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52132730A Expired JPS6054791B2 (en) | 1977-11-04 | 1977-11-04 | Composite field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054791B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025659U (en) * | 1988-06-23 | 1990-01-16 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142731A (en) * | 1993-05-26 | 1995-06-02 | Texas Instr Inc <Ti> | Power device and method for forming it |
| DE19902749C2 (en) * | 1999-01-25 | 2002-02-07 | Infineon Technologies Ag | Power transistor arrangement with high dielectric strength |
-
1977
- 1977-11-04 JP JP52132730A patent/JPS6054791B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025659U (en) * | 1988-06-23 | 1990-01-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5466078A (en) | 1979-05-28 |
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