JP2656731B2 - Composite semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device,
In particular, a lateral MOS which can realize a high withstand voltage and a low threshold voltage and is suitable for effectively controlling an on-voltage and an on-current.
Semiconductor device.

[0002]

2. Description of the Related Art A conventional insulated gate type turn-off thyristor is shown in FIG.

[0003] This device comprises an n-based semiconductor substrate 1.
(E.g., an n-type silicon substrate) formed on one main surface of the thyristor and serving as an anode (p emitter) 2, a second region formed on the other main surface and serving as a p-base of the thyristor, and a p-base region 3, a region 6 formed by selective diffusion and serving as an n + cathode of a thyristor and a source of a short-circuit MOS transistor portion, and M
It is composed of a region 7 serving as a drain of the OS transistor portion.

Further, a thin gate insulating film 8 (for example, an SiO ₂ film) formed over the regions 6 and 7 and over the regions 6 and 7 and the p base region 3, and a gate electrode 12 on the thin gate insulating film 8. (P gate G), the cathode electrode 14 formed in the region 6, formed across the region 7 and the region 3,
P _B electrode 13 for short-circuiting both of them, and are provided with an anode electrode 15 formed in the region 2.

[0005] To ON the insulated gate turn-off thyristor having such a composite, injecting electrons from the p base region 3 and the P _B electrode 13 to a positive potential to the n + cathode region 6.

When the thyristor in the ON state is turned off, the gate electrode 12 is switched from a negative potential to a positive potential, the p base region 3 in contact with the gate insulating layer 8 is inverted to the n type, and the p base 3 and the cathode are turned off. 6 is electrically short-circuited via the short-circuit electrode 13 and the drain 7 and the inversion layer.

[0007] This type of thyristor device is described in [IEDM] (International ELECTRON DEVICES).
Meeting), pages 158 to 161 of 1985.

[0008]

The problem to be solved by the present invention is as follows.
The control of the voltage and the current by the insulating gate as described above is effectively performed in the lateral MOS thyristor.

At this time, it is important that the characteristics of the MOSFET section can be largely controlled by the gate applied voltage.

However, even if an attempt is made to reduce the gate threshold voltage by reducing the thickness of the gate insulating film below the gate, in order to secure a predetermined gate dielectric breakdown voltage,
There is a limitation that the thickness cannot be reduced below a certain value.

Another means for lowering the threshold voltage is a p base region (M) adjacent to the insulating film 8 below the gate.
This is to lower the impurity concentration (hereinafter referred to as surface concentration) on the surface of the OS transistor channel region 3). However, when the impurity concentration is reduced, the p base is liable to punch through, and the forward bias withstand voltage is reduced.

To avoid the punch-through, it is conceivable to increase the junction depth. However, if the junction depth is increased, the junction area inevitably occupies a large area, and the degree of circuit integration decreases. This raises another problem.

The present invention is intended to solve the above problems without adversely affecting other characteristics such as withstand voltage and reducing the degree of integration.

[0014]

In order to achieve the above object, in a semiconductor device according to the present invention, at least a second conductive type exposed to one main surface of a semiconductor substrate of a first conductive type and independent of and opposed to each other. A first semiconductor region and a second semiconductor region, and a third conductive type third semiconductor region provided in the second semiconductor region.
A lateral thyristor composed of a semiconductor region and a fourth semiconductor region in the second semiconductor region, which is independent of the third semiconductor region and is further away from the first semiconductor region and is exposed on the main surface; MO is inserted through the gate oxide film so that the fourth semiconductor region acts as a drain and a source.
MOSFET with S gate electrode, second semiconductor region and fourth
And an electrode for short-circuiting the semiconductor region on the main surface.

[0015] Preferably, the on-resistance when the MOSFET is on is smaller than the resistance of the second semiconductor region immediately below the MOSFET.

More preferably, a bonding surface formed by the third semiconductor region, the fourth semiconductor region, and the second semiconductor region, and a boundary surface between the second semiconductor region and the semiconductor base are substantially below the gate electrode. The second conductive type region on the surface of the semiconductor substrate below the gate electrode is made concentric and has a low impurity concentration. With such a configuration, the third semiconductor region and the fourth semiconductor region facing each other under the gate electrode and the second-conductivity-type high-impurity-concentration region sandwiched therebetween are formed by double diffusion using one common mask. It can be realized by forming.

[0017]

As a result of taking the above measures, the ON current flowing through the lateral thyristor can be controlled by controlling the MOSFET.

That is, when the third semiconductor region is at the lowest potential, the on-current flowing through the lateral thyristor is as described above.
When the MOSFET is turned on, the second semiconductor region immediately below the third semiconductor region, the second semiconductor region immediately below the fourth semiconductor region, the short-circuit electrode, the fourth semiconductor region, and the third semiconductor region via the channel of the MOSFET. A current path is formed that flows directly into the MOSFET, and this current can be controlled by the gate voltage of the MOSFET. When this current is increased by increasing the gate voltage, when the on-current of the lateral thyristor is kept constant, the on-voltage increases, and finally turns off. When the on-voltage is kept constant, the on-current increases. Such control of the voltage and current of the lateral thyristor can be realized more effectively by making the on-resistance of the MOSFET smaller than the resistance of the second semiconductor region immediately below the MOSFET.

On the other hand, when the fourth semiconductor region has the lowest potential, the ON current flowing through the lateral thyristor is equal to the MOSF.
When the ET is turned on, it flows into the fourth semiconductor region via this MOSFET. Increasing this current by increasing the gate voltage increases the on-current flowing through the lateral thyristor,
This ON voltage increases. When this current is reduced by reducing the gate voltage, the on-current flowing through the lateral thyristor decreases, and the on-voltage also decreases. In this case, the control of the voltage and current of the lateral thyristor can be more effectively realized by making the on-resistance of the MOSFET smaller than the resistance of the second semiconductor region immediately below the MOSFET.

In order to effectively control the on-resistance of the MOSFET by the gate voltage, it is desirable to lower the threshold voltage of the MOS transistor without adversely affecting other characteristics such as withstand voltage. Generally, the threshold voltage of a MOS transistor is determined by the thickness of a gate insulating film and the surface concentration of a base region in contact with the gate insulating film. To lower the threshold voltage, reduce the thickness of the gate insulating film or
What is necessary is just to reduce the surface concentration of the base region.

For this purpose, in the present invention, the source and the drain of the MOS transistor, which are opposed to each other, and the base region sandwiched therebetween are self-aligned by double diffusion using a common mask. At this time, the base region is brought into contact with each other by lateral diffusion from both sides of the gate portion, or by interposing a low impurity region between them,
The surface concentration of the base region below the gate electrode is kept low.

[0022]

FIG. 1 shows a first embodiment according to the present invention.
This embodiment is a horizontal insulated gate type turn-off thyristor made in an IC.

Here, the distance between the anode region 2 and the p base region 3 is 55 μm, the distance l _a between the double diffusions of the MOS transistor portion which is a feature of the present invention is 15 μm, and the specific resistance of the n-type substrate 1 is 20 Ω−. cm.

The surface concentration (C _{sp1 in} FIG. 10) of the anode region 2 and the p + base regions 3 and 4 is 5 × 10 ¹⁸ cm ⁻² , the diffusion depth is 5 μm, and the surface concentration of the p − base region 5 is 5 × 10 ¹⁵
cm ⁻² , diffusion depth 5 μm, n + type cathode region 6
The surface concentration (C _{sn in} FIG. 10) of the (source region of the MOS transistor) and the drain region 7 of the MOS transistor is 5 × 10 ¹⁹ cm ⁻² and the diffusion depth is 3 μm.

The maximum surface concentration (C _{sp2 in} FIG. 10) of the p base (including the p − base region 5 and the p + base regions 3 and 4) under the gate is 1 × 10 ¹⁷ cm ⁻² and the gate insulating film 8
Has a thickness of 0.1 μm.

This thyristor operates as a thyristor in the anode region 2-n base region 1-p + base region 3-n + emitter region 6.

[0027] In order to ON this, from P _B terminal p +
A current is supplied to the p + base region 3 via the base region 4 and the p− base region 5 to drive the same.

To turn it off, a positive voltage is applied to the gate G, and p + between the source (n + emitter of thyristor) 6 and the drain 7 of the MOS transistor portion is applied.
A channel is formed in the base region 3-p- base region 5-p + base region 4.

Thus, the n + emitter 6 and the p + base 3
And the thyristor is turned off.

Next, an outline of a method of manufacturing a MOS transistor portion of the insulated gate type turn-off thyristor of the present invention will be described.

First, as shown in FIG. 2, a p @-region 5 serving as a part of the p base of a MOS transistor is formed with a p-type impurity in a main surface on a side serving as a p base in an n-type substrate 1 of a thyristor. Formed. At this time, a thermal oxide film 16 used as a diffusion mask in a later step is also formed at the same time. Subsequently, as shown in FIG. 3, the thermal oxide film 16 on the p @-base region 5 other than where the channel region of the MOS transistor is to be formed is selectively removed by photo-etching to diffuse p-type impurities. The p + base regions 3, 4 of the thyristor are formed.

At this time, the p + base regions 3 and 4 spread below the thermal oxide film 16 by the lateral diffusion, and as shown in FIG. The thickness tox ₂ ) is formed to be smaller than the thermal oxide thickness tox ₁ on the p − region.

Subsequently, the resist 32 is used as a mask except for the area where the source (cathode of the thyristor) 6 and the drain of the MOS transistor section are opposed, and the area where the source and the drain are opposed is the above-mentioned oxide film thickness t.
by utilizing the difference in ox ₁ and tox _2, by an amount oxide film 16 of the oxide film thickness tox ₂ is removed to form a diffusion window 5A, 7A.

Further, using the remaining oxide film 16 as a mask as shown in FIG. 5, an n-type impurity is diffused from the diffusion windows 6A and 7A, so that the source region 6 and the drain region 7 of the MOS transistor are formed. Are simultaneously formed.

As described above, the opposing 2 under the gate electrode
The feature of the present invention lies in that two p + base regions 3 and 4 and n + regions 6 and 7 serving as a source and a drain are diffused and formed using the same oxide film 16 as a mask.

Thus, the p− region 5 and the p + regions 3 and 4
And the junction between n + region 6 and p + region 3 and the junction between n + region 7 and p + region 4 are concentric, so that the surface concentration of the channel region can be reduced.

Thereafter, as shown in FIG. 1, a predetermined gate oxide film 8 and electrodes 12, 13, 14, and 15 are formed in respective corresponding regions (however, the anode region 2 is formed of p
+ At the same time as the base is formed), the first of the horizontal insulated gate type turn-off thyristor as shown in FIG.
Is obtained.

The threshold voltage of the MOS transistor portion of the insulated gate type turn-off thyristor is about 3 V, the gate voltage applied when off is 10 V, and the forward and reverse withstand voltage of the thyristor is 350 V.

A typical example of the surface concentration between the source and the drain under the gate insulating film is shown in FIG. 9 for the conventional type and FIG. 10 for the present invention.

In the case of the conventional structure, as shown in FIG. 9, the p-based surface concentration for determining the threshold voltage is C _sp1 .

On the other hand, in the present invention, p-type and n-type impurities are double-diffused from the common diffusion window (self-alignment),
By forming the base region by lateral diffusion below the mask, the surface maximum concentration of the p base region can be C _sp2 lower than C _sp1 even with the same diffusion process. As a result, the threshold voltage can be reduced.

The concentration C _sp2 can be made substantially the same as the maximum p base maximum concentration in the lateral direction of the two double diffusions. Therefore, when the MOS transistor according to the present invention is forward biased, the depletion layer formed at the junction between the p base and the n base does not reach the n + cathode.
Therefore, the breakdown voltage does not decrease as compared with the conventional structure.

Therefore, according to the present invention, the threshold voltage can be reduced without lowering the breakdown voltage.

FIG. 6 shows an insulated gate turn-off thyristor according to a second embodiment of the present invention. In this structure, the p @-base portion 5 is removed from the MOS transistor portion of the first embodiment, and the p base of the MOS transistor is connected to the p @ + layers 3, 4.
It is formed only by.

This embodiment is different from the first embodiment in that M
Two p +, which are channel regions of the OS transistor section
The base regions 3 and 4 are configured to contact and overlap each other on the surface of the base under the gate insulating film 8.

That is, in the second embodiment, two p + between the source 6 and the drain 7 of the MOS transistor portion
Width l _b and p double diffusion mask of the base region 3 and 4 and the n + region 6 and 7 (the gate insulating film 8) + base layer 3 and 4
When the diffusion depth of _x.sub.jp is x _jp1 , the distance from the ends of both diffusion windows to the inside of the mask in the lateral direction and the two p + base layers 3 and 4 contact each other, ie, 2 × x 1 _jp1
And l ₁ > l _b (1). Furthermore, the distance l ₂ of the n + diffusion depth of the source 6 and drain 7 when the x _JN1, laterally from both diffusion window, diffuses inwardly of the mask, source and drain contacts, namely 2 between × l _b, as impart a relationship _{l b> l 2 ... (2} ), each part of the dimensions and material constants, processing time, etc. are set.

[0047] In the experimental example of the present inventors, a l _b and 7 [mu] m, others were designed the same as the first embodiment.

The feature of the second embodiment is that the process for forming the p @-layer 5 is not required, so that the process is simpler than that of the first embodiment, and the length of the p base of the MOS transistor is small. That is, since the gate length can be shortened, the mutual conductance can be increased as compared with the first embodiment.

As is apparent, the first and second embodiments can be applied to a vertical insulated gate type turn-off thyristor. For this purpose, the p + anode region may be provided below the n + region 38 in the first and FIG.

FIG. 7 shows a third embodiment to which the MOS transistor section of the present invention is applied.

This embodiment is a MOS gate type bipolar transistor.

This device has an n-emitter region 21 and a p + base region 1 which constitute one bipolar transistor.
8, comprising an n − collector substrate 17 and an n + collector layer 38. Further, below the gate portion G1 of the first MOS transistor portion, the source is made common to the n-emitter region 21 of the bipolar transistor, and the p base portion is formed by the method of the present invention. A region 20 is formed from the p + base region 19, and the n + drain region 22 and the p + base region 19 are short-circuited by the electrode 28.

In this case, the source 21, the drain 22, and the p + base regions 18 and 19 are formed on the opposite ends of the source 21 and the drain 22 by double diffusion using the same mask.

The second MOS transistor portion is formed by using the base region 18 in common, shorting the source region 23 and the base region 18 by the electrode 31, and sharing the drain with the n − collector. In this case, the source region 23 facing the drain 17 is formed by double diffusion using the same mask, using an oxide film at the end of the p + base region.

The structures of the p + regions 18 and 19, the p-region 20, the n + regions 21, 22, 23, and the MOS transistor portion of the G1 gate portion and their respective concentrations are described in the first embodiment. Is the same as the corresponding part.

When this transistor is turned on, a positive potential is applied to the gate G2 and a negative potential is applied to the gate G1 to turn on only the second MOS transistor on the gate G2 side. This allows the p + base 18 and the n- collector 17
Are short-circuited, and a base current is supplied to the bipolar transistor to turn it on.

When the transistor is turned off, a negative potential is applied to the G2 gate and a positive potential is applied to the G1 gate, and only the first MOS transistor on the gate G1 side is turned on. As a result, the emitter 21 and the base 18 of the bipolar transistor are short-circuited, and this transistor is turned off.

In the embodiment of FIG. 7, the first MOS transistor is formed by double diffusion using a common mask according to the present invention, so that the surface concentration of the p base can be reduced and the gate drive voltage is reduced. can do.

Of course, this MOS transistor section is
The same effect can be obtained by forming the same method as in the second embodiment (FIG. 6).

In the above description, a semiconductor device in which an n-channel MOS transistor is combined has been described as an example.
Naturally, the present invention can be applied to a combination of p-channel MOS transistors.

[0061]

According to the present invention, it is possible to effectively control the on-voltage and on-current of the lateral MOS thyristor without adversely affecting other characteristics such as the degree of integration and withstand voltage.

[Brief description of the drawings]

FIG. 1 is a first embodiment according to the present invention.

FIG. 2 shows a production method of the present invention.

FIG. 3 shows a production method of the present invention.

FIG. 4 shows a production method of the present invention.

FIG. 5 shows a production method of the present invention.

FIG. 6 shows a second embodiment according to the present invention.

FIG. 7 shows a third embodiment to which the MOS transistor section of the present invention is applied.

FIG. 8 shows a conventional insulated gate type turn-off thyristor.

FIG. 9 is a typical example of a surface concentration between a source and a drain under a gate insulating film, in a case of a conventional type.

FIG. 10 is a typical example of a surface concentration between a source and a drain under a gate insulating film, in the case of the present invention.

[Explanation of symbols]

1 ... n-type silicon substrate, 2 ... p + anode region, 3,
4, 18, 19 ... p + base region, 5, 20 ... p- base region, 8, 24, 26 ... gate insulating film, 12, 13,
14, 15, 27, 28, 29, 30 ... electrodes.

 ──────────────────────────────────────────────────の Continuation of front page (72) Inventor Yoshitaka Sugawara 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research Laboratory (56) References JP-A-60-74678 (JP, A)

Claims (2)

(57) [Claims] At least one of a first semiconductor region and a second semiconductor region of a second conductivity type, which are exposed on one main surface of a semiconductor substrate of a first conductivity type and are provided independently and opposed to each other, A third semiconductor region of the first conductivity type provided therein, and a second semiconductor region, wherein the first semiconductor surface is provided so as to face the third semiconductor region and to be further away from the first semiconductor region than the third semiconductor region; And a fourth semiconductor region exposed to the semiconductor device via a gate oxide film such that the third semiconductor region and the fourth semiconductor region act as a drain and a source of the MOSFET.
A MOS gate electrode provided; and an electrode for short-circuiting a second semiconductor region and a fourth semiconductor region on the main surface , wherein the second semiconductor region is a third semiconductor region and a fourth semiconductor region.
A fifth semiconductor region of the second conductivity type and a sixth
And a semiconductor region, under the MOS gate electrode.
In this case, only the region with both impurity concentration gradients overlaps
A composite semiconductor device, which is characterized in that: 2. A method according to claim 1, wherein at least one of the first conductive type semiconductor substrates is provided.
Second conductors exposed on the surface and provided independently and opposite to each other
A first semiconductor region and a second semiconductor region of a first conductivity type, and a third semiconductor of a first conductivity type provided in the second semiconductor region
In the region and the third semiconductor region in the second semiconductor region
And more distant from the first semiconductor region than from the third semiconductor region.
A fourth semiconductor region exposed on the one main surface, and a third semiconductor region and a fourth semiconductor region are connected to a drain of the MOSFET.
And through the gate oxide to act as a source
Providing a MOS gate electrode, a second semiconductor region and a fourth semiconductor region on the main surface;
An electrode to be short-circuited , wherein the second semiconductor region below the MOS gate electrode is connected to a third semiconductor region.
Impurity of second conductivity type including body region and fourth semiconductor region
Concentration of the fifth and sixth semiconductor regions and the low impurity concentration.
And a seventh semiconductor region .