JPS6074678A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6074678A JPS6074678A JP18272883A JP18272883A JPS6074678A JP S6074678 A JPS6074678 A JP S6074678A JP 18272883 A JP18272883 A JP 18272883A JP 18272883 A JP18272883 A JP 18272883A JP S6074678 A JPS6074678 A JP S6074678A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- type
- diffusion layer
- layer
- dirt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000015556 catabolic process Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims description 66
- 206010011224 Cough Diseases 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 101150114751 SEM1 gene Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、例えばＳＳＲ（５ｏｔｌｄ ５ｔａｔｅ
Ｒｅｔａｙ）に使用され、ＭＯ８（Ｍ＠ｔａｔＯｘｌｄ
ｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ ）構造によってトリ
が機能が制御される、サイリスタおよびトライアック等
の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field of the invention] This invention relates to, for example, SSR (5otld 5tate
MO8 (M@tatOxld)
The present invention relates to semiconductor devices such as thyristors and triacs whose functions are controlled by a structure.
例えば温度制御回路および時間制御回路に使用されるＳ
ＳＨには、一般に電気トリガまたは光トリガによってス
イッチング動作するサイリスタ、トライアック等の半導
体装置が組み込まれる。For example, S used in temperature control circuits and time control circuits.
The SH generally incorporates a semiconductor device such as a thyristor or a triac that performs a switching operation using an electric trigger or an optical trigger.
ｔＡＪｋはｒ−）。、カッ−１間に、。８構造部１１を
設けたサイリスタ（特開昭５５−７４１６８ ）を示す
もので、このサイリスタはＰ型とＮ型のタイプの異なる
４つの領域（ＰＮＰＮ ）より形成されている。すなわ
ち、このサイリスタは、アノード電極Ａにプラス（ト）
、カソード電極Ｋにマイナス←）の電圧を印加した状態
で、ダート電極Ｇにプラス（ト）の電圧を印加すると導
通状態になるもので、この場合、ＭＯ８構造部１１のダ
ート酸化膜に印加される電圧が、そのしきい値電圧を越
えると、ダートＧ、カソードに間が短絡してトリガ機能
をオフ制御し遮断状態となるものである。このよりな、
ＭＯ８構造部１１のダート酸化膜のしきい値電圧に対応
する特定電圧範囲でのみトリガ機能をオン制御してサイ
リスタを動作させる機能を、一般に、ゼロクロス機能と
称する。ここで、上記ＭＯ８構造部１１の？−）部には
、ダート酸化膜の絶縁破壊防止対策として、２つのコン
デンサＣＩおよびＣ２で分圧した一方の電圧を印加する
ようにしている。tAJk is r-). , for a while. This figure shows a thyristor (Japanese Unexamined Patent Publication No. 55-74168) provided with eight structural parts 11, and this thyristor is formed of four regions (PNPN) of different types, P-type and N-type. In other words, this thyristor has a positive (t)
When a positive (←) voltage is applied to the dirt electrode G while a negative (←) voltage is applied to the cathode electrode K, a conductive state is established. When the voltage exceeds the threshold voltage, a short circuit occurs between dart G and the cathode, and the trigger function is controlled to be turned off, resulting in a cutoff state. More than this,
The function of operating the thyristor by turning on the trigger function only in a specific voltage range corresponding to the threshold voltage of the dirt oxide film of the MO8 structure 11 is generally referred to as a zero-cross function. Here, ? of the MO8 structure part 11? -) As a measure to prevent dielectric breakdown of the dirt oxide film, one voltage divided by two capacitors CI and C2 is applied.
次に、第２図および第３図は、それぞれ、上記第１図に
おける場合と同様のトリが機能制御用のＭＯ８構造部１
２および１３を設けたサイリスタ（特開昭５４−２６８
０）およびトライアック（特開昭５５−３６９４）を示
すもので、このサイリスタおよびトライアックの何れの
場合においても、ＭＯ８構造部１２．１３のダート部に
は、直接アノードＡ、カソードに間の電圧が印加される
ようになっている。この場合、ｆ−）酸化膜の絶縁耐圧
を上げる為には、そのダート酸化膜の膜厚を厚く形成し
なければならない。この事は、前記第１図におけるサイ
リスタにおいても同様である。ここで、上記第１図乃至
第３図における半導体装置は、何れの場合においても、
最大電圧が例えば、４００ （Ｖ）程度以下の低電圧県
外下で使用されるものである。Next, in FIGS. 2 and 3, the same bird as in FIG. 1 is used for function control MO8 structure 1.
Thyristor equipped with 2 and 13 (Japanese Patent Application Laid-Open No. 54-268
0) and a triac (Japanese Unexamined Patent Publication No. 55-3694). In both the thyristor and the triac, the voltage between the anode A and the cathode is directly applied to the dirt part of the MO8 structure 12.13. It is now applied. In this case, in order to increase the dielectric strength of the f-) oxide film, the dart oxide film must be formed thickly. This also applies to the thyristor shown in FIG. 1 above. Here, in any case, the semiconductor devices shown in FIGS. 1 to 3 are as follows.
It is used outside the prefecture with low voltages where the maximum voltage is, for example, about 400 (V) or less.
しかし、このように、 ＭＯ８構造部のダート酸化膜の
絶縁耐圧を上げる為に、その酸化膜自体の膜厚を厚く形
成したのでｔｊ：、Ｍ２Ｓ部のしきいｆｔｏｔｌＥが上
がってトリガ機能を制御する特定電圧範囲が広がる状態
と彦る。すなわち、例えば前述したそれぞれの半導体装
置を、最大電圧１０００（イ）程度の高電圧条件下で使
用する場合には、Ｍ２Ｓ部のしきい値電圧が上がってゼ
ロクロス機能を低下させると共に、比較的高いアノード
Ａ、カソードに間室圧でもトリガ機能がオン制御される
ようになシ、そのスイッチング時に伴なって電磁障害が
発生する恐れがある。However, in order to increase the withstand voltage of the dirt oxide film in the MO8 structure, the thickness of the oxide film itself is made thicker, so the threshold ftotlE of the M2S part increases and controls the trigger function. It seems like the specific voltage range is expanding. That is, for example, when each of the above-mentioned semiconductor devices is used under a high voltage condition with a maximum voltage of about 1000 (a), the threshold voltage of the M2S section increases and reduces the zero-crossing function, and the relatively high Since the trigger function is controlled to be turned on even when there is pressure between the anode A and the cathode, electromagnetic interference may occur during switching.
この発明は上記のような問題点に鑑みなされたもので、
例えば最大電圧１０００（Ｉｉｌ）というような高電圧
条件下で使用するような場合でも、ゼロクロス機能を低
下させることなく、ダート酸化膜の絶縁破壊を防止する
ことが可能と力る半導体装置を提供することを目的とす
る。This invention was made in view of the problems mentioned above.
To provide a semiconductor device capable of preventing dielectric breakdown of a dirt oxide film without deteriorating zero cross function even when used under high voltage conditions such as a maximum voltage of 1000 (Iil). The purpose is to
すなわちこの発明に係る半導体装置は、Ｎ型半導体基板
面のＭＯ８構造を設けたＰ型ゲート拡散層に近接した距
離で、上記ＭＯ８構造のｆ−）≠°′電気的に接続した
Ｐ型拡散領域を形成し、Ｐ型アノード拡散層とＮ型カソ
ード拡散層との間に、上記ＭＯ８構造のダート酸化膜の
絶縁破壊電圧を印加した際に、上記Ｐ型拡散領域に対し
て空乏層が到達するようにしたものである。That is, in the semiconductor device according to the present invention, the P-type diffusion region is electrically connected to f-)≠°' of the MO8 structure at a distance close to the P-type gate diffusion layer provided with the MO8 structure on the surface of the N-type semiconductor substrate. When a dielectric breakdown voltage of the dirt oxide film of the MO8 structure is applied between the P-type anode diffusion layer and the N-type cathode diffusion layer, the depletion layer reaches the P-type diffusion region. This is how it was done.
以下図面によルこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第４図はその構成を示すもので、この半導体装置はＮ型
の半導体基板２１から形成する。このＮ型半導体基板２
１の主表面には、まず、Ｐ型ｆ−）拡散層２２を形成し
、このＰ型ダート拡散層２２の表面には、例えばそれぞ
れ同一の拡散形状で第１および第２のＮ型カソード拡散
層２３および２４を形成する。この第２のＮ型カソード
拡散層２４は、アルミニウム等による導電部２５によシ
上記Ｐ型？−）拡散層２２に電気的に接続されるもので
、このＰ型ダート拡散層２２の中央部表面上には、上記
第１および第２のＮ型カソード拡散層２３．２４それぞ
れへζｙ部に接触するようにしてダート酸化８２６を形
成する。そして、このダート酸化膜２６の表面上には、
ｒ−ト導電層２１を形成し、破線で示すようなＭＯＳ
（ＭａｔａｔＯｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ
）構造部２８を構成する。FIG. 4 shows its structure, and this semiconductor device is formed from an N-type semiconductor substrate 21. This N-type semiconductor substrate 2
First, a P-type f-) diffusion layer 22 is formed on the main surface of the P-type dirt diffusion layer 22, and on the surface of this P-type dirt diffusion layer 22, for example, first and second N-type cathode diffusion layers each having the same diffusion shape are formed. Form layers 23 and 24. This second N-type cathode diffusion layer 24 is formed of the above-mentioned P type? -) electrically connected to the diffusion layer 22, and on the central surface of the P-type dirt diffusion layer 22 there is a A dirt oxide 826 is formed in contact. Then, on the surface of this dirt oxide film 26,
A MOS conductive layer 21 is formed as shown by the broken line.
(Matat Oxide Sem1 conductor
) constitutes the structural part 28.
また、このＮ型半導体基板２ノの主表面には、上記Ｐ型
ゲート拡散層２２に近接した距離ｔで、フローティング
Ｐ型拡散領域２９を形成する。Furthermore, a floating P-type diffusion region 29 is formed on the main surface of the N-type semiconductor substrate 2 at a distance t close to the P-type gate diffusion layer 22 .
このＰ型拡散領域２９は、上記ＭＯ８構造部２８のダー
ト酸化膜２６上に形成したダート導電層２７に電気的に
接続されるもので、このＰ型拡散領域２９を形成したＮ
型半導体基板２１の主表面と反対側の表面には、Ｐ型ア
ノード拡散層３０を形成する。そして、このＰ型アノー
ド拡散層３０および上記第１のＮ型カソード拡散層２３
、Ｐ型ｆｆ−）拡散層２２から、それぞれ、アノード電
極Ａおよびカソード電極に１ゲート電極Ｇを導出する。This P-type diffusion region 29 is electrically connected to the dirt conductive layer 27 formed on the dirt oxide film 26 of the MO8 structure 28, and the P-type diffusion region 29 is
A P-type anode diffusion layer 30 is formed on the surface of the semiconductor substrate 21 opposite to the main surface. This P-type anode diffusion layer 30 and the first N-type cathode diffusion layer 23
, P-type ff-) diffusion layer 22, one gate electrode G is led out as an anode electrode A and a cathode electrode, respectively.
ことで、上記Ｐ型ゲート拡散層２２とＰ型拡散領域２９
との距離ｔは、アノード電極Ａとカッ′（ド電極にとの
間に、ダート酸化膜２６の絶縁破壊電圧Ｖｔを印加した
際に、Ｐ型ｆ−）拡散層２２とＮ型半導体基板２１との
界面に生じる破線ａで示すような空乏層３１の幅板下に
設定される。As a result, the P-type gate diffusion layer 22 and the P-type diffusion region 29
When the dielectric breakdown voltage Vt of the dirt oxide film 26 is applied between the anode electrode A and the cathode electrode, the distance t between the P-type f−) diffusion layer 22 and the N-type semiconductor substrate 21 The depletion layer 31 is set under the width plate of the depletion layer 31 as shown by the broken line a generated at the interface with the depletion layer 31.
つｔシ、例えば、上記ＭＯ８構造部２８のしきい値電圧
ｖＴを５〜６Ｍ程度に設定する場合には、Ｐ型ダート拡
散層２２の表面濃度をｌＸｌ０”（ｃＩＩＬ−３）、界
面電荷密度をｌ ｘ ｌ Ｑ”（ａｍ−２）とすれば、
ダート酸化膜２６の膜厚は１５００ （１）程度に設定
される。ここで、このｆ−）酸化膜２６（１５００Ｘ）
の絶縁破壊電圧Ｖｔは一般に１２０〜１３０Ｍ程度であ
る。すなわち、このダート酸化膜２６（１５００Ｘ）Ｏ
絶縁破壊電圧Ｖｔ＝１２０（Ｖ）を、Ｐ型アノード拡散
層３０−Ｎ型カソード拡散層２３間に印加した場合に生
じる空乏層３１の幅は、Ｎ型半導体基板２１の濃度を１
ｘｌＯ（ｃｍ ）、Ｐ型ゲート拡散層２２の拡散深さを
４０（μｍ）とすれば、３０（μｍ）８度と々る。よっ
て、この場合、上記Ｐ型ｒ−）拡散層２２とＰ型拡散領
ｉ″２９との距離ｔは、３０（μｍ）以下〔ｔく３０（
μｍ））の適描な値に設定すればよい。For example, when setting the threshold voltage vT of the MO8 structure 28 to about 5 to 6M, the surface concentration of the P-type dirt diffusion layer 22 is set to lXl0'' (cIIL-3), the interface charge density is If it is l x l Q” (am-2), then
The thickness of the dirt oxide film 26 is set to about 1500 (1). Here, this f-) oxide film 26 (1500X)
The dielectric breakdown voltage Vt is generally about 120 to 130M. That is, this dirt oxide film 26 (1500X)O
The width of the depletion layer 31 that occurs when dielectric breakdown voltage Vt=120 (V) is applied between the P-type anode diffusion layer 30 and the N-type cathode diffusion layer 23 is such that the concentration of the N-type semiconductor substrate 21 is 1.
xlO (cm 2 ) and the diffusion depth of the P-type gate diffusion layer 22 is 40 (μm), it is 30 (μm) and reaches 8 degrees. Therefore, in this case, the distance t between the P-type r-) diffusion layer 22 and the P-type diffusion region i''29 is less than or equal to 30 (μm).
It may be set to an appropriate value of μm).
すなわちこのように構成される半導体装置において、ま
ず、アノード電極Ａ−カソード電極に間電圧ｖＡＫを、
ＯＭから次第に上昇させると、空乏層３１は徐々にＮ型
基板２１側に広がるようになる。ここで、フローティン
グＰ型拡散領域２９およびＭＯ８構造部２８のダート導
電層２７それぞれの電位は、上記アノードＡ−カソード
に間電圧Ｖ□と同電位になるもので、この電圧ｖＡＫが
ＭＯ８構造部２８のしきい値電圧ＶＴ＝５〜６（ｖ）程
度に達するまでの範囲内では、トリが機能はオン制御さ
れ、ダート電極Ｇに供給される電気トリが信号またはＰ
型ゲート拡散層２２の表面に照射される光トリが信号ｐ
ｈによってこの半導体装置は導通状態となる。この場合
、トリガ機能がオン制御されるＭＯ８構造部２８のしき
い値電圧範囲ＯＭ〜■、＝５〜６Ｍを比較的狭く設定し
たので、電磁障害が発生することはない。That is, in the semiconductor device configured in this way, first, a voltage vAK is applied between the anode electrode A and the cathode electrode.
When gradually rising from OM, the depletion layer 31 gradually spreads toward the N-type substrate 21 side. Here, the respective potentials of the floating P-type diffusion region 29 and the dirt conductive layer 27 of the MO8 structure 28 are the same potential as the voltage V□ between the anode A and the cathode, and this voltage vAK is Until the threshold voltage VT of 5 to 6 (v) is reached, the function of the bird is controlled to be on, and the electric bird supplied to the dirt electrode G is not connected to the signal or P
The light beam irradiated onto the surface of the gate diffusion layer 22 generates the signal p.
This semiconductor device becomes conductive due to h. In this case, since the threshold voltage range OM~■,=5~6M of the MO8 structure 28 in which the trigger function is turned on is set to be relatively narrow, electromagnetic interference will not occur.
次に、アノードＡ−カソードに間電圧ｖＡＫが、ｍｓ’
ｍ造部２８のしきい値電圧ｖ、＝５〜６（Ｖを越えた場
合には、ダート酸化膜２６直下のＰ型ゲート拡散層２２
０表面には、ｎチャンネルが形成されるようになシ、第
１のＮ型カソード拡散層２３と第２のＮ型カソード拡散
層２４とは結合されるように々る。これにより、第１お
よび第２のＮ型カソード拡散層２３．２４とＰ型ダート
拡散層２２とは、導電部２５により電気的に接続される
ように々す、ｆ−）電極Ｇとカソード電極にとは短絡す
るように々る。この場合、この半導体装置のトリガ機能
はオフ制御されるようになシ、いかなるトリガ信号や外
来ノイズが供給されたとしても導通状態になることはな
い。Next, the voltage vAK between the anode A and the cathode is ms'
The threshold voltage v of the m-structured portion 28 is 5 to 6 (if it exceeds V, the P-type gate diffusion layer 22 directly under the dirt oxide film 26
An n-channel is formed on the 0 surface, and the first N-type cathode diffusion layer 23 and the second N-type cathode diffusion layer 24 are bonded together. As a result, the first and second N-type cathode diffusion layers 23 and 24 and the P-type dirt diffusion layer 22 are electrically connected to each other by the conductive portion 25.f-) The electrode G and the cathode electrode It seems like there is a short circuit with Ni. In this case, the trigger function of this semiconductor device is controlled to be off, and will not become conductive even if any trigger signal or external noise is supplied.
そして、アノードＡ−カソードに間電圧■。And the voltage between the anode A and the cathode is ■.
が、ＭＯ８構造部２８のｆ−）酸化膜２６の絶縁破壊電
圧Ｖｔ−１２０（Ｖ）付近まで上昇した場合には、空乏
層３ノは破Ｊで示すように、フローティングＰ型拡散領
域２９に到達するようになシ、イワゆる、Δンチスルー
現象が生じる。これによシ、さらにアノードＡ−カソー
ドに間電圧ＶＡＫが上昇した場合には、Ｐ型拡散領域２
９は、破線すで示すように、空乏層３１によ〕完全に包
囲されるようにな勺、その電位は上記パンチスル一時に
おける電圧値、つまり、ダート酸化膜２６の絶縁破壊電
圧Ｖｔ＝１２０（Ｖ）付近の一定電圧値に保持されるよ
うになる。この場合、ＭＯ８構造部２８のｆｆ−）導電
層２７に印加される電圧も、上記一定電圧値に保持され
るようＫなるので、例えば、アノードＡ−カソードに間
電圧Ｖ□が、１０００（Ｖ）というような高電圧まで上
昇したとしても、ｅ−）酸化膜２６が絶縁破壊されるよ
うなことはない。However, when the dielectric breakdown voltage of the f-) oxide film 26 of the MO8 structure 28 rises to around Vt-120 (V), the depletion layer 3 is broken into the floating P-type diffusion region 29 as shown by the broken J. As this happens, the Δ anti-through phenomenon occurs. As a result, if the voltage VAK between the anode A and the cathode further increases, the P-type diffusion region 2
9 is completely surrounded by the depletion layer 31 as already shown by the broken line, and its potential is the voltage value at the time of punching, that is, the dielectric breakdown voltage Vt of the dirt oxide film 26 = 120 ( V) is maintained at a constant voltage value around V). In this case, the voltage applied to the ff-) conductive layer 27 of the MO8 structure 28 is also maintained at the constant voltage value, so that, for example, the voltage V□ between the anode A and the cathode is 1000 (V Even if the voltage rises to a high voltage such as e-), the oxide film 26 will not undergo dielectric breakdown.
したがって、このように構成される半導体装置によれば
、ｆｆ−）酸化膜２６の絶縁破壊電圧Ｖｔ以下で、空乏
層３１が到達する距離ｔに、７０−テイングＰ型拡散領
域２９を形成したことによシ、ＭＯ８構造部２８の？−
）導電層２１には、上記絶縁破壊電圧Ｖｔを上回るよう
な電位は一切印加されなくなシ、ダート酸化膜２６が絶
縁破壊されるのを防止することができる。Therefore, according to the semiconductor device configured as described above, the 70-Teing P-type diffusion region 29 is formed at a distance t that the depletion layer 31 reaches at a voltage lower than the dielectric breakdown voltage Vt of the ff-) oxide film 26. Yes, what about MO8 structure part 28? −
) No potential exceeding the dielectric breakdown voltage Vt is applied to the conductive layer 21, thereby preventing dielectric breakdown of the dirt oxide film 26.
尚、上記実施例では、Ｐ型アノード拡散層３０をＮ型カ
ソード拡散層２３．２４の反対側の表面に形成し、縦型
構造としたが、このＰ型アノード拡散層３０は、例えば
第５図に示すように、上記Ｎ型カソード拡散層２３．２
４と同一の表面に形成し、横型構造としてもよい。また
、各細波を逆導電型にすることも勿論可能である。In the above embodiment, the P-type anode diffusion layer 30 was formed on the surface opposite to the N-type cathode diffusion layer 23, 24 to have a vertical structure. As shown in the figure, the N-type cathode diffusion layer 23.2
It may be formed on the same surface as 4 and may have a horizontal structure. Furthermore, it is of course possible to make each wavelet of opposite conductivity type.
以上のようにこの発明によれば、アノード。 As described above, according to the present invention, the anode.
カソード間に印加される最大電圧に関係なく、ＭＯ８構
造部を設計することができるので、例えば、最大電圧１
０００（ロ）というような高電圧条件下で使用するよう
な場合でも、ダート酸化膜を厚く設計する必要がないの
で、ゼロクロス機能を低下させることなく、ダート酸化
膜の絶縁破壊を防止することが可能となる。Since the MO8 structure can be designed independently of the maximum voltage applied across the cathode, e.g.
Even when used under high voltage conditions such as 000 (b), there is no need to design the dart oxide film to be thick, so it is possible to prevent dielectric breakdown of the dart oxide film without degrading the zero-cross function. It becomes possible.
第１図乃至第３図はそれぞれトリガ機能制御用のＭＯ８
構造部を設けた従来の半導体装置を示ず回路構成図、第
４図はこの発明の一実施例に係る半導体装置を示す断面
構成図、第５図は上記この発明の一実施例に係る半導体
装置の他の実施例を示す断面構成図である。
２１・・・Ｎ型半導体基板、２２・・・Ｐ型ダート拡散
層、２３・・・第１のＮ型カソード拡散層、２４・・・
第２のＮ型カソード拡散層、２５・・・導電部、２６・
・・ｆ−）酸化膜、２７・・・ダート導電層、２８・・
・ＭＯ８構造部、２９・・・フローティングＰ型拡散領
域、３０・・・Ｐ型アノード拡散層、３１・・・空乏層
。
出願人代理人 弁理士 鈴 江 武 彦第１図 ｓ２図
第３図Figures 1 to 3 show MO8 for trigger function control.
FIG. 4 is a cross-sectional configuration diagram showing a semiconductor device according to an embodiment of the present invention; FIG. FIG. 7 is a cross-sectional configuration diagram showing another example of the device. 21... N-type semiconductor substrate, 22... P-type dirt diffusion layer, 23... first N-type cathode diffusion layer, 24...
second N-type cathode diffusion layer, 25... conductive part, 26...
...f-) Oxide film, 27... Dirt conductive layer, 28...
- MO8 structure part, 29... floating P type diffusion region, 30... P type anode diffusion layer, 31... depletion layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure s2 Figure 3
Claims (1)
る第二導電型アノード拡散層および第二導電型ダート拡
散層と、この第二導電型ｙ −ト拡散層の表面に形成さ
れる第１および第２の第一導電型カソード拡散層と、こ
の第２の第一導電型カソード拡散層と上記第二導電型ダ
ート拡散層とを電気的に接続する導電部と、上記第二導
電型ダート拡散層の表面上に上記第１および第２の第一
導電型カソード拡散層それぞれの表面に接触して形成さ
れるｆ−）酸化膜と、このダート酸化膜の表面上に形成
される導電層と、このダート酸化膜上の導電層に電気的
に接続され上記第一導電型半導体基板の表面に上記第二
導電型？−）拡散層に近接した距離で形成される第二導
電型拡散領域とを具備したことを特徴とする半導体装置
。 咳２）上記第二導電型ｒ−）拡散層と第二導電型拡散領
域との距離は、第二導電型アノード拡散層と第１の第一
導電型カソード拡散層との間に、ｒ−）酸化膜の絶縁破
壊電圧を印加した際に、第二導電型ダート拡散層と第一
導電型半導体基板との界面に生じる空乏層の幅以下に設
定したことを特徴とする特許請求の範囲第１項記載の半
導体装置。(1) A second conductivity type anode diffusion layer and a second conductivity type dirt diffusion layer formed on the surface of the first conductivity type semiconductor substrate, and a second conductivity type y-t diffusion layer formed on the surface of the second conductivity type y-t diffusion layer. 1 and a second first conductivity type cathode diffusion layer; a conductive portion electrically connecting the second first conductivity type cathode diffusion layer and the second conductivity type dirt diffusion layer; an f-) oxide film formed on the surface of the dirt diffusion layer in contact with the respective surfaces of the first and second first conductivity type cathode diffusion layers; and a conductive film formed on the surface of the dirt oxide film. layer and the second conductivity type on the surface of the first conductivity type semiconductor substrate electrically connected to the conductive layer on this dirt oxide film? -) a second conductivity type diffusion region formed at a distance close to the diffusion layer. Cough 2) The distance between the second conductivity type r-) diffusion layer and the second conductivity type diffusion region is such that the distance between the second conductivity type anode diffusion layer and the first first conductivity type cathode diffusion layer is r- ) The width of the depletion layer formed at the interface between the second conductivity type dirt diffusion layer and the first conductivity type semiconductor substrate is set to be less than or equal to the width of the depletion layer formed at the interface between the second conductivity type dirt diffusion layer and the first conductivity type semiconductor substrate when a dielectric breakdown voltage of the oxide film is applied. The semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18272883A JPS6074678A (en) | 1983-09-30 | 1983-09-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18272883A JPS6074678A (en) | 1983-09-30 | 1983-09-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6074678A true JPS6074678A (en) | 1985-04-26 |
| JPH0580158B2 JPH0580158B2 (en) | 1993-11-08 |
Family
ID=16123401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18272883A Granted JPS6074678A (en) | 1983-09-30 | 1983-09-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074678A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6353972A (en) * | 1986-08-22 | 1988-03-08 | Hitachi Ltd | Composite semiconductor device |
| JPS6384067A (en) * | 1986-09-27 | 1988-04-14 | Toshiba Corp | Semiconductor device and manufacture thereof |
| EP0276703A2 (en) * | 1987-01-26 | 1988-08-03 | Kabushiki Kaisha Toshiba | Zero-crossing type thyristor |
| EP0281739A2 (en) * | 1987-01-23 | 1988-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device comprising a thyristor |
| US4943835A (en) * | 1985-11-22 | 1990-07-24 | Kabushiki Kaisha Toshiba | Semiconductor device including protecting MOS transistor |
| JPH07147394A (en) * | 1994-08-05 | 1995-06-06 | Hitachi Ltd | Compound semiconductor device |
| US5747836A (en) * | 1995-09-11 | 1998-05-05 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit provided with thyristor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105572A (en) * | 1981-12-18 | 1983-06-23 | Sanken Electric Co Ltd | Zero cross photo thyristor |
-
1983
- 1983-09-30 JP JP18272883A patent/JPS6074678A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105572A (en) * | 1981-12-18 | 1983-06-23 | Sanken Electric Co Ltd | Zero cross photo thyristor |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943835A (en) * | 1985-11-22 | 1990-07-24 | Kabushiki Kaisha Toshiba | Semiconductor device including protecting MOS transistor |
| JPS6353972A (en) * | 1986-08-22 | 1988-03-08 | Hitachi Ltd | Composite semiconductor device |
| JPS6384067A (en) * | 1986-09-27 | 1988-04-14 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH0548957B2 (en) * | 1986-09-27 | 1993-07-22 | Toshiba Kk | |
| EP0281739A2 (en) * | 1987-01-23 | 1988-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device comprising a thyristor |
| US4992844A (en) * | 1987-01-23 | 1991-02-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| EP0276703A2 (en) * | 1987-01-26 | 1988-08-03 | Kabushiki Kaisha Toshiba | Zero-crossing type thyristor |
| US4956690A (en) * | 1987-01-26 | 1990-09-11 | Kabushiki Kaisha Toshiba | Zero crossing type thyristor |
| JPH07147394A (en) * | 1994-08-05 | 1995-06-06 | Hitachi Ltd | Compound semiconductor device |
| US5747836A (en) * | 1995-09-11 | 1998-05-05 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit provided with thyristor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0580158B2 (en) | 1993-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3751722A (en) | Mos integrated circuit with substrate containing selectively formed resistivity regions | |
| US3302076A (en) | Semiconductor device with passivated junction | |
| GB1579938A (en) | Semiconductor devices | |
| US3855611A (en) | Thyristor devices | |
| JPS6074678A (en) | Semiconductor device | |
| US3432731A (en) | Planar high voltage four layer structures | |
| US2994811A (en) | Electrostatic field-effect transistor having insulated electrode controlling field in depletion region of reverse-biased junction | |
| US4430663A (en) | Prevention of surface channels in silicon semiconductor devices | |
| JP3718223B2 (en) | Semiconductor device for high voltage with vertical groove | |
| US5506425A (en) | Semiconductor device and lead frame combination | |
| JPS5753944A (en) | Semiconductor integrated circuit | |
| JPH0154865B2 (en) | ||
| US3704384A (en) | Monolithic capacitor structure | |
| US4170019A (en) | Semiconductor device with variable grid openings for controlling turn-off pattern | |
| EP4092755A3 (en) | Semiconductor device with conductive element formed over dielectric layers and method of fabrication therefor | |
| KR20030057490A (en) | Bidirectional static switch responsive in quadrants q4 and q1 | |
| JPS57172765A (en) | Electrostatic induction thyristor | |
| US3654498A (en) | Semiconductor device having an integrated pulse gate circuit and method of manufacturing said device | |
| US3274400A (en) | Temperature compensated silicon controlled rectifier | |
| US4163241A (en) | Multiple emitter and normal gate semiconductor switch | |
| US4231054A (en) | Thyristor with starting and generating cathode base contacts for use in rectifier circuits | |
| US3555372A (en) | Semiconductor bilateral switching device | |
| US4187515A (en) | Semiconductor controlled rectifier | |
| JPS56110288A (en) | Semiconductor laser element | |
| JPS572574A (en) | Insulated gate type field effect transistor |