JPH02201964A - Mos type transistor - Google Patents

Abstract

PURPOSE:To attain the high integration of a title transistor and speed up the operation of the same by independently controlling respective voltages on gate electrodes to restrict the production of hot carriers by connecting connection terminals to a plurality of divided gate electrodes respectively. CONSTITUTION:A plurality of divided gate electrodes 23 are provided, to each of which a connection terminal is connected to independently control voltage of each gate electrode 23. Accordingly, voltage on the gate electrode 23 divided and arranged in the vicinity of a drain electrode 25 where a very high electric field is existent can be set to voltage with which a hot carrier is less produced. Further, once an independent binary signal is applied to each gate electrode 23, there is formed a logical circuit having inputs corresponding to the divided electrodes. Hereby, the production of such a hot carrier can be restricted, and when it is desired to construct a logical circuit, the number of used transistors can be reduced to assure high integration of an IC and speed up the operation of the same.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of MO3 field effect transistors (MOSFETs) used in semiconductor integrated circuits, and is particularly effective when applied to miniaturized transistors with short gate lengths. relating to things.

Semiconductor integrated circuits (ICs) have MO as an active device.
There are those that use S-type transistors and those that use bipolar transistors, but MOS-type transistors have the advantage of being able to increase the degree of integration by one order of magnitude or more than bipolar transistors.

The structure of a MOS type transistor is, for example, M shown in FIG.
Like an OSFET, a source region diffusion layer 13 and a drain region diffusion layer 14 are formed on both ends of one gate electrode 12 in a semiconductor substrate 11, and an insulating film 15 is formed between the semiconductor substrate 11 and the gate electrode 12. ing. and,
Switching is performed by applying a voltage to the gate electrode 12, and a logic circuit can be constructed by combining a plurality of them as shown in FIG. 4(b). In this case, only one type of binary signal of 1° or 0° can be applied to one gate electrode.

By the way, in order to increase the integration and speed of ICs,
There is a demand for miniaturization of the elements constituting this, and for this purpose, it is necessary to downsize the MO5 type transistor.

However, as the size of MO3 type transistors has progressed, a reduction in threshold voltage due to short channel effects and deterioration of transistor characteristics due to generation of hot carriers have become problems.

When the channel length of an MO3 type transistor becomes short, the electric field near the drain region/diffusion layer 14 below the gate electrode 12 becomes extremely high (and the electric field concentration 16 increases) under a constant power supply voltage, as shown in FIG. This generates hot carriers that have obtained high energy from the electric field.The amount of hot carriers generated greatly depends on the gate voltage and drain voltage, and moreover, they are generated more when the gate voltage changes.For example, when the train voltage is set to 5V. When the gate voltage is changed, the amount of hot carriers generated reaches its peak when the gate voltage is about 1/2 of the drain voltage, as shown in Figure 8. A part of it is injected into the oxide film (insulating film) and remains there, changing the threshold voltage of the transistor.Threshold voltage is the most important characteristic value in configuring IC1, especially LSI. Therefore, it is necessary to suppress the hot carrier effect that changes the threshold voltage.

In order to suppress this short channel effect, it is necessary to reduce the thickness of the diffusion layer of the source and drain electrodes, and an LDD structure has been proposed as a technique to alleviate the electric field concentration near the drain. (Unexamined Japanese Patent Publication No. 59-52
878). As shown in FIG. 9, in this LDD structure, a shallow impurity diffusion layer 17 doped with a low concentration of impurity is formed near the gate electrode 12 as a source/drain region, and the adjacent region (outer side on the left and right in the figure) is formed near the gate electrode 12 as a source/drain region. ) is formed with a deep impurity diffusion layer 18 doped with impurities at a high concentration.

The sun is about to set. However, in the MO3 type transistor having the LDD structure, it is difficult to control the impurity profile of the impurity diffusion layers 17 and 18, and it is difficult to optimize and form the impurity profile. Especially when making shallow joints,
It has been difficult to satisfy both the impurity concentration and junction depth. In addition, the source electrode and
A structure in which a drain electrode is formed has also been proposed, but the manufacturing process is complicated. Furthermore, since only one type of logic signal can be applied to the gate electrode 12, a plurality of transistors are required to form a logic circuit, which hinders higher integration and higher speed of ICs.

Therefore, the present invention was invented in view of the above-mentioned problems, and it is possible to suppress the generation of hot carriers even if the channel length is short, and moreover, the number of transistors used can be reduced when constructing a logic circuit. The purpose is to provide an MO5 type transistor.

In order to achieve the above objectives, the present invention provides a gate electrode, an insulating film, a semiconductor layer, and a source electrode formed on the semiconductor layer.
An MO8 type transistor comprising a diffusion layer of a drain electrode is characterized in that the gate electrode is divided into a plurality of parts, and a connection terminal is connected to each of the divided gate electrodes.

Further, such an MO3 type transistor is characterized in that the diffusion layers of the source electrode and drain electrode are formed only directly under or outside of the gate electrodes located at both ends of the plurality of gate electrodes.

■ According to the above configuration of the present invention, the gate electrode is divided into a plurality of parts, and the connection terminal is connected to each of the divided gate electrodes, so that the voltage of each gate electrode can be controlled independently. .

Therefore, the voltage of the gate electrode, which is divided and arranged near the drain electrode where the electric field is extremely high, can be set to a voltage that causes less hot carrier generation.

Further, by applying different binary signals to each gate electrode, a logic circuit having inputs as many as the divided number of gate electrodes is formed.

impunity Embodiments of the present invention will be described below based on the drawings.

The embodiment shown in FIG. 1 is a micro MO3 type field effect transistor (MOS FET) constituting an LSI, and
n-channel MOSF whose semiconductor is P type (nMO3)
It is ET.

The structure of this MOSFET is as shown in FIG.
2 is formed, and three small-area gate electrodes 23 are formed on the upper surface of this insulating film 22, creating a structure in which a conventional single gate electrode is divided. In the upper layer of the semiconductor substrate 21, diffusion layers of a source electrode 24 and a drain electrode 25 are formed to face each other in the horizontal direction with a gate electrode 23 in between. A protective layer 26 is formed between each gate electrode 23 and around the gate electrode 23, and a metal electrode 27 is formed outside the periphery of this protective layer 26. An element isolation layer 28 made of Sing and an interphase insulating film 29 made of 5i02 are formed outside the metal electrode 27 and drain electrode 25 on the right side of the figure, and the metal electrode 27 and source electrode 24 on the left side of the figure. And each gate electrode 2 described above
3 are connected to connection terminals (not shown), respectively.

To explain each layer, the gate electrode 23 is formed of polycrystalline Si, for example, and the diffusion layers of the source electrode 24 and drain electrode 25 are formed into n-type by implanting impurities such as As, for example, by ion implantation. The protective layer 26 is formed of, for example, SiO□, phosphorous silicate glass, or the like. For example, an alloy of AI and Si is used for the metal electrode 27.

Connection terminals are respectively connected to the gate electrodes 23 as described above, and this MOSFET is represented by a symbol as shown in FIG. 1(b). An example of a logic circuit configured using this MOSFET is shown in FIG. 4(a), and this logic circuit is a NAND circuit.

Next, the operating principle of the above MOSFET will be explained. The operation of a typical MOS FET is that when a thin insulating film is sandwiched between the semiconductor substrate and the gate electrode and a voltage higher than the threshold voltage is applied, the band bending on the semiconductor surface increases and the surface layer becomes opposite to the substrate. An inversion layer having semiconductor properties is formed, and this inversion layer is used as a channel.

In this embodiment, a voltage is applied to the gate electrodes 23 at both ends (left and right outer sides in FIG. 1) of the three gate electrodes 23, and an inversion layer 30 is formed directly below them, as shown in FIG.

This inversion layer 30 is always formed regardless of whether the transistor is ON or OFF, and when the transistor is turned on and current flows, inversion layers are successively formed between the left and right inversion layers 30 to form the channel 31. It is assumed that it will be formed. If the inversion layer 30 is always formed in this way, the channel length will be shortened, which has the advantage of increasing the speed of operation.

When a voltage is applied to the gate electrode 23, a high electric field is generated near the drain electrode 25 below the rightmost gate electrode 23 in Figure 3, but by setting the gate voltage of the rightmost gate electrode 23 to a voltage that generates fewer hot carriers. Generation of hot carriers can be suppressed. Figure 5(a) shows the third
Figure (a) shows the relationship between the operating state of the NOT circuit and the amount of hot carriers generated; value), the amount of hot carriers generated is suppressed. On the other hand, in conventional MOS FETs, hot carriers (rising portion) are generated when the voltage changes, as shown in Figure 5(b).
is occurring.

By the way, in practical use of MOSFETs, the positions of the source electrode 24 and the drain electrode 25 are often changed by changing the source voltage and drain voltage.
In this embodiment, the gate voltage is fixed not only at the right end but also at the left end gate electrode 23 to cope with the generation of hot carriers near the left and right electrodes (diffusion layers). Therefore, at least three gate electrodes 23 are required to suppress the generation of hot carriers and to use the device as a logic element. The MOS FET of this example is shown in Figs. 3 and 4 (
As shown in a), by applying a binary signal to each gate electrode 23, it functions as a simple logic element (NAND circuit). Therefore, it functions similarly to a logic element in which a plurality of transistors are connected, and it is possible to achieve higher integration and higher speed of an IC.

By the way, conventionally, two gate electrodes are placed close to each other, and a source electrode and a drain electrode are formed on both sides of the gate electrode, and a diffusion layer of the source electrode and the drain electrode is also formed between the source electrode and the drain electrode. and this results in 2
A structure consisting of several transistors can be seen. However, since this type of transistor is simply a combination of two transistors, it occupies a large area. On the other hand, although the MOS FET of this embodiment functions as two or more transistors, there is no need to form a source/drain electrode diffusion layer between the source electrode 24 and the drain electrode 250. Therefore, the size of the transistor can be reduced, and the integration and speed of the IC can be increased.

Note that in this example, nMo5 was explained, but
It can also be implemented in pM OS, and also depletion type,
Of course, it can also be implemented in an enhancement form.

Also, regarding voltages that generate fewer hot carriers,
It is not limited to 5■.

As is clear from the above explanation, the MO according to the present invention
In the type 5 transistor, the gate electrode is divided into a plurality of parts, and a connection terminal is connected to each of the divided gate electrodes, so that the voltage of each gate electrode is controlled independently. Therefore, only the gate electrode in the vicinity of the drain electrode where the electric field is extremely high can be set to a voltage that causes less generation of hot carriers, and the generation of hot carriers can be suppressed. Furthermore, since each of the five divided gate electrodes is connected to a connecting terminal, by applying a different binary signal to each gate electrode, a logic circuit having the same number of inputs as the divided gate electrodes can be formed.

In this way, the MO3 type transistor according to the present invention is
Since one transistor is operated with multiple gate electrodes, short channel effects can be suppressed without forming an LDD structure, and
It has the same function as a logic element in which a plurality of transistors are connected, and as a result, it is possible to achieve higher integration and higher speed of an IC.

4. Ward l! Figure 1 (a) and (b) are drawings showing a MOSFET which is an embodiment of the MO3 type transistor according to the present invention, and (a) is a cross-sectional view showing its structure; (b) is a diagram showing an equivalent circuit, Figure 2 is a cross-sectional view to explain the state of use of MOSFET, Figure 3 (a) is an equivalent circuit diagram of a NOT circuit, and (b) is an input in that case. 4(a) and 4(b) show examples of logic circuits (NAND circuits) constructed using MOSFETs, (a) shows the MOSFETs of this example, (b) shows the conventional MOSFET, FIG. 5 is a graph showing the relationship between the gate voltage and the amount of hot carrier generation in the circuit operation of the NOT circuit, and (a) shows the MOSFET of the present example (7).
ET, (b) shows the conventional (7) MOSFET, Fig. 6 is a cross-sectional view showing the conventional MOSFET, Fig. 7 is a simplified cross-sectional view showing the phenomenon of hot carrier generation, and Fig. 8 is a hot carrier. A graph showing the generation amount of LDD, Figure 9
FIG. 2 is a cross-sectional view showing a transistor structure.

21... Semiconductor substrate (semiconductor layer), 22... Insulating film, 23... Gate electrode, 24... Source electrode, 25
...Drain electrode, 30...Inversion layer, 31...Channel

Claims (2)

[Claims] (1) In a MOS transistor consisting of a gate electrode, an insulating film, a semiconductor layer, and diffusion layers for source and drain electrodes formed in the semiconductor layer, the gate electrode is divided into a plurality of parts, and each of these divided gate electrodes is A MOS transistor characterized in that a connection terminal is connected to the MOS transistor. (2) The MOS transistor according to item 1, characterized in that the diffusion layers of the source and drain electrodes are formed only directly under or outside of the gate electrodes located at both ends of the plurality of gate electrodes. MOS type transistor.