JPH03105971A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a resistance of a body part and to increase a resistant amount to a latch-up of a parasitic thyristor by a method wherein a high- concentration P-type buried layer is formed at the lower part of a P-well of an N-channel type nonvolatile memory transistor which is operated in an avalanche region. CONSTITUTION:The following are formed on the same chip: a double-diffusion type output MOS transistor which forms a channel part by doubly diffusing a part 114 and a part 116 formed by mating use of a gate electrode layer 113 as a mask; and a floating-gate type nonvolatile memory transistor. During this process, a voltage drop by a Hall current flowing in a drain region is made to be a low resistance by using a first enclosure in a P-type region which is composed of a P-type buried layer 106 and a P-type diffusion layer 108. Thereby, it is possible to prevent that a parasitic thyristor which is constituted between the P-type region and a P-channel MOS transistor part is latched np.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor integrated circuit device in which a nonvolatile memory and a power MOSFET are formed on the same chip.
The present invention relates to a semiconductor integrated circuit device with increased latch-up resistance of a MOS section. [Prior Art] In an EPROM or a flash EEPROM in which hot electrons are injected into a floating circuit, in a write mode, a nonvolatile memory transistor is operated in an avalanche region to perform writing. In this mode, there is a phenomenon in which far more holes flow from the drain to the body than hot electrons flow to the gate. For this reason, nonvolatile memory transistors that utilize the above mechanism have a structure in which the body of the nonvolatile memory transistor is shared with the semiconductor substrate, reducing the resistance of the body portion and increasing the latch-up resistance of the parasitic thyristor. In addition, as a prior art related to the present invention, "Iya Fukuda, LM bit CMOS EPRON" HN
27C101” “HN27C301” Hitachi Review VO
L. 68 No. 7 (1986-7) J. [Problems to be Solved by the Invention] In the conventional example described above, a common P-type semiconductor substrate is used for the bodies of all N-channel MOS transistors including nonvolatile memory transistors to prevent latch-up. For this reason, an output MOS transistor (in the present invention, the source and body are connected and the body is connected like a single power MOSFET) and can be operated by raising the source potential higher than the substrate potential. , an MIS transistor whose source voltage can be driven to a level higher than the ground voltage is referred to as an output MOS transistor). The first object of the present invention is to provide an N-channel MMOS transistor that can be used for nonvolatile memory transistors that operate in the avalanche region and for source follower circuits that are not subject to the body bias effect.
An object of the present invention is to provide a semiconductor integrated circuit device in which OS transistors can be formed on the same chip, and a method for manufacturing the same. A second object of the present invention is to be able to freely set the potential of each terminal of both the N-channel MOS transistor and the P-channel MOS transistor, regardless of the presence or absence of a nonvolatile memory transistor, and furthermore, the source and body can be set freely. It is an object of the present invention to provide a semiconductor integrated circuit device and a method for manufacturing the same, in which output MOS transistors that do not deteriorate the current consumption ability by connecting and eliminating the substrate effect can be easily formed on the same chip.

[Means to solve the problem]

In order to achieve the first objective above, the P of an N-channel nonvolatile memory transistor operating in the avalanche region is
A heavily doped P-type buried layer is provided at the bottom of the well to reduce the resistance of the body part and take measures against latch-up. An output MOS transistor was formed in the separated P-type semiconductor region. Another method is to share the body of the N-channel nonvolatile memory transistor with the P-type semiconductor substrate, and the output MOS transistor has a double diffusion structure with the drain being the N-type semiconductor region separated by the P-type semiconductor substrate. It was formed with In order to achieve the second objective above, horizontal P-channel M
An OS transistor was formed in an N-well separated by a P-type semiconductor substrate, and a double-diffusion type N-channel MOS transistor was formed in an N-well separated by a P-type semiconductor substrate.

[effect] According to the present invention, in a semiconductor integrated circuit device in which a non-volatile memory transistor and an output MOS transistor coexist on the same chip, the latch-up resistance of a parasitic thyristor is improved, and further, the non-volatile memory transistor and This has the advantage that noise to the logic MOS transistor section can be prevented. Furthermore, according to the present invention, the potential of each terminal of both the N-channel MOS transistor and the P-channel MOS transistor can be freely set regardless of the presence or absence of a nonvolatile memory transistor, and furthermore, the source and body can be connected. By eliminating the substrate effect, it is possible to realize a semiconductor integrated circuit device in which output MOS transistors that do not deteriorate current drive capability can be easily formed on the same chip. 【Example】

Examples of the present invention will be described below. FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention. In this embodiment, an N-channel output MOS transistor is shown on the right side of the sectional view, a floating type nonvolatile memory transistor is shown in the center, and a P-channel MOS transistor is shown on the left side. A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described below. First, an N-type buried 110 is placed on a P-type semiconductor substrate 101.
2 and a P-type buried N103 is formed. Next, the N-type epitaxial layer 104 is lengthened to form an N-type buried layer 105 and a P-type buried layer 106. After that, the N-type epitaxial layer 107 is grown again, and the P-type diffusion IW108 reaching the P-type buried 1106 and the N-type diffusion /eJ109 reaching the N-type buried ffl05 are formed, and the body region of the P-channel MOS transistor is formed. An N-well diffusion M110, which will become the structure, and a P-well diffusion layer 111, which will become the body region of the N-channel floating nonvolatile MoS transistor, are formed. Thereafter, gate electrodes 11, 13, 115 and a P-type diffusion layer 114, which becomes a body region for a double-diffusion type N-channel output MOS transistor. , a highly doped N-type diffusion layer 116 that will become the source of the N-channel output MOS transistor and a highly doped P-type diffusion layer 17 that will become the source and drain regions of the P-channel MOS transistor are formed, and finally, the metal electrode layer 1 is formed.
This can be realized by forming 18. In this embodiment, a double diffusion type output MOS transistor and a nonvolatile memory transistor are formed on the same chip to form a channel part by double diffusion of transistors 114 and 116 formed using the gate electrode layer 113 as a mask. It is shown. To write data to the floating gate type nonvolatile memory transistor shown in the center of the figure, for example, 12.5 V is applied to the gate 115 and hot electrons are injected to the drain of the floating gate 113 of the nonvolatile memory transistor. However, at this time, a large number of holes flow from the drain to the body side. For this reason, conventional hot electron injection nonvolatile memory transistors use a common body and substrate to reduce resistance and prevent parasitic thyristor latch-up. In the case of this embodiment, the voltage drop due to the hole current flowing in the drain region is reduced between the P-type buried N106 and the P-type diffused layer 106.
By lowering the resistance in the first enclosure of the P-type region, latch-up of the parasitic thyristor formed between the P-channel MOS transistor section and the P-channel MOS transistor section is prevented. In addition, the double-diffusion type output MOS transistor on the right side of the figure is isolated by a second enclosure of the P-type region consisting of a P-type substrate 101, P-type buried M1, 03 and 106, and a P-type diffusion layer 108. Therefore, while the source and body are connected,
It is possible to operate the device by raising the source voltage above the ground voltage. An enclosure of the N-type semiconductor region composed of diffusion J'll05, 109 is placed between the first enclosure of the P-type semiconductor region and the second enclosure of the P-type region for element isolation of the output MOS transistor. The structure is such that these three regions are set at the lowest potential to prevent noise from the output MOS transistor from being applied to the nonvolatile memory transistor or CMOS logic section. Note that only the area surrounding the N-type semiconductor region may be set to a high potential. Note that since the P-type diffusion M108 used as an enclosure for the non-volatile memory transistor is provided to fix the potential of the P-type buried layer 106, there are some parts that do not surround the body of the non-volatile memory transistor. The effect remains unchanged. Regarding the enclosure of the N-type semiconductor region,
A portion of the N-type semiconductor layer enclosure can be removed within a range that does not interfere with noise countermeasures from output MOS transistors and the like. In addition, for the P-type diffusion layer 1108 and the N-type diffusion layer 109 (or the N-type diffusion layer N109 and the N-type buried layer 105), an insulating layer is provided on the side wall of the trench, and metal, alloy, or low-resistance polycrystalline silicon is buried. It may be replaced with a conductor. According to the semiconductor integrated circuit device of this embodiment, both the upper arm element and the lower arm element of a bridge circuit such as a motor drive are basically the output transistors shown in this figure, and the on-resistance is small and the current drive capacity is high. Large N-channel power MO
This can be realized using SFET. Furthermore, the operation of this output power MOSFET varies depending on the data stored in advance in the nonvolatile memory formed on the same chip, even if the same input is input to this semiconductor integrated circuit. It has the advantage of being programmable to do so. FIG. 2 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention. In this embodiment as well, the N-channel output MOS transistor is shown on the right side of the sectional view, the floating type nonvolatile memory transistor is shown in the center, and the P-channel MOS transistor is shown on the left side. A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described below. First, a heavily doped N-type buried layer 202 is formed on a P-type semiconductor substrate 201, and after diffusion, a P-type buried layer N203 is formed. Here, by using antimony or arsenic as the impurity for the N-type buried layer 202 and using boron as the impurity for the P-type buried FM 203, the P-type epitaxial layer 2
By lengthening 08 and adding a heat process,
As for the final shape, it is possible to increase the upward diffusion length of the P-type buried layer 203 of boron, which has a larger diffusion coefficient than arsenic or antimony. Therefore, in this embodiment, the P-type region 2 surrounding the body of the nonvolatile memory transistor is
03, 205 and N-type regions 202, 206 can be formed. Next, an N-well diffusion layer 207 that will become the body region of the P-channel MOS transistor and a P-well diffusion layer 208 that will become the body region of the N-channel MOS transistor are formed. After that, gate electrode layers 210 and 212, a P-type diffusion 9211 which becomes a body region for a double-diffusion type output MOS transistor, a high concentration N-type diffusion N213 which becomes a source of an N-channel MOS transistor, and a source of a P-channel MOS transistor. , a highly doped P-type expansion @ which becomes the drain region
This can be achieved by forming the layer 214 and finally forming the metal electrode layer 215. FIG. 3 is a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention. In this embodiment, an N-channel output M○S transistor whose drain is the substrate is shown on the right side of the sectional view, a bloating type nonvolatile memory transistor is shown in the center, and a P-channel MOS transistor is shown on the left side. A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described below. First, a heavily doped N-type buried layer M302 is formed on an N-type semiconductor substrate 301, and a P-type epitaxial layer 303 is grown. Next, a high concentration N type buried layer 304 and a high concentration P type buried layer 305 are formed. An N-type epitaxial layer N306 is grown, and then a high concentration P-type diffusion N307 and a high concentration N-type diffusion layer 308 are formed to form an N-well diffusion layer 309 which will become the body region of the P-channel MOS transistor and the body of the N-channel MOS transistor. A P well 310 is formed as a region. After that, the gate electrode layer 312,
314. A P-type diffusion layer 313 that becomes a body region for a double-diffusion type N-channel output MOS transistor, a high concentration N-type diffusion layer 315 that becomes a source and drain of an N-channel MOS transistor, and a source of a P-channel MOS transistor. This can be achieved by forming the highly concentrated P-type diffusion layer 316, which will become the drain region, and finally forming the metal electrode layer 316. In this embodiment, the N-type semiconductor substrate 301 is used as the drain of the output M○S transistor, and the P-type epitaxial region 303
is set to ground potential, and non-volatile memory and CMO
The structure is such that it is possible to form elements that require element isolation using a P-type diffusion layer, such as an S logic section or a bipolar transistor. In addition, in this embodiment, in order to reduce the resistance of the body of the nonvolatile memory transistor, a P-type buried M30 is used at the bottom of the body.
5 and a P-type diffusion layer 307 on the side surface of the body. FIG. 4 is a sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. In this embodiment as well, the N-channel output MOS transistor is shown on the right side of the sectional view, the floating type nonvolatile memory transistor is shown in the center, and the P-channel MOS transistor is shown on the left side. A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described below. First, a heavily doped P-type buried layer 402 is formed on an N-type semiconductor substrate 401, and a P-type epitaxial layer 403 is grown. After that, a high concentration N-type diffusion layer 4 for element isolation is added.
A high concentration P type diffusion M404 is formed so as to reach the P type buried layer 402. Next, an N-well diffusion layer 406, which will become the body region of the P-channel MOS transistor, and a P-well diffusion N407, which will become the body region of the N-channel MOS transistor, are formed. After that, the gate electrode layer 409,
411, Low concentration N-type expansion for high voltage N-channel MOS transistor [410, High concentration N-type diffusion layer 412 which becomes the source and drain of the N-channel MOS transistor and P-channel M. This can be achieved by forming a heavily doped P-type diffusion layer 413 that will become the source and drain regions of the OS transistor, and finally forming a metal electrode layer 414. In this embodiment, in order to reduce the resistance of the body of the nonvolatile memory transistor, a P-type diffusion 7!402 at the bottom of the body and a P-type diffusion M404 at the side surface of the body are provided. Separation from the N-channel output MOS transistor is performed by an N-type substrate 401 and an N-type diffusion layer 405. FIG. 5 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. In this embodiment as well, the N-channel output MOS transistor is shown on the right side of the sectional view, the floating type nonvolatile memory transistor is shown in the center, and the P-channel MOS transistor is shown on the left side. A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described below. First, a heavily doped N-type buried layer 502 and a heavily doped P-type buried layer 503 are formed on a P-type semiconductor substrate 501, and an N-type epitaxial layer M504 is lengthened. After that, the high concentration P type diffusion layer 505 and N
A high concentration N type diffusion layer 506 is formed to reach the type buried layer 502.
Next, N-well diffusion/il507. which becomes the body region of the P-channel MOS transistor is formed. P-well diffusion 1 which becomes the body region of the N-channel MOS transistor
508 is formed. After that, the gate electrode, Ii510,
512, and a P-type diffusion N511 for the channel of the double-diffused N-channel MOS transistor.
High concentration N type diffusion layer 513 which becomes the source of the S transistor
This can be achieved by forming highly concentrated P-type diffusions 1514 that will become the source and drain regions of a P-channel MOS transistor, and finally forming a metal electrode layer 515. In this example, in order to reduce the resistance of the P-type body of the nonvolatile memory transistor, a P-type buried layer 503 at the bottom of the body and a P-type diffusion layer 505 on the side surface of the body are provided, and by further connecting to the P-type substrate, the nonvolatile The body resistance of the memory transistor is reduced. Isolation from the N-channel output MOS transistor is performed by N-type buried/I502 and N-type diffusion M506. FIG. 6 is a sectional view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention. In this embodiment as well, the N-channel output MOS transistor is shown on the right side of the sectional view, the floating type nonvolatile memory transistor is shown in the center, and the P-channel MOS transistor is shown on the left side. A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described below. First, a deep, heavily doped N-type burying M602 is formed on a P-type semiconductor substrate 601. This is formed deeply so that the impurity concentration peak is deeper than the surface by a so-called retrograde method in which boron is diffused and then b-choline is diffused to cancel it out. Next, P channel M
N well diffusion N6 which becomes the body region of the OS transistor
03, a P-well diffusion layer 604 is formed to become the body region of the N-channel MOS transistor. After that, gate electrodes 11606, 608, double diffusion type N
After forming the P-type diffusion layer 607 that will become the channel of the channel MOS transistor, if necessary, form the N-type diffusion layer 608 for the offset drain of the high-voltage lateral N-channel MOS transistor, and the highly doped N-type diffusion layer 608 that will become the source and drain of the N-type diffusion layer. This can be achieved by forming an N-type expanded vlN 609 and a heavily doped P-type diffusion #610 that will become the source and drain regions of the P-channel MOS transistor, and finally forming a metal electrode layer 611. In this embodiment, by connecting the P-type body of the nonvolatile memory transistor to the P-type semiconductor substrate 601, the resistance of the body part is lowered, and at the same time, the source voltage is raised above the ground voltage on the same chip. The output MOS transistor that can be used is a horizontal double-diffusion type N-channel MOS transistor whose drain is an N-type diffusion 1602 separated by a P-type substrate. Note that according to this semiconductor structure, a horizontal P-channel MOS
A transistor can be formed in an N-well separated by a P-type semiconductor substrate, and a double diffusion type N-channel MOS transistor can be formed in an N-well separated by a P-type substrate. Therefore, the potential of each terminal can be freely set for both N-channel MOS transistors and P-channel MOS transistors.Furthermore, by connecting the source and body to eliminate the substrate effect, the output does not deteriorate the current gap capability. MOS transistors can be easily formed on the same chip. The effectiveness of this embodiment is independent of the presence or absence of nonvolatile memory.

【Effect of the invention】

According to the present invention, a non-volatile memory transistor and an output M
In semiconductor integrated circuit devices in which OS transistors coexist on the same chip, the latch-up resistance of parasitic thyristors can be improved, and furthermore, it is possible to prevent noise from the operation of output MoS transistors to nonvolatile memory transistors and logic MOS transistors. effective. Further, according to the present invention, regardless of the presence or absence of a nonvolatile memory transistor, each terminal potential can be freely set for both an N-channel MoS transistor and a P-channel MOS transistor, and furthermore, the source and body can be connected. By eliminating the substrate effect, it is possible to easily form an output MOS transistor on the same chip without deteriorating the current drive capability.

[Brief explanation of drawings]

1 to 6 are sectional views of essential parts of semiconductor integrated circuit devices according to embodiments of the present invention, respectively. Explanation of symbols 101, 201, 501, 601...
...P-type semiconductor substrate 301, 401
......N-type semiconductor substrate 102, 105
,202,302,304,502...
...N-type buried layer 103, 106, 203, 30
5,402,503・・・・・・・・・・・・P
Mold embedding layer 104, 107, 204, 303, 306, 5
04・・・・・・・・・・・・N-type epitaxial layer 403 ・・・・・・・・・・・・・・・
・P-type epitaxial layer 108, 11 1, 11
4, 117, 205, 208, 211, 2
14, 307, 310, 313, 404, 407,
413,505,508,511,514,604,6
07,610...P-type diffusion layer 109, 110, 116, 206, 207
, 213, 308, 309, 315, 4
05,406,410,412,506,507,51
3,602,603,609...N type diffusion layer 112,
209,311,408,509,605...
......Insulating layer 113, 1
15, 210, 212, 312, 314, 316
, 409, 4]. 1, 510, 512,606
,608,611・・・・・・・・・・・・・・・
......Gate electrode layer 118, 215
,414,515・・・・・・・・・・・・・・・
・・・・・・・・・Metal electrode layer Fig. 1 Fig. 3 Fig. 2 No. θta Jθ5 101 jθ3 Jθ2 304 Sheep 4 Fig. 4σl 4θl 403

Claims (1)

[Claims] 1. A first MIS transistor and a nonvolatile memory transistor whose source and body are connected and whose source voltage can be driven to a ground voltage or higher are formed on the same chip. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the nonvolatile memory transistor has a mode of operation in an avalanche region. 3. providing a first high concentration buried layer of a first conductivity type below the body (first conductivity type) of the nonvolatile memory transistor;
3. The semiconductor integrated circuit device according to claim 1, wherein the body region has a low resistance. 4. A second semiconductor region of the first conductivity type is provided from the main surface of the semiconductor so as to reach the first high concentration buried layer of the first conductivity type of the nonvolatile memory transistor. A semiconductor integrated circuit device according to any one of claims 1 to 3. 5. A peripheral portion of the body region of the nonvolatile memory transistor is surrounded by the first high concentration buried layer of the first conductivity type and the second semiconductor region of the first conductivity type. A semiconductor integrated circuit device according to any one of claims 1 to 4. 6. The semiconductor integrated circuit device according to claim 1, wherein the outside of the body region of the nonvolatile memory transistor is surrounded by a first conductivity type semiconductor layer of a second conductivity type. 7. The semiconductor integrated circuit device according to claim 6, wherein a MIS transistor other than the nonvolatile memory transistor is also formed in a region surrounded by the first conductivity type semiconductor layer of the second conductivity type. 8. The semiconductor integrated circuit device according to claim 1, wherein the body region of the nonvolatile memory transistor is connected through a semiconductor layer of the same conductivity type as the semiconductor substrate. 9. The semiconductor integrated circuit device according to claim 1, wherein the drain of the first MIS transistor is formed of a part of a semiconductor substrate. 10. The first MIS transistor is an N-channel MIS transistor.
10. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is an S transistor. 11. The first MIS transistor is a double diffusion type M
11. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is an IS transistor. 12. Instead of the second semiconductor region of the first conductivity type,
12. The semiconductor integrated circuit device according to claim 4, further comprising a conductor region whose side surfaces are surrounded by an insulating layer and in which a metal, alloy, or low-resistance polycrystalline silicon layer is embedded. 13. A part of the enclosure of the first conductivity type semiconductor layer of the second conductivity type provided outside the body region of the nonvolatile memory transistor is surrounded by an insulating layer on the side surface, and is made of a metal, an alloy, or a low-resistance polyester. 13. A semiconductor integrated circuit device according to claim 6, characterized in that a conductor region in which a crystalline silicon layer is buried is used. 14. Claims 1 to 13, characterized in that the operation of the first MIS transistor is made variable according to data stored in advance in the nonvolatile memory.
The semiconductor integrated circuit device described in . 15. A horizontal P-channel MIS transistor is formed in an N-well separated by a P-type substrate, and a double-diffused N-channel MIS transistor is formed in an N-well separated by a P-type substrate. Semiconductor integrated circuit device.