JP2000058846A - Field-effect transistor and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance an operating speed without causing reduction in breakdown voltage in a method for driving a sub-gate field-effect transistor for use in a high breakdown-voltage thin film circuit. SOLUTION: This method for driving a field-effect transistor comprises a semiconductive layer 12 in which a source region 41 along a current path, an active region 31, an off-set region 33, and a drain region 42 are arranged in this order; a gate electrode 21 formed on a gate insulation film on the active region 31; and a sub-gate electrode 23 formed by sandwiching a sub-gate insulation film ranging from the gate electrode 21 to the off-set region. At this time, a pulse-like input signal is applied on the gate electrode 21, and also a pulse-like input signal which is independent from the input signal to the gate electrode 21 and synchronizes with the input signal to the gate electrode 21 is applied on the sub-gate electrode 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method of driving the same, and more particularly, to a sub-gate type field effect transistor used in a high withstand voltage thin film circuit and a method of driving the same.

[0002]

2. Description of the Related Art There is a demand for an insulated gate field effect transistor used in a high withstand voltage thin film circuit to operate at a high voltage without lowering the operation speed. Conventionally, this type of field-effect transistor has been described in Electron Device Letter, June 1996, Vol.11, No.6, p.244, Fig.
1 (IEEE ELECTRON DEVICE LETTERS, Vol.11, No.6, JU
NE 1990) is known and is called a so-called sub-gate structure field effect transistor.
Its main configuration is that an offset region is provided between the active region and the drain region, and a sub-gate electrode is provided so as to cover at least the gate electrode end portion and the offset region adjacent to the gate electrode end portion with the sub-gate insulating film interposed therebetween. ing. FIG. 14 is a cross-sectional view showing a configuration of a sub-gate type nMOS transistor used in a conventional high withstand voltage thin film circuit. As shown in FIG. Is formed, and a semiconductor layer 112 patterned to a required size is formed on the insulating base layer 111.
The semiconductor layer 112 includes an n-type source region 141 along the current flow path, an active region 131 not doped with impurities,
An offset region 133 not doped with an impurity and an n-type drain region 142 are provided in this order. A source electrode 145 is provided on the source region 141 via a contact plug, a drain electrode 146 is provided on the drain region 142 via a contact hole,
Each is provided. A first interlayer insulating film 151 is formed to cover the active region 131 and the offset region 133, and a gate electrode 121 is formed on the active region 131 with the first interlayer insulating film 151 interposed therebetween. Active area 131
First interlayer insulating film 151 sandwiched between gate electrode 121 and gate electrode 121
Becomes a gate insulating film. Further, a second interlayer insulating film 152 is formed to cover the gate electrode 121. Sub-gate electrode 123 is formed on offset region 133 with first interlayer insulating film 151 and second interlayer insulating film 152 interposed therebetween. Offset region 133 and sub-gate electrode 12
The first interlayer insulating film 151 and the second interlayer insulating film 152 sandwiched between the three become the sub-gate insulating film.

FIG. 15 shows the structure of the nMOS transistor 20.
FIG. 2 is a circuit diagram of an nMOS inverter using No. 1. In this figure, the source electrode 145 is connected to the ground connection terminal 16.
1 to the ground line. Drain electrode 146 is connected to a positive power supply line via load resistance 170 and power supply connection terminal 162. Output terminal 16
3 is connected to the drain electrode 146 and outputs a voltage _VOUT . 15, the same components as those in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted.

[0004] In the nMOS transistor 201, it is possible to control the conductivity of the offset region 133 by applying a sub-gate voltage _{V FN} to sub-gate electrode 123. FIG. 16 is a timing chart for driving the sub-gate field effect transistor.
By applying a constant sub-gate voltage V _FN to the sub-gate electrode 123 and switching the gate voltage V _N between a low level and a high level, each of the nMOS transistors 20
Turn 1 off and on. In the above known example, as shown in FIG. 16, by setting the sub-gate voltage V _FN applied to the sub-gate electrode 123 to a voltage slightly higher than half of the drain voltage, the drain region 142 is turned off when the nMOS transistor 201 is in the off state. Can be formed near the boundary between the active region 131 and the offset region 133 and near the boundary between the offset region 133 and the drain region 142 to improve the breakdown voltage characteristics. Further, by applying a sub-gate voltage V _FN in the sub-gate electrode 123, field effect transistor resistance of the offset region 133 when the ON state is lower than the state without added sub-gate voltage V _FN. In addition, since formation of a depletion layer due to a lateral electric field can be suppressed, on-current can be improved.

[0005]

Incidentally, in such a sub-gate structure nMOS transistor 201,
An attempt to obtain a high ON current in order to further increase the operating speed, it is necessary to increase the sub-gate voltage V _FN. However, when the sub-gate voltage _VFN is increased, the offset region 133 is in an inverted state even when the transistor is turned off.
1 and the electric field intensity near the boundary between the offset region 133 and the offset region 133 increase. Therefore, there is a problem that the breakdown voltage is reduced when the nMOS transistor 201 is in the off state. Moreover,
Since the potential difference between the gate electrode 121 and the sub-gate electrode 123 increases, the maximum value of the voltage that can be applied to the sub-gate electrode 123 is
Is limited by the pressure resistance of

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a field effect transistor capable of improving the operation speed without causing a decrease in withstand voltage and a driving method thereof. .

[0007]

According to a first aspect of the present invention, there is provided a method of driving a field effect transistor, comprising a source region, an active region, and an offset region along a current flow path. A semiconductor layer provided with a drain region, a gate electrode formed on the gate insulating film on the active region, and at least the gate extending from the gate electrode to the offset region and sandwiching a sub-gate insulating film. According to a method for driving a field effect transistor having a sub-gate electrode formed so as to cover a part of the offset region adjacent to an end of an electrode and an end of the gate electrode, a pulse-like input signal is supplied to the gate electrode. And a pulse-shaped input signal independent of the input signal to the gate electrode and synchronized with the input signal to the gate electrode. It is characterized in that applied to the gate electrode.

According to a second aspect of the present invention, there is provided the driving method of the field effect transistor according to the first aspect, wherein a voltage level of an input signal applied to the sub-gate electrode is different from a voltage level of an input signal to the gate electrode. It is characterized by.

According to a third aspect of the present invention, there is provided the driving method of the field-effect transistor according to the second aspect, wherein the source region and the drain region of the field-effect transistor are of n-conductivity type, and when the field-effect transistor is off. The low level of the input signal applied to the sub-gate electrode is higher than the low level of the pulse signal applied to the gate electrode, and the high level of the input signal applied to the sub-gate electrode when the field effect transistor is on is higher than the gate electrode. , Which is higher than the high level of the input signal applied to.

According to a fourth aspect of the present invention, there is provided the driving method of the field effect transistor according to the third aspect, wherein the low level of the input signal applied to the sub-gate electrode in the off state of the field effect transistor corresponds to the offset region. The depletion voltage is a high level of an input signal applied to the sub-gate electrode when the field-effect transistor is on, which is a voltage at which an n-type conductive layer is formed at least in the offset region.

According to a fifth aspect of the present invention, there is provided the driving method of the field effect transistor according to the second aspect, wherein a source region and a drain region of the field effect transistor are of a p-type, and when the field effect transistor is in an off state. The high level of the input signal applied to the sub-gate electrode is lower than the high level of the pulse signal applied to the gate electrode, and the low level of the input signal applied to the sub-gate electrode when the field-effect transistor is on is the low level of the gate electrode. , Which is lower than the low level of the input signal applied to.

According to a sixth aspect of the present invention, there is provided a driving method of the field effect transistor according to the fifth aspect, wherein a high level of an input signal applied to the sub-gate electrode when the field effect transistor is in an off state, and the offset region has a high level. The depletion voltage is a voltage at which a low level of an input signal applied to the sub-gate electrode when the field-effect transistor is on is a voltage at which a p-type conductive layer is formed in the offset region.

According to a seventh aspect of the present invention, there is provided a field effect transistor, comprising: an n-type first source region, a first active region, a first offset region,
a first semiconductor layer provided with an n-type first drain region; a first gate electrode formed on a first gate insulating film on the first active region; From the gate electrode to the first offset region, and at least an end of the first gate electrode and the first offset adjacent to an end of the first gate electrode with a first sub-gate insulating film interposed therebetween. An n-type field effect transistor having a first sub-gate electrode formed so as to cover a part of the region, a p-type second source region along a current flow path, a second active region, A second semiconductor layer provided with a second offset region, a p-type second drain region, and a second gate formed on a second gate insulating film on the second active region. An electrode and the second offset from the second gate electrode. Over the gate region and at least the end of the second gate electrode and a part of the second offset region adjacent to the end of the second gate electrode with the second sub-gate insulating film interposed therebetween. A p-type field-effect transistor having a second sub-gate electrode formed on the n-type field-effect transistor and the p-type field-effect transistor.
A field-effect transistor connecting the first drain region and the second drain region in cascade, connecting the first gate electrode to the second sub-gate electrode, and Is connected to the first sub-gate electrode.

According to an eighth aspect of the present invention, there is provided a driving method of the field effect transistor according to the seventh aspect, wherein a pulse-like input signal is applied to the first gate electrode or the second sub-gate electrode, and The pulse-shaped input signal independent of the input signal to the first gate electrode or the second sub-gate electrode and synchronized with the input signal to the first gate electrode or the second sub-gate electrode is output to the second gate electrode. It is characterized in that the voltage is applied to the gate electrode or the first sub-gate electrode.

According to a ninth aspect of the present invention, there is provided a driving method of the field effect transistor according to the eighth aspect, wherein a voltage level of an input signal applied to the second gate electrode or the first sub-gate electrode and the first level are controlled. The voltage level of the input signal to the gate electrode or the second sub-gate electrode is different.

According to a tenth aspect of the present invention, there is provided the driving method of the field effect transistor according to the ninth aspect, wherein the low level of the input signal applied to the second gate electrode or the first sub-gate electrode is the first level. Gate electrode or the second
And the high level of the input signal applied to the second gate electrode or the first sub-gate electrode is higher than the low level of the pulse signal applied to the first sub-gate electrode.
Or higher than the high level of the input signal applied to the gate electrode or the second sub-gate electrode.

According to an eleventh aspect of the present invention, there is provided the driving method of the field effect transistor according to the tenth aspect, wherein the low level of the input signal applied to the first gate electrode or the second sub-gate electrode is equal to the low level of the input signal. 2 in the offset area
The n-type field effect transistor is turned off, and the low level of the input signal applied to the second gate electrode or the first sub-gate electrode is set to the first offset region. Is a voltage at which the p-type field effect transistor is turned on, and the high level of the input signal applied to the first gate electrode or the second sub-gate electrode causes the second offset region to be depleted. And a voltage at which the n-type field effect transistor is turned on, and the second gate electrode or the first
High level of the input signal applied to the sub-gate electrode of
An n-type conductive layer is formed in the first offset region, and the p-type field effect transistor is turned off.

According to a twelfth aspect of the present invention, there is provided a driving method of a field-effect transistor, wherein an n-type first transistor is provided along a current flow path.
A first active region, a first active region, a first offset region, and an n-type first drain region.
A first gate electrode formed on a first gate insulating film on the first active region; a first gate electrode extending from the first gate electrode to the first offset region; At least the first
An n-type field effect transistor having a first sub-gate electrode formed so as to cover an end of the gate electrode and a part of the first offset region adjacent to the end of the first gate electrode; A second semiconductor layer provided with a p-type second source region, a second active region, a second offset region, and a p-type second drain region along the current flow path; A second gate electrode formed on the second gate insulating film on the second active region, and a second sub-gate insulating film extending from the second gate electrode to the second offset region. A p having a second sub-gate electrode formed so as to cover at least an end of the second gate electrode and a part of the second offset region adjacent to the end of the second gate electrode. Type field effect transistor A method of driving a cascade-connected field-effect transistor by connecting one drain region and the second drain region, wherein the first gate electrode, the first sub-gate electrode, the second gate electrode, and the second It is characterized in that mutually independent and synchronized pulse-like input signals are applied to the two sub-gate electrodes.

According to a thirteenth aspect of the present invention, there is provided the driving method of the field effect transistor according to the twelfth aspect, wherein a voltage level of an input signal applied to the first sub-gate electrode and an input signal applied to the first gate electrode are provided. A voltage level of a signal is different, and a voltage level of an input signal applied to the second sub-gate electrode is different from a voltage level of an input signal to the second gate electrode.

According to a fourteenth aspect of the present invention, there is provided the driving method of the field effect transistor according to the thirteenth aspect, wherein the p-type field effect transistor is on when the n-type field effect transistor is off, and the n-type field effect transistor is on. It is characterized in that the p-type field effect transistor is off when the type field effect transistor is on.

According to a fifteenth aspect of the present invention, there is provided a driving method of the field effect transistor according to the thirteenth or fourteenth aspect, wherein a low level of an input signal applied to the first sub-gate electrode when the n-type field effect transistor is off. The level is higher than the low level of the pulse signal applied to the first gate electrode, and the high level of the input signal applied to the first sub-gate electrode in the ON state of the n-type field effect transistor is higher than the first gate electrode. And the high level of the input signal applied to the second sub-gate electrode in the off state of the p-type field effect transistor is higher than the high level of the input signal applied to the second gate electrode. Lower and applied to the second sub-gate electrode in the ON state of the p-type field effect transistor That the low level of the input signal is the second
, Which is lower than the low level of the input signal applied to the gate electrode.

The invention according to claim 16 is the first invention.
5. The method for driving a field-effect transistor according to item 5, wherein the first transistor is turned off when the n-type field-effect transistor is off.
The low level of the input signal applied to the sub-gate electrode of
The first offset region has a depletion voltage, and a high level of an input signal applied to the first sub-gate electrode when the n-type field-effect transistor is on is at least n-type in the first offset region. A voltage at which a conductive layer is formed, and a high level of an input signal applied to the second sub-gate electrode in an off state of the p-type field effect transistor is a voltage at which the second offset region is depleted; The low level of the input signal applied to the second sub-gate electrode in the ON state of the p-type field effect transistor is a voltage at which a p-type conductive layer is formed in the second offset region.

[0023]

According to the method of driving a field effect transistor of the present invention, a pulse-like input signal is applied to the gate electrode of the sub-gate type field effect transistor, and the input signal to the gate electrode is independent of the input signal to the gate electrode. A synchronized pulse-like input signal is applied to the sub-gate electrode.
Therefore, by adjusting the voltage applied to the sub-gate electrode independently of the voltage applied to the gate electrode, the state of the offset region can be switched according to the off state or the on state of the transistor. By applying an electric field to the offset region through the sub-gate electrode, the width of the depletion layer formed in the offset region by the lateral electric field can be controlled. By expanding the depletion layer, the maximum electric field is reduced and the withstand voltage is improved.

When the transistor is turned on, the active region is inverted and carriers are induced. At this time, by applying a voltage that is a potential between the gate potential and the drain potential to the sub-gate electrode and inverting the offset region, carriers are induced in the offset region, the resistance of the offset region is reduced, and the offset region is turned on. The current can be increased. In this case, the breakdown voltage decreases, but when the transistor is turned on, the output voltage of the inverter decreases. Therefore, the required withstand voltage is reduced because the drain voltage of the transistor is reduced. According to the electric field of the present invention, the above method is used to drive an n-type field effect transistor and a p-type field effect transistor so that when one is on, the other is off, and when one is off, the other is on. The present invention can be applied to a driving method of an effect transistor. In this case, as in the above case, the withstand voltage can be improved and the operation speed can be increased.

In the field-effect transistor of the present invention, the n-type field-effect transistor and the p-type field-effect transistor are such that when one is on, the other is off, and when one is off, the other is on. When driven so that the low level of the input signal applied to the second gate electrode or the first sub-gate electrode is higher than the low level of the pulse signal applied to the first gate electrode or the second sub-gate electrode, The high level of the input signal applied to the second gate electrode or the first sub-gate electrode is the first level.
By driving the input signal applied to the gate electrode or the second sub-gate electrode to be higher than the high level, carriers are induced in the offset region when both the n-type field-effect transistor and the p-type field-effect transistor are on, In the off state, the electric field can be reduced by the offset region. As a result, the withstand voltage can be improved and the operation speed can be increased.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a sectional view showing a configuration of a sub-gate type nMOS transistor according to a first embodiment of the present invention.
Is a circuit diagram of an nMOS inverter using the same nMOS transistor, and FIG. 3 is a timing chart showing an operation of the same nMOS inverter. First, the same nMOS
The structure of the transistor will be described. This form of nMOS
The transistor 101 is of a sub-gate type suitable for use in a high withstand voltage thin film circuit, and as shown in FIG.
An insulating underlayer 11 is formed thereon, and a first semiconductor layer 1 patterned to a required size on the insulating underlayer 11
2 are formed. In the first semiconductor layer 12,
An n-type source region 41, an active region 31 not doped with impurities, an offset region 33 not doped with impurities, and an n-type drain region 42 are provided along the current flow path in this order. A first interlayer insulating film 51 is formed to cover the active region 31 and the offset region 33, and a gate electrode 21 is formed on the active region 31 with the first interlayer insulating film 51 interposed therebetween. Active region 31 and gate electrode 2
The first interlayer insulating film 51 sandwiched between the first and second insulating films 51 serves as a first gate insulating film.

Further, a second interlayer insulating film 52 is formed to cover the gate electrode 21. Sub-gate electrode 23 is formed on offset region 33 with first interlayer insulating film 51 and second interlayer insulating film 52 interposed therebetween. The first interlayer insulating film 51 and the second interlayer insulating film 52 sandwiched between the offset region 33 and the sub-gate electrode 23 become the first sub-gate insulating film. Further, a source electrode 45 is connected to the source region 41 through a contact hole, and a drain electrode 46 is connected to the drain region 142 through a contact hole.
Is connected.

Next, an nMOS inverter according to this embodiment will be described. This nMOS inverter,
As shown in FIG. 2, the nMOS transistor 101 and the load resistor 70 are schematically constituted. The source electrode 45 of the nMOS transistor 101 is connected to the ground line via the ground connection terminal 61, and the drain electrode 46 is connected to the load resistor 70. And a positive power line via a power connection terminal 62. Further, an output terminal 63 is connected to the drain electrode 46 without passing through the load resistor 70, and outputs the voltage _VOUT .

Next, with reference to FIG.
The operation of the S inverter will be described. Gate electrode 21
Gate voltage (input signal) _{V N} to be applied to the case of the low level _{V NL,} nMOS transistor 101 is turned off. In this case, the sub-gate voltage V _FN is optimized, the width of the depletion layer formed in the offset region 33 is controlled by the lateral electric field, and the sub-gate voltage V
_Change to _FNL . This sub-gate voltage V _FNL becomes higher than the low level of the gate voltage V _N. As a result, the peak of the lateral electric field is divided near the boundary between the drain region 42 and the offset region 33 and near the boundary between the offset region 33 and the active region 31, and the withstand voltage is improved. When the nMOS transistor 101 is off, n
Voltage substantially equal V to the output terminal 63 connected to the drain electrode 46 of the MOS transistor 101 and the power supply voltage _{V D D
OUT} is output. Next, a pulse-like gate voltage V _N
Is changed from the low level V _NL to the high level V _NH , the sub-gate voltage V _FN is also changed from the low level V _FNL to the high level V _FNH in synchronization with the gate voltage V _N.

At this time, the sub-gate voltage V _FNH is set higher than the gate voltage V _NH , and a voltage is applied such that an n-type conductive layer is formed in the offset region 33 immediately below the sub-gate electrode 23. Thereby, electrons are generated in the offset region 33 and the resistance of the offset region 33 is reduced.
A higher ON current can be obtained. nMOS transistor 1
01 the on state, substantially equal to voltage _{V OUT} and the ground voltage _{V SS} is an output terminal 63 connected to the drain electrode 46 of the nMOS transistor 101 is output. The pulse signal to the gate electrode 21 may be a signal obtained by level-converting the gate signal to the sub-gate electrode 23 by a level shift circuit.

As described above, according to this embodiment, when the transistor 101 is off, the breakdown voltage is improved by controlling the width of the depletion layer formed in the offset region 33. Further, in the ON state, as the sub-gate voltage rises, electrons are induced in the offset region 33 immediately below the sub-gate electrode 23, and the resistance of the offset region 33 decreases, so that the switching characteristics are improved.

Second Embodiment FIG. 4 is a sectional view showing the structure of a sub-gate type pMOS transistor according to a second embodiment of the present invention.
Is a circuit diagram of a pMOS inverter using the pMOS transistor, and FIG. 6 is a timing chart showing the operation of the pMOS inverter. The structure of this pMOS transistor is substantially the same as that shown in FIG. 1 if the n-type is changed to p-type.
In FIG. 2, as shown in FIG. 4, an insulating base layer 11 is formed on the glass substrate 1, and a second semiconductor layer 13 patterned to a required size is formed on the insulating base layer 11. . The second semiconductor layer 13 has p
Source region 44, active region 32 not doped with impurities, offset region 34 not doped with impurities,
A p-type drain region 43 is provided in this order. A first interlayer insulating film 51 is formed to cover the active region 32 and the offset region 34, and a first interlayer insulating film 51 is formed on the active region 32.
The gate electrode 22 is formed with the interlayer insulating film 51 therebetween. The first interlayer insulating film 51 sandwiched between the active region 32 and the gate electrode 22 serves as a second gate insulating film. Further, a second interlayer insulating film 52 is formed to cover the gate electrode 22. Sub-gate electrode 24 is formed on offset region 34 with first interlayer insulating film 51 and second interlayer insulating film 52 interposed therebetween. The first interlayer insulating film 51 and the second interlayer insulating film 51 sandwiched between the offset region 34 and the sub-gate electrode 24
Is the second sub-gate insulating film. Further, a source electrode 47 is provided on the source region 44 via a contact hole, and a drain electrode 48 is provided on the drain region 43 via a contact hole.

Next, the circuit configuration of the pMOS inverter will be described with reference to FIG. In this pMOS transistor 102, as shown in FIG.
Is connected to a positive power line via a positive power connection terminal 62. The drain electrode 48 is connected to the load resistance 17.
0 and the ground connection terminal 61 are connected to the ground line. The output terminal 63 is connected to the drain electrode 48, and outputs a voltage _{V OU T.} In FIG. 5, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

Next, with reference to FIG.
The operation of the S transistor will be described. First, pMO
A voltage substantially equal to the power supply voltage _VDD is applied to the drain electrode 47 of the S transistor 102. Gate voltage applied to the gate electrode 22 (input signal) V _P is high level V
_At the time of _PH , the pMOS transistor 102 is turned off. In this case, to optimize the sub-gate voltage V _FP, withstand voltage of the offset region 34 is depleted to the sub-gate voltage V _FPH that maximizes. This sub-gate voltage V _FPH
Is lower than the high level _{V PH} of the gate voltage _{V P.}
As a result, the peak of the lateral electric field is reduced to the drain region 43.
Near the boundary of the offset area 34 and the offset area 34
And the active region 32 is formed in the vicinity of the boundary, thereby improving the breakdown voltage. In this case, substantially equal to voltage _{V OUT} and the ground voltage _{V SS} is output to the output terminal 63 connected to the source electrode 48 of the pMOS transistor 102. Next, the gate voltage applied to the gate electrode 22 (the pulse signal) _{V P} is low level from the high level _{V PH} V
When the transition to _PL, sub-gate voltage _{V FP} also be synchronized with the gate voltage _{V P} by transitioning from a high level _{V FPH} the low level _{V FPL.} At this time, the sub-gate voltage V
The _FPL lower than the gate voltage V _PL, and applies a voltage such as p-type conductive layer is formed in the offset region 34 immediately below the sub-gate electrode 24. As a result, holes are generated in the offset region 34 and the resistance of the offset region 34 decreases, so that a higher on-current can be obtained. When the pMOS transistor 102 is on, the nMOS transistor 101 is off, so that the output terminal 63 connected to the source electrode 48 of the pMOS transistor 102 outputs a voltage _VOUT substantially equal to the power supply voltage _VDD .
The pulse signal to the gate electrode 22 may be a signal obtained by level-converting the gate signal to the sub-gate electrode 24 by a level shift circuit.

Thus, according to this embodiment, p
When the MOS transistor 102 is off, controlling the width of the depletion layer formed in the offset region 34 alleviates the electric field concentration and improves the breakdown voltage. Also, p
When the MOS transistor 102 is on, holes are induced in the offset region 34 immediately below the sub-gate electrode 24 as the sub-gate voltage decreases, and the offset region 3
4, the switching effect is improved and the same effect as that of the first embodiment can be obtained.

FIG. 7 shows a sub-gate type complementary metal oxide semiconductor (CMOS) according to a third embodiment of the present invention.
tor) sectional view showing the configuration of the inverter, and FIG.
FIG. 9 is a circuit diagram of the OS inverter, and FIG. 9 is a timing chart showing the operation of the CMOS inverter. First, a structure of a CMOS inverter using a sub-gate transistor will be described with reference to FIG. The CMOS inverter according to this embodiment is obtained by connecting the nMOS transistor 101 according to the first embodiment and the pMOS transistor 102 according to the second embodiment in series with the common drain electrodes 46 and 48. is there. That is, in this embodiment, the drain electrode 46 of the nMOS transistor 101 and the drain electrode 48 of the pMOS transistor 102 are constituted by a common drain electrode 49. In FIG. 7, the same reference numerals are given to the respective portions corresponding to the components in FIGS. 1 and 4, and the description thereof will be omitted.

In this embodiment, in particular,
The source region of the nMOS transistor 101 is a first source region, the active region is a first active region, the offset region is a first offset region, the drain region is a first drain region, and the gate electrode is a first drain region. A gate electrode, a sub-gate electrode as a first sub-gate electrode, p
The source region of the MOS transistor is a second source region, the active region is a second active region, the offset region is a second offset region, the drain region is a second drain region, and the gate electrode is a second gate. An electrode and a sub-gate electrode as a second sub-gate electrode are distinguished from the first and second embodiments.

Next, with reference to FIG.
The circuit configuration of the S inverter will be described. This CMO
The S inverter is an nMOS inverter (first embodiment) or a pMOS inverter (second embodiment) described above.
The difference from the above is that the load resistor 70 is eliminated because the transistors function as load resistors. The output terminal 63 is connected to the common drain electrode 49 to output the voltage _VOUT . pMOS transistor 1
The source electrode 47 is connected to a power supply line via a power supply connection terminal 62. On the other hand, the source electrode 45 of the nMOS transistor 101 is connected to a ground line via a ground connection terminal 61.

Next, the operation of the CMOS inverter will be described with reference to FIG. nMOS transistor 10
On the contrary, when the nMOS transistor 101 is in the off state, the pMOS transistor 102 is in the on state.
Is turned on, the pMOS transistor 102 is turned off.

First, the operation of the nMOS transistor 101 will be described. When the gate voltage (input signal) V _N applied to the gate electrode 21 is at the low level V _NL , nMO
S transistor 101 is turned off. In this case, to optimize the sub-gate voltage V _FN, sub-gate voltage withstand voltage becomes maximum in the offset region 33 is depleted V _{FN L}
To This sub-gate voltage V _FNL is equal to the gate voltage V _N
Higher than the low level. Thus, by controlling the width of the depletion layer formed in the offset region 33, the electric field concentration is reduced and the breakdown voltage is improved. Note that nM
When the OS transistor 101 is off, the pMOS transistor 102 is on, so that the drain electrode 46 and the drain electrode 4 of the nMOS transistor 101
A voltage V _OUT substantially equal to the power supply voltage V _DD is output from an output terminal 63 connected to the power supply voltage V _DD .

Next, pulsed gate voltage _{V N} from the low level _{V NL} of when to transition to a high level _{V NH} is sub-gate voltage _{V FN} is also the gate voltage _{V N} synchronized with allowed by the high level _{V FNH} from the low level _{V FNL} Transition to. At this time, the sub-gate voltage V _FNH is set higher than the gate voltage V _NH , and a voltage is applied such that an n-type conductive layer is formed in the offset region 33 immediately below the sub-gate electrode 23. Thereby, electrons are generated in the offset region 33 and the resistance of the offset region 33 is reduced, so that a higher on-current can be obtained. When the nMOS transistor 101 is on, the PMOS transistor 102 is off. Therefore, the ground voltage V is applied to the output terminal 63 connected to the drain electrode 46 of the nMOS transistor 101.
_A voltage V _OUT substantially equal to _SS is output. The pulse signal to the gate electrode 21 may be a signal obtained by level-converting the gate signal to the sub-gate electrode 23 by a level shift circuit.

Next, the operation of the pMOS transistor will be described.
Will be explained. Gate voltage applied to gate electrode 22
(Input signal) V_PIs high level V_PHAt the time of pMOS
The transistor 102 is turned off. In this case,
Port voltage V_FPAnd deplete the offset region 34
Sub-gate voltage V at which the breakdown voltage is maximized_FPHNasu
You. This sub-gate voltage V_FPHIs the gate voltage V_PNo ha
Level I_PHLower than As a result, the offset
By controlling the width of the depletion layer formed in the
As a result, the electric field concentration is reduced, and the breakdown voltage is improved. pMOS transistor
When the transistor 102 is off, the nMOS transistor
Since the star 101 is in the ON state, the pMOS transistor
The output terminal 63 connected to the source electrode 48 of the
Is the ground voltage V _SSV approximately equal to_OUTIs output
You. The drain electrode of the pMOS transistor 102
47 has a power supply voltage V_DDIs applied.

[0043] Next, the sub-gate voltage _{V FP} also be synchronized with the gate voltage _{V P} when the gate voltage applied to the gate electrode 22 (the pulse signal) _{V P} changes from a high level _{V PH} to the low level _{V PL} High A transition is _made from the level V _FPH to the low level V _FPL . At this time, the sub-gate voltage V _FPL lower than the gate voltage V _FPL, and p-type conductive layer for applying a voltage as formed in the offset region 34 immediately below the sub-gate electrode 24. This allows
Holes are generated in the offset region 34 and the offset region 34
, A higher on-current can be obtained. p
When the MOS transistor 102 is on, the nMOS
Since the transistor 101 is off, a voltage V _OUT substantially equal to the power supply voltage V _DD is output to the output terminal 63 connected to the source electrode 48 of the pMOS transistor 102. The pulse signal to the gate electrode 22 may be a signal obtained by level-converting the gate signal to the sub-gate electrode 24 by a level shift circuit.

As described above, according to the third embodiment, when the nMOS transistor or the pMOS transistor is off, the electric field concentration is reduced by controlling the width of the depletion layer formed in the offset region. As a result, the breakdown voltage is improved. Also, an nMOS transistor or pMO
When the S transistor is in the ON state, carriers are induced in the offset region immediately below the sub-gate electrode by the sub-gate voltage, so that the resistance of the offset region decreases and the switching characteristics are improved, which is substantially the same as the first and second embodiments. The effect can be obtained.

Fourth Embodiment FIG. 10 shows a CMOS according to a fourth embodiment of the present invention.
5 is a timing chart illustrating an operation of the inverter. In the third embodiment, the pulse signal synchronized with the pulse signal to the gate electrode is input to the sub-gate electrodes of both the nMOS transistor 101 and the pMOS transistor 102.
When the characteristics are significantly different from those of the MOS transistor 102, the driving method of this embodiment as shown in FIG. 10 can be applied. In this case, the sub-gate potential _{V FP} applied to the sub-gate electrode 24 of the pMOS transistor 102 and a constant fixed potential. And nMO
Only the sub-gate electrode 23 of the S transistor 101, _{V FNH} when _{V F NL,} the high level when the pulse signal is the low level to the pulse signal _V N, the gate in synchronization with the _{V P} electrode 21 to the gate electrode of each transistor Input pulse. Thus, in the OFF state of the nMOS transistor 101, the sub-gate voltage V _FNL applied to the sub-gate electrode 23, it is possible to control the width of the depletion layer formed in the offset region 33, the breakdown voltage is improved. When the nMOS transistor 101 is on, nM
As the sub-gate voltage of the OS transistor 101 increases to _VDD , electrons are induced in the offset region 33 immediately below the sub-gate electrode 23, whereby the resistance decreases and the switching characteristics improve. In the off state of the pMOS transistor 102, the electric field concentration is reduced by controlling the width of the depletion layer formed in the offset region 34 by the constant sub-gate voltage V _FPH applied to the sub-gate electrode 24, and the breakdown voltage is improved. I do. In addition, when the pMOS transistor 102 is in the on state, the constant sub-gate voltage V _FPH
As a result, the offset region 34 immediately below the sub-gate electrode 24
Then, holes are induced to reduce the resistance, and the switching characteristics are improved. In this case, the pMOS transistor 10
Since the input signal to 2 is fixed, the offset region is depleted in the off state, carriers are not necessarily induced in the on state, and the breakdown voltage may decrease. Therefore, the withstand voltage of the pMOS transistor 102 becomes nMOS
This is suitable for application when the withstand voltage of the transistor 101 is significantly higher than that of the transistor 101.

Fifth Embodiment FIG. 11 shows a CMOS according to a fifth embodiment of the present invention.
5 is a timing chart illustrating an operation of the inverter. This embodiment is significantly different from the above-described fourth embodiment in that the sub-gate voltage V _FN applied to the sub-gate electrode 23 of the nMOS transistor 101 is set to a constant fixed potential V _FNL and the gate electrode of each transistor is changed. pulse signal _V N, the low level to the sub-gate electrode 24 of the pMOS transistor 102 in synchronization with the _{V P} is V to
_The point is that a pulse signal whose _{FPL is at} a high level of V _FPH is input. As shown in FIG. 11, even with this configuration, the nMOS transistor 101 or the pMOS
When the transistor 102 is off, the width of the depletion layer formed in the offset region is controlled by the sub-gate voltage, so that the breakdown voltage is improved. Further, when the nMOS transistor 101 or the pMOS transistor 102 is in the ON state, carriers are induced in the offset region immediately below the sub-gate electrode due to the sub-gate voltage, and the resistance of the offset region decreases, thereby improving the switching characteristics.
It is possible to obtain substantially the same effect as that of the embodiment. In addition,
In this case, since the input signal to the nMOS transistor 101 is fixed, the offset region is depleted in the off state, carriers are not necessarily induced in the on state, and the breakdown voltage may decrease. Therefore, the withstand voltage of the nMOS transistor 101 is
It is suitable to be applied when the pressure resistance is considerably higher than the withstand voltage.

Next, a sixth embodiment of the present invention will be described.
FIG. 12 shows a CMOS according to a sixth embodiment of the present invention.
FIG. 13 is a timing chart showing the operation of the CMOS inverter. The element structure is the same as the structure of the CMOS transistor shown in FIG. 7 except for the connection between the gate electrode and the sub-gate electrode. As shown in FIG.
1 and the pMOS transistor 102 to form a CMOS inverter, which is the same as the third embodiment, except that the sub-gate electrodes 23 and 24 and the gate electrodes 21 and
In contrast to the third embodiment in which mutually independent pulse signals are input to the transistor 22, in this embodiment, the pulse signal input to the gate electrode 21 of one transistor 101 is applied to the sub-gate electrode of the other transistor 102. The third point is that a pulse signal input to the gate electrode 22 of the other transistor 102 is used as a pulse signal input to the sub-gate electrode 23 of the one transistor 101. This is different from the embodiment. The sixth embodiment is particularly suitable when the amplitude of a pulse signal input to the gate electrodes 21 and 22 is large.

In this specific configuration, the drain region (first drain region) 42 of the nMOS transistor 101 and the drain region (second drain region) 44 of the pMOS transistor 102 are connected, and the nMOS transistor 101 and the pMOS transistor The transistor 102 is cascaded. Then, the gate electrode (first gate electrode) 21 of the nMOS transistor 101 and the sub-gate electrode (second sub-gate electrode) 2 of the pMOS transistor 102
4 and the gate electrode (second gate electrode) 22 of the pMOS transistor 102 and the sub-gate electrode (first sub-gate electrode) of the nMOS transistor 101
23 is connected. Other configurations include the source electrode 4 of the pMOS transistor 102.
7 is connected to a power supply line via a power supply connection terminal 62, and the source electrode 45 of the nMOS transistor 101 is
It is connected to a ground line via a ground connection terminal 61.

Next, referring to FIG.
The operation of the OS inverter will be described. nMOS tiger
Pulse signal input to the gate electrode 21 of the transistor 101
Issue V_{IN N}Low level of V_SSAnd the high level is V
_NHAnd The gate of the pMOS transistor 102
Pulse signal V input to the_INPThe low level of
V _PLAnd the high level is V_DDAnd Where nM
Input to the gate electrode 21 of the OS transistor 101
Pulse signal is low level V_SSAnd the pMOS transistor
Pulse input to the gate electrode 22 of the transistor 102
Signal is low level V_PL, The nMOS transistor
The transistor 101 is off, the pMOS transistor 102
Is turned on. At this time, the pMOS transistor 1
02 has a potential of V_SSBecomes nM
The potential of the sub-gate electrode 23 of the OS transistor is V_PL
become.

[0050] In this case, to optimize the sub-gate voltage V _PL, withstand voltage of the offset region 33 is depleted to the voltage becomes maximum. This voltage is higher than the low level _{V SS} of the gate voltage _{V INN.} As a result, the peak of the lateral electric field is divided near the boundary between the drain region 42 and the offset region 33 and near the boundary between the offset region 33 and the active region 31, and the withstand voltage is improved. Since sub-gate voltage becomes equal to V _SS in the pMOS transistor 102, holes are induced decreases the resistance of the offset region 33 in the sub-gate electrode 24 under the offset region 33, the on-current is increased.

On the other hand, the pulse signal to the gate electrode 21 of the nMOS transistor 101 is at the high level V _NH ,
When the pulse signal to the gate electrode 22 of the pMOS transistor 102 is at the high level _VDD , the nMOS transistor 101 is turned on and the PMOS transistor 102 is turned off. At this time, the subgate potential of the pMOS transistor is V _NH , and the subgate potential of the nMOS transistor is V _DD .

In this case, the sub-gate voltage V _NH is optimized, and the offset region 34 is depleted to a voltage at which the breakdown voltage is maximized. This voltage becomes lower than the high level V _DD of the gate voltage V _INP . As a result, the width of the depletion layer formed in the offset region 33 is increased, and the maximum electric field is reduced, so that the breakdown voltage is improved. nMOS transistor 1
In 01, since the sub-gate voltage becomes equal to _VDD , electrons are induced in the offset region 33 immediately below the sub-gate electrode 23, so that the resistance of the offset region 33 decreases and the on-current increases.

Therefore, even with this configuration, substantially the same effects as described in the first and second embodiments can be obtained. Further, the mutual transistors 101 and 102
The gate electrodes 21 and 22 and the sub-gate electrodes 23 and 24 are interconnected by utilizing the magnitude relationship of the voltages applied to the gate electrodes 21 and 22 and the sub-gate electrodes 23 and 24, respectively, so that a level shift circuit is not used. Since it may be possible, the element structure can be simplified.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to the embodiments, and there are design changes and the like within a range not departing from the gist of the present invention. Is also included in the present invention. For example, in the above embodiment, the input signals are separately supplied to the gate electrode and the sub-gate electrode. However, the gate electrode and the sub-gate electrode are connected by a level shift circuit, and any one of the gate electrode and the sub-gate electrode is used. An input signal may be supplied to one of the electrodes. In this case, a voltage lower than the applied voltage is applied to the other electrodes by the level shift circuit. In addition, although a voltage between the gate voltage and the drain voltage is applied to the sub-gate electrode, the offset region is depleted when the transistor is off,
Any voltage may be used as long as carriers are induced in the offset region in the on state.

[0055]

As described above, according to the structure of the present invention, there is provided a sub-gate insulated gate field-effect transistor having a sub-gate electrode for controlling the state of an offset region provided between an active region and a drain region. In the driving method, based on a basic configuration in which a pulse-shaped input signal independent of an input signal applied to the gate electrode and synchronized with the input signal is applied to the sub-gate electrode, an offset is set in accordance with an off state or an on state of the transistor. By depleting or inverting the region to induce carriers, high withstand voltage and high-speed response can be realized.

In a sub-gate insulated gate field-effect transistor in which an n-type insulated gate field-effect transistor and a p-type insulated gate field-effect transistor are cascaded with a common drain, and a method of driving the same, By connecting the gate electrode and the sub-gate electrode with each other, only applying a pulse-like input signal synchronized with the gate electrode and the sub-gate electrode of one transistor allows the offset region to be adjusted according to the off state or the on state of both transistors. Carriers are induced by depletion or inversion, and high breakdown voltage and high-speed response can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of an nMOS transistor according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of an nMOS inverter using the same nMOS transistor.

FIG. 3 is a timing chart showing an operation of the nMOS inverter.

FIG. 4 is a sectional view showing a configuration of a pMOS transistor according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram of a pMOS inverter using the same pMOS transistor.

FIG. 6 is a timing chart showing the operation of the pMOS inverter.

FIG. 7 is a sectional view showing a configuration of a sub-gate type CMOS inverter according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of the CMOS inverter.

FIG. 9 is a timing chart showing the operation of the CMOS inverter.

FIG. 10 shows a CMOS according to a fourth embodiment of the present invention;
5 is a timing chart illustrating an operation of the inverter.

FIG. 11 shows a CMOS according to a fifth embodiment of the present invention;
5 is a timing chart illustrating an operation of the inverter.

FIG. 12 shows a CMOS according to a sixth embodiment of the present invention;
It is a circuit diagram of an inverter.

FIG. 13 is a timing chart showing the operation of the CMOS inverter.

FIG. 14 is a cross-sectional view showing a structure of a conventional nMOS transistor.

FIG. 15 is a circuit diagram of an nMOS inverter using the same nMOS transistor.

FIG. 16 is a timing chart showing the operation of the nMOS inverter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Insulating substrate 12 Semiconductor layer (1st semiconductor layer) 13 Semiconductor layer (2nd semiconductor layer) 21 Gate electrode (1st gate electrode) 22 Gate electrode (2nd gate electrode) 23 Subgate electrode (1st layer) Sub-gate electrode) 24 sub-gate electrode (second sub-gate electrode) 31 active region (first active region) 32 active region (second active region) 33 offset region (first offset region) 34 offset region (second) Offset region) 51 first interlayer insulating film 52 second interlayer insulating film 101 nMOS transistor 102 pMOS transistor V _DD power supply voltage (high level) V _SS ground voltage V _OUT output V _N , _VP gate voltage V _FN , V _FP sub-gate voltage

Claims (16)

[Claims] 1. A semiconductor layer provided with a source region, an active region, an offset region, and a drain region along a current flow path, and a gate electrode formed on a gate insulating film on the active region. And a sub-gate electrode formed so as to cover at least an end of the gate electrode and a part of the offset region adjacent to the end of the gate electrode with the sub-gate insulating film interposed from the gate electrode to the offset region. A method for driving a field effect transistor having a pulsed input signal applied to the gate electrode, independent of the input signal to the gate electrode, and synchronized with the input signal to the gate electrode. A driving method of the field effect transistor, wherein the input signal is applied to the sub-gate electrode. 2. The method according to claim 1, wherein the voltage level of the input signal applied to the sub-gate electrode is different from the voltage level of the input signal applied to the gate electrode. 3. A source signal and a drain region of the field effect transistor are of n conductivity type, and a low level of an input signal applied to the sub-gate electrode when the field effect transistor is in an off state is a pulse signal applied to the gate electrode. The high level of an input signal applied to the sub-gate electrode is higher than a low level of the input signal applied to the sub-gate electrode when the field-effect transistor is on, and the high level of an input signal applied to the gate electrode is higher than the low level of the input signal. A method for driving a field-effect transistor. 4. A low level of an input signal applied to the sub-gate electrode in an off state of the field effect transistor is a voltage at which the offset region is depleted,
4. The field effect transistor according to claim 3, wherein the high level of the input signal applied to the sub-gate electrode in the on state of the field effect transistor is a voltage at which an n-type conductive layer is formed at least in the offset region. Drive method. 5. A source signal and a drain region of the field effect transistor are of p conductivity type, and a high level of an input signal applied to the sub-gate electrode when the field effect transistor is off is a pulse signal applied to the gate electrode. 3. The device according to claim 2, wherein the input signal applied to the sub-gate electrode is lower than the low level of the input signal applied to the gate electrode when the field-effect transistor is on. A method for driving a field-effect transistor. 6. A high level of an input signal applied to the sub-gate electrode in an off state of the field-effect transistor is a voltage at which the offset region is depleted,
And a low level of an input signal applied to the sub-gate electrode when the field-effect transistor is on,
6. The method according to claim 5, wherein the voltage is a voltage at which a p-type conductive layer is formed in the offset region. 7. An n-type first source region, a first active region, a first offset region, and an n-type first source region along a current flow path.
A first semiconductor layer provided with a first drain region of a type, a first gate electrode formed on a first gate insulating film on the first active region, A first offset region extending from a gate electrode to the first offset region and at least an end of the first gate electrode and an end of the first gate electrode with a first sub-gate insulating film interposed therebetween; An n-type field-effect transistor having a first sub-gate electrode formed so as to cover a partial region of a second source region; a second p-type source region along a current flow path; a second active region; A second semiconductor layer provided with an offset region and a p-type second drain region, and a second semiconductor layer formed on a second gate insulating film on the second active region.
And at least an end of the second gate electrode and an end of the second gate electrode from the second gate electrode to the second offset region and across a second sub-gate insulating film. A p-type field-effect transistor having a second sub-gate electrode formed to cover a part of the second offset region adjacent to the n-type field-effect transistor and the p-type field-effect transistor Are connected in cascade by connecting the first drain region and the second drain region, the first gate electrode is connected to the second sub-gate electrode, and the second gate electrode A field effect transistor, wherein the field effect transistor is connected to the first sub-gate electrode. 8. The method for driving a field-effect transistor according to claim 7, wherein a pulse-like input signal is applied to the first gate electrode or the second sub-gate electrode, and the first gate is applied. A pulse-shaped input signal independent of an input signal to an electrode or the second sub-gate electrode and synchronized with an input signal to the first gate electrode or the second sub-gate electrode; A method for driving a field effect transistor, wherein the method is applied to a first sub-gate electrode. 9. A voltage level of an input signal applied to the second gate electrode or the first sub-gate electrode is different from a voltage level of an input signal applied to the first gate electrode or the second sub-gate electrode. 9. The method for driving a field effect transistor according to claim 8, wherein: 10. A low level of an input signal applied to the second gate electrode or the first sub gate electrode is higher than a low level of a pulse signal applied to the first gate electrode or the second sub gate electrode. And a high level of an input signal applied to the second gate electrode or the first sub-gate electrode is higher than a high level of an input signal applied to the first gate electrode or the second sub-gate electrode. The method for driving a field effect transistor according to claim 9, wherein 11. A low level of an input signal applied to the first gate electrode or the second sub-gate electrode is such that a p-type conductive layer is formed in the second offset region, and the n-type field effect transistor is provided. Is the voltage that turns off,
The low level of the input signal applied to the second gate electrode or the first sub-gate electrode is a voltage at which the first offset region is depleted and the p-type field-effect transistor is turned on. The high level of the input signal applied to the gate electrode or the second sub-gate electrode causes the second offset region to be depleted and the n
A high level of an input signal applied to the second gate electrode or the first sub-gate electrode, the n-type conductive layer being formed in the first offset region; 2. A voltage for turning off the p-type field effect transistor.
0. The method for driving a field-effect transistor according to item 0. 12. An n-type first source region, a first active region, a first offset region, and an n-type first source region along a current flow path.
a first semiconductor layer provided with an n-type first drain region; a first gate electrode formed on a first gate insulating film on the first active region; From the gate electrode to the first offset region and at least an end of the first gate electrode and the first offset adjacent to an end of the first gate electrode with a first sub-gate insulating film interposed therebetween. An n-type field effect transistor having a first sub-gate electrode formed so as to cover a part of the region, a p-type second source region along a current flow path, a second active region, A second semiconductor layer provided with a second offset region and a p-type second drain region, and a second semiconductor layer formed on a second gate insulating film on the second active region.
And at least an end of the second gate electrode and an end of the second gate electrode from the second gate electrode to the second offset region and across a second sub-gate insulating film. A p-type field effect transistor having a second sub-gate electrode formed so as to cover a part of the second offset region adjacent to the first drain region and the second drain region And driving the cascade-connected field-effect transistors, wherein the first gate electrode, the first sub-gate electrode, the second gate electrode, and the second sub-gate electrode are mutually independent and synchronized. A method for driving a field effect transistor, comprising applying a pulsed input signal. 13. A voltage level of an input signal applied to said first sub-gate electrode is different from a voltage level of an input signal applied to said first gate electrode, and said input signal applied to said second sub-gate electrode has a different voltage level. Voltage level and the second
13. The method of driving a field effect transistor according to claim 12, wherein the voltage levels of the input signals to the gate electrodes are different. 14. The p-type field-effect transistor is on when the n-type field-effect transistor is off, and the p-type field-effect transistor is off when the n-type field-effect transistor is on. 14. The method of driving a field effect transistor according to claim 13, wherein: 15. A low level of an input signal applied to the first sub-gate electrode is higher than a low level of a pulse signal applied to the first gate electrode in an off state of the n-type field effect transistor, and The high level of the input signal applied to the first sub-gate electrode is higher than the high level of the input signal applied to the first gate electrode when the field effect transistor is on, and the high level of the input signal applied to the first gate electrode is off when the p-type field effect transistor is off. The high level of the input signal applied to the second sub-gate electrode is lower than the high level of the input signal applied to the second gate electrode, and the high level of the input signal is applied to the second sub-gate electrode when the p-type field effect transistor is on. The low level of the input signal to be applied is lower than the low level of the input signal applied to the second gate electrode. 13. The method according to claim 13, wherein:
5. The method for driving a field-effect transistor according to 4. 16. The n-type field-effect transistor according to claim 1, wherein a low level of an input signal applied to said first sub-gate electrode when said n-type field-effect transistor is off is a voltage at which said first offset region is depleted. The high level of the input signal applied to the first sub-gate electrode when the transistor is on is a voltage at which an n-type conductive layer is formed at least in the first offset region, and the p-type field effect transistor is off. The high level of the input signal applied to the second sub-gate electrode is a voltage at which the second offset region is depleted, and
16. The low level of an input signal applied to the second sub-gate electrode in the ON state of the field effect transistor is a voltage at which a p-type conductive layer is formed in the second offset region. A driving method of the field-effect transistor according to the above.