JPH0580831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a method of arranging signal lines or power supply lines that enables a high S/N ratio.

[Background of the invention]

As LSIs become more highly integrated and larger in the future,
Design that takes into account high speed and high S/N ratio is becoming increasingly important. However, with the increase in integration and scale,
As the wiring pitch of signal lines and power supply lines has become smaller, and three-dimensional wiring has become more common, coupling noise due to parasitic coupling capacitance between wirings has become a problem in conventional layout methods.

FIGS. 1 and 2 show the concept of a conventional method of arranging signal lines and power supply lines. In FIG. 1, 1 to 6 are signal lines or power supply lines formed in the same manufacturing process. Further, in FIG. 2, 7 is a signal line or a power supply line formed in a manufacturing process different from 1 to 5. As shown in Figs. 1 and 2, when 1 to 7 are placed in the same direction over a fairly long period, conventionally 6 or 7 is placed parallel to 1 to 5, so 1 to 5 generates a small signal. If this is a signal line that requires special attention to the S/N ratio, the coupling capacitance 8 to 11 with 6 or 7 will induce large coupling noise only on 2 and 3, which will cause a big problem in terms of S/N. I was getting used to it. Conversely, if 6 and 7 are signal lines that handle small signals, they will similarly receive large coupling noise from 2 and 3 due to the coupling capacitances 8 to 11.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to improve the arrangement method and provide a method for arranging signal lines and feeder lines with low noise and high S/N in order to solve the problems of the conventional arrangement method.

[Summary of the invention]

To achieve the above object, the present invention reduces the coupling capacitance between the wiring that becomes a noise source and the wiring that handles minute voltage by arranging the former (or the latter) so that it intersects the latter (or the former). By doing so, the problem of the prior art can be solved.

[Embodiments of the invention]

The present invention will be explained in detail below with reference to Examples.

FIG. 3 shows an embodiment of the present invention corresponding to FIG. 1. As shown in the figure, by arranging the wiring 6 in a stepwise manner and crossing the wirings 1 to 5, the coupling capacitance with a specific wiring among the wirings 1 to 5 does not increase, and the wirings 1 to The coupling capacitance between the individual wirings 5 and 6 can be reduced. That is, a large coupling noise is not induced between a specific wiring among wirings 1 to 5 and wiring 6, and the coupling noise between each wiring of wirings 1 to 5 and wiring 6 can be reduced.
Note that in FIG. 3, wirings 1 to 5 are formed of a conductive film 14, and wiring 6 is formed of a conductive film 13 formed in a manufacturing process different from that of 14 and 14. The combinations of the conductive films 13 and 14 include, for example, poly-Si or metals such as W and Mo, or silicides of these metals and Al in the first layer, a diffusion layer and Al in the first layer, and Al in the first layer. A second layer of Al can be considered, and either of the conductive films 13 and 14 may be the upper conductive film. Further, in the figure, 12 is a through hole that connects the conductive films 13 and 14.

FIG. 4 shows another embodiment of the present invention,
This corresponds to the conventional example shown in FIG. In this embodiment, the wiring 7 is formed in a manufacturing process different from that of the wirings 1 to 5. Similarly to the wiring 6 in FIG. , the coupling capacitance between each of the wirings 1 to 5 and the wiring 7 can be reduced. The combination of the conductive films 14 and 15 may be the same as the combination of the conductive films 13 and 14 described above, and either of the conductive films 14 and 15 may be the upper layer.

FIG. 5 shows another embodiment of the present invention. In FIG. 4, the wiring 7 is arranged in a stepwise manner, whereas the wiring 7 is
This is a case in which they are arranged so as to intersect linearly at a certain angle with respect to 5. According to this embodiment, the coupling capacitance between the wiring 7 and each wiring can be reduced as in FIG. 4. Note that when the number of crossing points between the wiring 7 and 1 to 5 is made equal in FIGS. 4 and 5, the length of the wiring 7 in FIG. 5 is shorter, but the coupling capacitance between the wiring 7 and each individual wiring is is large, so both can be used depending on the design.

FIG. 6 shows another embodiment of the invention. In the figure, wires 40 and 41 are not adjacent and are arranged vertically.
In particular, the case where it is desired to equalize the noise induced from the wiring 7 is shown. In this case, wiring 4
The wiring 7 may be arranged so that 0, 41 and 7 intersect in the same way, and in the figure, as an example, the wiring 7 is arranged in a zigzag pattern. According to this embodiment, the wiring 7
The coupling capacitance between the wire 7 and the wires 1, 2, 3, 5, 40, and 41 can be reduced, and the coupling capacitance between the wire 7 and the wires 40, 41 can be made equal.

In addition, in Fig. 3, Fig. 4, Fig. 5, and Fig. 6,
For convenience of explanation, an example is shown in which a plurality of wirings 1 to 5 and one wiring (6 or 7) are used.
The former is at least 2 or more, the latter at least 1
It suffices if there are more than one wire. Further, the wirings on both sides do not need to be equally spaced and have the same shape, but may be at arbitrary intervals and may have any shape. In any case, by arranging some or all of the plurality of latter wirings to intersect with at least one of the former wirings, depending on the design, the former and the latter The coupling capacitance between individual wirings can be reduced. An example is shown in FIG.

In FIG. 7, three wires 71, 72, and 73 are arranged in the same direction as wires 1 to 5. In this embodiment, the wiring 72 can be placed in a position where the coupling capacitance with the wirings 1 to 5 does not pose a problem in terms of design.
As before, it is arranged parallel to the wirings 1 to 5. On the other hand, the wiring 71 must be placed close to the wirings 1 to 3, and the wiring 73 must be placed close to the wirings 4 and 5, and it is necessary to reduce the coupling capacitance between the individual wirings in terms of design. Therefore, by making the wirings 71 and 73 intersect with the wirings 1 to 5 as shown in the figure, it is possible to reduce the coupling capacitance.

In addition, in FIGS. 3 to 7, when there are a plurality of wires shown by solid lines and dotted lines, each wire group may include wires formed in the same manufacturing process. For example, although an example in which the wiring groups are formed is described, in the present invention, the former and latter wiring groups are not limited to being formed in the same manufacturing process, but each wiring group includes wiring formed in solid lines in different manufacturing processes. may be included. For example, there is a case where the wiring group shown is formed of first layer Al, a part of the wiring group shown by dotted lines is formed of second layer Al, and the rest is formed of third layer Al.

Furthermore, in FIGS. 4 to 7, even if the wiring width is so wide that the wiring indicated by the dotted line overlaps one or more of the wiring indicated by the solid line,
As mentioned above, by arranging the wires in a stepwise manner or in a straight line at a certain angle with the wires shown by the solid lines, and by crossing a larger number of wires, it is possible to reduce the coupling capacitance with the individual wires shown by the solid lines. can.

Although the concept of the present invention has been illustrated above using several simple examples, the present invention will be explained below using more specific examples.

FIG. 8 shows an embodiment in which the present invention is applied to a decoder section of a semiconductor memory device. In the semiconductor memory device, wiring for a plurality of address signals is arranged in the decoder section 23. The number of wires for address signals varies depending on the size of the memory capacity, the method of configuring the memory array, etc., but is at least two or more. Here, in order to simplify the drawing, a case is shown in which six address signal wirings 16 to 21 are arranged. When arranging, for example, one signal line 22 that handles small signals in the decoder section 23 in the same direction as the wirings 16 to 21 arranged in this way, by arranging the signal lines 22 in a stepwise manner as shown in FIG. , it is possible to reduce the noise received from each address signal without receiving large noise from a specific address signal. Furthermore, by arranging 22 so as to intersect with all address signal wiring as shown in FIG. 8, the magnitude of noise induced in 22 does not change depending on the input address pattern, and any Even when an address pattern is input, the noise received by 22 is equally small. In addition, in FIG. 8, 22 is arranged in a step-like manner, but as shown in FIG. 5, it may be arranged so as to linearly intersect with 16 to 21 at a certain angle. Furthermore, in static type memories and memories in which one of the row or column decoders is static (for example, as described in Japanese Patent Laid-Open No. 58-29195), a set of address signals that are always complementary to each other is used. Wiring may be placed in the decoder section 23, and by crossing the wiring 22 with this set of wiring, the wiring 22 will always receive complementary noise from this set of wiring, making it impossible to cancel out the noise. It becomes possible.

Now, a memory array of a semiconductor memory device is a typical example in which a plurality of wirings handling minute signals are arranged. Hereinafter, an embodiment in which the present invention is applied to a memory array will be described using a one-transistor MOS memory as an example.

Figure 9 shows the data pair Di,,131.131
In a memory array consisting of memory cells (referred to as a folded dataline arrangement or two-crossing cell) laid out in close proximity to each other, peripheral circuits 24 and 25 consisting of address buffer circuits and other control circuits are connected. This is an example in which a signal or a power supply line 26 related to communication is arranged using a conductive film formed in a manufacturing process different from that of the data line and word line 127. In the figure, 128 is a memory cell, 29 is an X decoder. The driver 30 is a sense amplifier that differentially amplifies the signals read out onto the data pair lines. As shown in the figure, by arranging the wiring 26 so as to cross the data line pair at a certain angle, even if the wiring 26 is placed within the memory array, coupling noise between the individual data lines and the wiring 26 can be reduced. can be made smaller, and large noises are no longer induced only in specific data pairs. Furthermore, even if a mask misalignment occurs that may occur because the data pair line 26 and the data pair line 26 are formed in different manufacturing processes, an unbalance will not occur in the coupling capacitance between the data pair line 26 and the data pair line Di. Note that data lines, word lines, and wiring 2
As the conductive film forming 6, for example,
As described in Semiconductor World December 1982 issue p.32 or Japanese Patent Application Laid-Open No. 1985-198592,
The word lines are made of poly-Si, metals such as Mo, W, or silicides of these metals, the main parts of the data lines are made of the first layer of Al, and the wiring 26 is made of the second layer.
It is conceivable to form it with a layer of Al. In addition, in the case of one intersection cell, which will be described later, for example, p.32 of the same magazine,
As described in p. 33 or Japanese Patent Application Laid-Open No. 198592, the word line is formed of the first layer of Al, the data line is formed of poly-Si or a diffusion layer, and the wiring 26 is formed of the second layer of Al. It is conceivable to form it with Al.
However, the gist of the present invention is to reduce the coupling capacitance by crossing the data line and the wiring 26, and the combinations of conductive films are limited to those described herein unless departing from the idea of the present invention. It's not a thing.

FIG. 10 shows another embodiment of the present invention, in which the wiring 26 shown in FIG. 9 is arranged in a stepped manner, and this arrangement reduces the coupling capacitance between the wiring 26 and each data line. In order to further reduce the coupling capacitance, it is possible to increase the number of data lines that the wiring 26 intersects. In addition, in this embodiment, the wiring 2
6, the pitch _L1 of the part parallel to the data line is made equal to the pitch _L2 of the data line, and the wiring 26 intersects at the point where the data line is equally divided (9 in FIG. 10). The unbalance of the coupling capacitance between 26 and the data pair line Di due to the mask shift is minimized.

11 and 12 show the data pair lines Di, ,
This is an embodiment in which the present invention is applied to a memory array in which cells 231 and 231 are spatially separated (referred to as an open dataline arrangement or one-cross cell). In Figure 11, wiring 2
By arranging 26 linearly at a certain angle with respect to the data line, the coupling capacitance between 26 and each data line is reduced by arranging 26 in a stepwise manner in Fig. 12. . Furthermore, in this embodiment, the data pair lines are arranged to extend on both sides with the sense amplifier 30 at the center, and the wiring lines 26 are arranged symmetrically with respect to the sense amplifier row, thereby reducing the capacitance of the data pair lines. It's out of balance.

In the above embodiments, the case where there is one wiring in the memory array is shown. FIGS. 13 and 14 respectively show embodiments for a two-cross point cell system and a one-cross point cell system in the case of two wires 261 and 262. Further, although an example in which the wiring is arranged in a stepwise manner is shown here, arrangement methods shown in FIGS. 9 and 11 are also conceivable.

Similarly, the present invention can be applied to n wires (the maximum value of n, 1, and n is limited by the minimum value of the manufacturable wire pitch).

Now, in the above embodiment, an example was shown in which the wiring related to the communication between the peripheral circuits 24 and 25 was arranged in the memory array, but the present invention can also be applied to the case where the output of the decoder is arranged in the memory array. An example of this is described in Japanese Patent Application Laid-open No. 57-198592.

FIG. 15 shows the concept when the present invention is applied to the above invention. In the above invention, 1
As shown in the data line of the book, 31 _o,1 , 31 _o,2 ,
31 _o,3 and 31 _o,4 , and a switch 35 controlled by an output control signal YC36 _o from a Y decoder driver 34 is installed in a part of each divided data line.
_o,1 , 35 _o,2 , 35 _o,3 , 35 _o,4 are provided as common input/output lines 33 ₁ , 33 ₂ that are common to other divided data lines (for example, 31 _o+1,1 ). ．． ₃₃₃ and ₃₃₄ , data is exchanged between the two. In order to eliminate the increase in the area of the memory array,
YC is formed in a manufacturing process different from that of the data line, similar to the wiring 26 in FIG. 9 or 11. In this embodiment, by arranging the YC in the memory array in a stepwise manner, for example, and crossing the data line, the coupling capacitance between the YC (for example, 36 _o ) and one data line (for example, 31 _o,1 ) is This makes it possible to reduce the coupling noise that YC induces on the data line. In Fig. 15, 32 is the lead/
In the write control circuit, WE is a write/read control signal, A is an address signal, _Dio is a data input, and _Dput is a data output.

FIG. 16 shows an embodiment of the present invention for a two-intersection cell, and shows a part of the divided data line group (hereinafter referred to as sub-array) of FIG. 15. In this example, by arranging YC in a stepwise manner,
The coupling capacitance between one selected YC (for example, _31o ) and one data line (for example, 131o _+1,n ) is reduced. In other words, as shown in Fig. 16, by crossing one YC with, for example, five different data lines, the coupling capacitance becomes C ₀ + C ₁ (C ₀ or C ₁ in some combinations), which is different from the conventional It can be reduced to about 1/3 compared to the arrangement method, and high S/N read/write can be performed above the memory. Further reduction in coupling capacitance can be achieved by increasing the number of different data lines that YC intersects. In addition, in this embodiment, as described in FIG. 10, the pitch of the portion of YC parallel to the data line is made equal to the pitch of the data line, and furthermore, YC is arranged so that it intersects at the point where the data line is divided into even numbers. This arrangement prevents the coupling capacitance between YC and the data pair line Di from becoming unbalanced due to mask displacement. That is, in FIG. 16, the data line 131 _o+1,n
Alternatively, the coupling capacitance between 131 _o+1,n and the line group of YC is 3×(C ₀ +C ₁ ), so even if mask shift occurs, C ₀
By simply changing the values of and C ₁ , the capacitances of both will become equal. Therefore, the capacitance of Di varies due to the mask shift. This is not a source of noise.

FIG. 17 is an embodiment of the present invention for one intersection cell, and shows a part of the subarray of FIG. 15, similar to FIG. 16. In this example, since it is a single intersection cell, it is arranged so that YC is symmetrical with respect to the sense amplifier row, and YC between data pairs is
This is to prevent an imbalance in the coupling capacitance between the two. Also in Figure 16, as mentioned in Figure 15, by increasing the number of different data lines that YC intersects, it is possible to further reduce the coupling capacitance between one selected YC and the data line. It is.

FIG. 18 shows another embodiment of the present invention for a two-intersection cell, and is an example in which a sense amplifier row is commonly arranged in two subarrays. They share a sense amplifier and are connected to one of the subarrays via a gate control 37 controlled by an X coder 29. In this embodiment, the YCs of one subarray are arranged in the same manner as in FIG. 16, and the YCs of the other subarray are arranged symmetrically with respect to the sense amplifier column. By arranging them in this manner, it is possible to make the electrical characteristics of both subarrays the same even if the YCs are arranged in a stepped manner.

In the above embodiment, YC was installed for each data line, but YC can be installed using the method described in Japanese Patent Laid-Open No. 57-125186 (for example, when two sets of I/O lines are installed). The present invention can be applied even when provided corresponding to an arbitrary number of pairs of data lines.

The present invention can also be applied to the case where the YC wiring pitch is widened and signal lines and power supply lines different from the YC are provided therein as described above. An example is shown in FIG.

Figure 19 shows that by providing two sets of I/O lines,
This is an example in which the wiring pitch of the YC is doubled, and signals and power supply lines related only to communication between the peripheral circuits 24 and 25 are arranged in the same layer as the YC.
This allows wiring to be run inside the memory array without increasing the area of the memory array or increasing noise, resulting in a high S/N.
The chip area can be reduced. Note that here we have described the case where wiring different from YC is placed in the same layer as YC, but for example, YC is placed in the second Al layer.
However, it is also conceivable that other wirings may be formed using a different manufacturing process, such as when forming the third layer of Al.

Although several embodiments of the present invention have been described above, the scope of application of the present invention is not limited to the embodiments described here, and it goes without saying that various changes can be made without departing from the spirit of the invention. For example, in a memory array using two intersection cells, in order to eliminate capacitance unbalance between data pairs,
It is also conceivable to combine the present invention with a configuration in which pairs of wires cross each other an odd number of times as shown in FIG. 23 of No. 198592. Also, from Figure 9 onwards, 1
I explained using transistor MOS memory as an example, but
So-called static memory (for example, JP-A-Sho
30 of No. 57-198592), ROM, or a microprocessor in which these memories are mounted on the same chip, the present invention makes it possible to reduce noise in the memory array. Further, the embodiments shown in FIGS. 3 to 7 are applicable not only to memories but also to general LSIs manufactured using so-called microfabrication technology, and the present invention can reduce coupling noise between wirings. Particularly in CMOS-LSI, it is necessary to reduce the noise of wiring within the chip in order to prevent the latch-up phenomenon, and the reduction of noise by the present invention is considered to be particularly important.

〔Effect of the invention〕

As described above, according to the present invention, coupling noise between interconnects can be reduced and an LSI with high S/N can be realized.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are diagrams for explaining the conventional example,
FIGS. 3 to 7 are diagrams showing one embodiment of the present invention, and FIGS. 8 to 19 are circuit configuration diagrams of main parts of a semiconductor memory device showing other embodiments of the present invention. 1-7, 16-22, 26, 40, 41, 7
1, 72, 73, 261, 262...Signal line or power supply line, 8-11...Coupling capacitance, 12...Through hole, 13-15...Conductive film, 23...Decoder, 24, 25, 32... ...peripheral circuit, 27,
127, 227...word line, 28, 128, 2
28...Memory cell, 29...X decoder, 30
...Sense amplifier, 31, 31, 131, 13
1,231,231...Data line, 33...I/
O line, 34...Y decoder, 35...switch,
36...control line, 37...gate control circuit.

Claims (1)

[Scope of Claims] 1. A first wiring group consisting of at least two wirings arranged at arbitrary intervals and in an arbitrary shape, and at an arbitrary interval and in an arbitrary shape in substantially the same direction as the first wiring group. a second wiring group consisting of at least one wiring arranged in a semiconductor device, wherein at least one wiring in the second wiring group is arranged in at least two wirings in the first wiring group; A semiconductor device characterized in that it is arranged so as to intersect with the wiring of a book. 2. The first wiring group is a data line group in a semiconductor memory device, and the second wiring group is a signal line or a power supply line arranged in the data line group. A semiconductor device according to scope 1. 3. The semiconductor device according to claim 1, wherein at least one wiring of the second wiring group is arranged in a stepped manner with respect to the first wiring group.