JPS6236303Y2 - - Google Patents

Description

[Detailed description of the invention] This invention improves the channel width of the horizontal channel through which wiring between gate cells passes in a master slice large-scale integrated circuit (hereinafter referred to as LSI).

A conventional device of this type is shown in FIG. In the figure, 1a and 1b are input/output cells arranged vertically and horizontally around the chip, 2 are gate cells arranged regularly inside the input/output cells 1a and 1b, and 3 are input/output cells 1 and gate cells 2. Horizontal channels 4a, 4b, 4 through which interconnections interconnecting between or between a plurality of gate cells 2 pass;
C is a vertical channel through which wiring interconnects the input/output cell 1 and gate cell 2 or between multiple gate cells 2, and 5 is a vertical channel provided at the center of the chip for supplying power to the input/output cell 1 and gate cell 2. This is the power ground.

Next, the design method of this LSI will be explained. In master slice LSIs, gate cells 2 and input/output cells 1 are fixed at predetermined positions, and by changing only the connections between these cells, many types of logic circuits are realized. This method
In LSI, the width and position of horizontal channel 3 and vertical channel 4 are fixed in advance, and wiring for connection between cells is placed on these channels 3 and 4.

Conventional master slice type LSIs are configured as described above, so the same gate cells are arranged regularly, the width of each horizontal channel is uniform everywhere, and the wiring for connection between cells is connected to a specific horizontal channel. The drawback was that the wiring was often concentrated in the center of the channel and could not be completed. Also, if the width of the horizontal channel is increased to allow complete wiring, the usage rate of the horizontal channel will be lower near the periphery of the chip.
The disadvantage was that the chip area became large.

Furthermore, there is a conventional device described in Japanese Patent Application Laid-open No. 119692/1983 in which the width of the wiring area, ie, the channel, is increased near the center of the LSI chip. However, in the device described in this publication, the arrangement of the same logic units (gate cells) is arbitrarily changed near the center of the chip.
In this case, since the arrangement of the gate cells is random, it is not possible to distinguish (divide) horizontal channels between two opposing cell rows, which would be possible using the normal channel wiring method within the wiring area, and therefore the channel wiring method cannot be applied. First, automatic wiring was complicated.

This idea was made in order to eliminate the drawbacks of the conventional ones as described above. By increasing the width of each horizontal channel near the center of the LSI chip, wiring between cells can be automatically performed using the normal channel wiring method. The purpose is to provide a master slice type LSI that can be completely wired and has a small chip area.

An embodiment of this invention will be described below with reference to the drawings. In FIG. 2, 21a and 21b are input/output cells arranged vertically and horizontally around the chip, and 22a and 22b are input/output cells 21a and 21b.
The gate cells are regularly arranged inside the chip, and gate cells 22a with short vertical length are arranged near the center of the chip, and gate cells 22a with long vertical length are arranged near the periphery of the chip.
2b is placed. 23 is a horizontal channel through which wiring connecting the input/output cell 21 and the gate cells 22 or between the gate cells 22 passes; 24a, 24;
b, 24c are vertical channels through which wiring connects between the input/output cells 21 and gate cells 22 or between gate cells 22; 25 is a power supply provided in the center of the chip for supplying power to the input/output cells 21 and gate cells 22; It's grand.

The arrangement of the input/output cells 21a and 21b, the gate cell 22b, and the power supply ground 25 in this embodiment is exactly the same as in FIG. 1, so automatic wiring using the normal channel wiring method is possible in this embodiment as well. .

Next, the design method of this LSI will be explained. In the master slice LSI, gate cells 22 and input/output cells 21 are fixed at predetermined positions, and by changing only the connections between these cells, many types of logic circuits are realized. Although the width and position of the horizontal channel 23 and the vertical channel 24 are fixed, especially in the master slice type LSI of the present invention, the vertical length of the gate cell 22a near the center of the chip is made shorter than the gate cell 22b near the periphery. Therefore, the width of each lateral channel 23 becomes wider near the center of the chip. Then, wiring is placed on these channels by automatic wiring using a normal channel wiring method for connection between cells.

In the above embodiment, there are two gate cells 22, one with a short vertical length 22a and one with a long vertical length 22b.
Types are used. However, as long as each horizontal channel is widened near the center of the chip, three or more types of gate cells may be used, and the same effect as in the above embodiment can be achieved.

As described above, according to this invention, the gate cells are arranged so that the width of each horizontal channel increases near the center of the LSI chip, so wiring between cells can be completely performed automatically by the normal channel wiring method. Master slicing method that can increase the usage rate of each horizontal channel and has a small chip area.
This has the effect of providing LSI.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the chip structure of a conventional master slice LSI, and FIG. 2 is a plan view showing the chip structure of a master slice LSI according to an embodiment of the invention. 21a, 21b...input/output cell, 22a, 22
b... Gate cell, 23... Horizontal channel for wiring,
24a, 24b, 24c...Vertical channel for wiring,
25...Power ground.

Claims (1)

[Scope of utility model registration request] Input/output cells arranged around the chip, gate cells arranged regularly inside the input/output cells, horizontal channels for wiring between the input/output cells and the gate cells or between the gate cells, and the input/output cells and the gate cells. In a master slice type large-scale integrated circuit, the circuit is provided with a vertical channel for wiring between the gate cells or between the gate cells, and the input/output cells and the gate cells are arranged in such a manner that automatic wiring can be performed using a normal channel wiring method, A master slice type large-scale integrated circuit characterized in that the channel width of the wiring horizontal channel near the center of the chip is widened by shortening the vertical length of the gate cell near the center.