JPH02201958A - Gate array type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the efficiency of wiring in a circuit layout and shorten a design interval by making greater the number of wiring channels in a wiring channel region at a chip center than those in wiring channel regions outside the chip center. CONSTITUTION:Wiring channel regions 13-3a, 13-2a, and 13-1 are widened as they go toward the central portion. Further, a master chip (substrate) 2 is provided where the number of wiring channels in the wiring channel region 13-1 at the chip central portion is greater than that in the wiring channel regions 13-2a, 13-2b, 13-3a, and 13-3b other than the chip central portion. Accordingly, even if layouts and wirings are performed from the chip central portion and the wirings are complicated at the chip central portion to result in any non- wired portion, the probability of that trouble is reduced and a need of any manual design is also reduced. Hereby, the efficiency of the wirings in a circuit layout is improved and a design interval is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device designed using a gate array method.

[Conventional technology]

In a conventional semiconductor integrated circuit device using a gate array method, a standardized wiring channel region is provided in advance under the gate array. For example, as shown in FIG. 2, wiring channel regions 3-1.・・・
*, and a wiring channel 4 is provided in each wiring channel region. Further, the number of wiring channels in the wiring channel region was configured to be all the same.

[Problem to be solved by the invention]

In the conventional gate array type semiconductor integrated circuit device described above, the number of wiring channels in the wiring channel area is the same regardless of the wiring channel area, so when automatically laying out the circuit you want to design using the gate array. Since the layout and wiring are done from the center of the chip, the wiring in the center of the chip becomes congested as the scale increases, and due to the lack of wiring channels, automatic routing becomes impossible, and manual layout is required. The disadvantage is that more items are required and the design period increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array type semiconductor integrated circuit device that has high efficiency in wiring processing in circuit layout and can shorten the design period.

[Means to solve the problem]

In the gate array type semiconductor integrated circuit device of the present invention, the number of horizontal wiring channels in the wiring channel region is gradually increased in the wiring channel region near the center of the chip compared to the periphery of the chip. It is.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of a chip showing an embodiment of the present invention.

In this embodiment, the wiring channel region is 13-3a.

13-2a and 13-1, which become wider toward the center, and the wiring channel region 13-1 in the center of the chip.
The number of wiring channels in the wiring channel regions 13-2a, 132b, 13-3a, 1.3-3 other than the central part of the chip is
It has more mask chips (base) 2 than the number of wiring channels in b.

With such a configuration, the wiring is arranged and wired starting from the central part of the chip, and even if the wiring becomes congested in the central part of the chip and there are unwired lines, the probability of this occurring is small and the need for manual design is reduced.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which the number of wiring channels in the wiring channel area between the cell arrays in which a plurality of basic cells are arranged in an array is different depending on the wiring channel area, and the number of wiring channels in the wiring channel area in the central part of the chip is configured to be different depending on the wiring channel area. By making the number of wiring channels larger than the number of wiring channels in the wiring channel region other than the central part of the chip, the efficiency of wiring processing in circuit layout is improved, the necessity of manual design can be reduced, and the design period can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a chip layout diagram showing an embodiment of the present invention, and FIG. 2 is a master chip layout diagram showing a conventional example. 1-1 to 1-4.11-1 to 11-4...power line, 2
, 12...Cell array, 3-1.3-2a. -3-3b, 13-1. 13-2a, ---
13-3b... Wiring channel region, 4, 14... Wiring channel, 5.15... Bonding pad.

Claims (1)

[Claims] A gate array type semiconductor integrated circuit device characterized in that the number of horizontal wiring channels in the wiring channel region is gradually increased in the wiring channel region closer to the center of the chip than in the periphery of the chip.