JPH01161729A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To alleviate the complexity of wirings formed at the center of a chip and to easily perform automatic wirings by providing a first wiring channel only region formed in a cross shape at the center, and second wiring channel only region formed in a longitudinal and lateral lattice state on a region except the center. CONSTITUTION:In a semiconductor integrated circuit device of a gate array type in which cell regions 2 laterally regularly arranged with cell transistor group for forming a logic are clearly distinguished from a wiring channel only region used as wirings between the cell regions 2, a first wiring channel only region 4 formed in a cross shape at the center and a second wiring channel only region 5 formed in longitudinal and lateral lattice state except the center are provided. For example, an IC chip 1 formed with bonding pads 3 along the outer periphery is constructed to contain a cross-shaped thick first wiring channel only region 4 formed at the center of the chip 1, and a second wiring channel only region 5 formed longitudinally and laterally except the cross shape of the center.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device designed using a gate array method.

[Conventional technology]

A semiconductor integrated circuit device using the conventional gate array method is
A standardized area dedicated to wiring channels is designed in advance under the gate array.

For example, FIG. 2 is a plan view of an IC chip showing an example of such a conventional technique.

As shown in FIG. 2, the IC chip 11 with the bonding pads 13 formed along the outer periphery forms a dedicated wiring channel area 15 between the cell arrays 12 in which a plurality of basic cells are arranged in an array. Wiring is performed between the cell arrays (cell regions) 12 and the like.

[Problem that the invention seeks to solve]

Generally, in automatic layout of gate arrays, arrangement and wiring are performed from the center of the chip, so there is a problem that the wiring becomes crowded at the center of the chip. However, in the conventional gate array type semiconductor integrated circuit device mentioned above, the area dedicated to wiring channels is only in the horizontal direction, so it is not easy to alleviate the congestion of wiring in the central part. Large function blocks are also increasingly used, and vertical wiring is also becoming more congested. Therefore, conventional semiconductor integrated circuit devices have the drawbacks that automatic wiring is not possible due to an insufficient number of wiring channels, and that manual layout is required, which increases the design period.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that solves problems such as alleviating congestion of wiring formed in the center of a chip and facilitating automatic wiring.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention has gates that clearly distinguish between a cell region in which a group of cell transistors constituting a logic are arranged regularly in the horizontal direction and a wiring channel exclusive region used for wiring between each cell region. In an array-type semiconductor integrated circuit device, a first wiring channel exclusive area formed in a cross shape in the center, and a second wiring channel exclusive area formed in a vertical and horizontal lattice shape in an area other than the central area. It consists of:

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an IC chip showing an embodiment of the present invention.

As shown in FIG. 1, this IC chip 1 has bonding pads 3 formed along its outer periphery and is structured to include wiring channel dedicated regions 4 and 5 in a vertical and horizontal lattice shape.

In this embodiment, the first wiring channel exclusive area 4 with a thick cross formed in the center of the chip 1 is replaced by the second wiring channel exclusive area 5 formed vertically and horizontally outside the central cross area.
A base with a larger number of wiring channels can be obtained.

Therefore, even if placement and wiring are performed from the central part of the chip 1 and the wiring becomes crowded in the central part of the chip, the wiring channel dedicated area 4 in the central part of the chip 1 has a higher number of wiring channels than the other wiring channel dedicated area 5. Since there are many channels, the wiring efficiency is improved, and the vertical wiring channel dedicated area 4
By forming the lines 5 and 5, the wiring efficiency can be improved even in the vertical direction, which has been difficult to wire up until now. With this configuration, automatic layout becomes possible and the design period is shortened.

〔Effect of the invention〕

As explained above, the gate array type semiconductor integrated circuit device of the present invention can perform wiring processing by automatic layout by forming dedicated areas for wiring channels in a vertical and horizontal lattice shape in the central area and areas other than the central area. This has the effect of increasing efficiency and realizing complete automation of wiring for chips.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an IC chip showing an embodiment of the present invention;
FIG. 2 is a plan view of an IC chip showing a conventional example. DESCRIPTION OF SYMBOLS 1... IC chip, 2... Cell area, 3... Ponding pad, 4... First wiring channel exclusive area,
5...Second wiring channel exclusive area.

Claims (1)

[Claims] In a gate array type semiconductor integrated circuit device in which a cell region in which a group of cell transistors constituting a logic is arranged regularly in the horizontal direction and a region dedicated to a wiring channel used for wiring between each cell region are clearly distinguished, A semiconductor integrated circuit comprising: a first dedicated wiring channel region formed in a cross shape in a central portion; and a second dedicated wiring channel region formed in a vertical and horizontal lattice pattern in a region other than the central portion. circuit device.