JPH06120346A - Method for automatically designing semiconductor integrated circuit chip - Google Patents

Abstract

PURPOSE:To design a pattern layout which minimizes dead spaces between input/output circuits and an internal circuit without degrading the chip performance even when placing terminals in ideal terminal positions on the periphery of an LSI chip, predetermined for each lead frame. CONSTITUTION:Patterns of an input circuit 37, output circuit 38, and power supply circuits 39 and 40, are placed on the periphery of an LSI chip, respectively. The pattern of an internal circuit 31 is placed in the internal region on the LSI chip. The title method also includes a step wherein required wiring patterns are formed between those circuits; step, following or preceding the step above, wherein an input terminal 33, output terminal 34 and power supply terminals 35 and 36 are placed in the ideal terminal positions on the periphery of the LSI chip, predetermined according to lead frames to be mounted with chips; step wherein connecting wiring patterns 41-44 are formed between the input circuit and input terminal, between the output circuit and output terminal, and between the power supply circuits and power supply terminals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically designing a semiconductor integrated circuit chip, and more particularly to a method for automatically designing a pattern layout on a large scale integrated circuit (LSI) chip with the aid of a computer.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a pattern layout on a conventional LSI chip.

An internal circuit 50 is arranged in the central area of the chip, and a terminal row and an input / output circuit area are arranged in the peripheral area of the chip. In the terminal row, an input terminal 51, an output terminal 52, a first power supply terminal 53, a second power supply terminal 54
2 are arranged in the input / output circuit area so as to pass over the input circuit 61, the output circuit 62 and these.
Book power supply wires 63 and 64 are arranged.

FIG. 6A shows the pattern of the input circuit block 71 in which the input terminal 51 and the input circuit 61 in FIG. 5 are connected, and FIG. 6B shows the output in FIG. The pattern of the output circuit block 72 in which the terminal 52 and the output circuit 62 are connected is shown.

FIG. 7A shows the first power supply terminal 5 in FIG.
7 shows a pattern of the first power supply wiring circuit block 73 in which the third power supply wiring 63 and the first power supply wiring 63 are connected to each other.
5B shows a pattern of the second power supply wiring circuit block 74 to which the second power supply terminal 54 and the second power supply wiring 64 in FIG. 5 are connected.

Each circuit block (peripheral circuit block)
The patterns 71 to 74 are registered in the LSI chip automatic designing apparatus as an automatic designing library and can be used as needed. FIG. 8 is a plan view showing an example of a state in which a terminal row of an LSI chip and a lead frame are connected by a bonding wire.

The LSI chip 80 is mounted on the bed portion of the lead frame, and the terminal 81 of the chip and the inner lead portion 82 of the lead frame are connected by the bonding wire 83. FIG. 9 shows a part of FIG. 8 taken out and enlarged, and shows inspection items in the bonding design.

Here, L1 is the distance between the bonding wire connection ends, L2 is the distance between the terminals, and θ is the angle of incidence of the bonding wire on the lead frame. A judgment is made as to whether or not the electrical connection with the frame can be guaranteed, that is, whether or not the bonding design is possible.

Each inspection item in the above bonding design is limited, and there is a restriction on the arrangement position of each terminal. The terminal position around the LSI chip calculated in consideration of these restrictions is called an ideal terminal position, which is determined for each lead frame to be mounted on the chip. When designing a pattern layout on an LSI chip, it is desirable to arrange each terminal at an ideal terminal position corresponding to the lead frame to be mounted on the chip.

However, conventionally, when automatically designing a pattern layout on an LSI chip, even if each terminal is arranged at an ideal terminal position, as described above, the peripheral circuit block 7 is formed.
When the positions of the terminals 51 to 54 are determined in 1 to 74, the positions of the circuits 61 to 64 connected thereto are also determined naturally. Due to this, the dead space between the input circuit 61 or the output circuit 62 and the internal circuit 50 increases, and the chip size increases.

[0011]

As described above, according to the conventional method for automatically designing an LSI chip, even if each terminal is arranged at an ideal terminal position around the LSI chip, if the position of the terminal is determined in the peripheral circuit block, The fact that the position of the circuit connected to this is also determined by itself has been one of the factors that hinder the miniaturization of the chip size.

The present invention has been made to solve the above-mentioned problems, and even when each terminal is arranged at an ideal terminal position around the LSI chip which is determined for each lead frame to be mounted on the chip, the automatic layout program is used. , L
An object of the present invention is to provide an automatic design method of a semiconductor integrated circuit chip capable of designing a pattern layout in which a dead space between an input circuit or an output circuit and an internal circuit is suppressed to a minimum without impairing the function of the SI chip. To do.

[0013]

According to the present invention, a pattern of a plurality of circuit blocks accommodating functional circuits is arranged on a mask area for creating a pattern of an LSI chip area, and the plurality of circuit blocks are arranged. Buildings that form wiring patterns between them to achieve desired integrated circuit patterns
In an automatic design method of a block type semiconductor integrated circuit chip, each pattern of an input circuit, an output circuit, and a power supply wiring circuit of an LSI is arranged in a peripheral area of the LSI chip, and a pattern of an internal circuit of the LSI is arranged in an internal area of the LSI chip. The step of arranging and forming the required wiring pattern between each circuit, and before or after this step, input terminals, output terminals, power supply terminals are placed at ideal terminal positions in the LSI chip peripheral area determined by the lead frame to be mounted on the chip. Arranging, and the input circuit, the output circuit,
And a step of forming a connection wiring pattern between each pattern of the power supply wiring circuit and the corresponding input terminal, output terminal, and power supply terminal.

[0014]

Operation: The input terminal and the input circuit on the LSI chip are separate blocks, the output terminal and the output circuit are separate blocks,
Separate blocks for the first power supply terminal and the first power supply wiring,
Since the second power supply terminal and the second power supply wiring are treated as separate blocks, the circuits, the power supply wirings, and the terminals can be freely arranged at optimal positions without being restricted by each other. .

Therefore, the automatic layout program makes it possible to design the pattern layout in which the dead space between the input circuit or the output circuit and the internal circuit is suppressed to the minimum without impairing the function of the LSI chip. The chip size can be reduced.

Furthermore, by registering the pattern layout of the terminal block in which each terminal is arranged at the ideal terminal position around the LSI chip determined for each lead frame to be mounted on the chip as an automatic design library,
Optimal terminal arrangement can be achieved simply by selecting a desired terminal block corresponding to the lead frame on which the chip is to be mounted.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a flowchart showing an example of a method for automatically designing a semiconductor integrated circuit chip according to the present invention. Figure 2
Shows an example of the connection description of the terminal block as a part of the connection description language for the automatic layout program for realizing the flowchart of FIG.

In this connection description, A represents the number of terminals, B represents the terminal number, C represents the terminal center coordinate X, and D represents the terminal center coordinate Y. In this example, the number of terminals is 144, and the first terminal is 320 μm in the X-axis direction and 25331 μm in the Y-axis direction.
It is indicated that is placed as the center coordinate. Figure 3
In step S1 of FIG. 1, the pattern of the terminal block is registered as an automatic design library of the automatic design apparatus. FIG. 4 shows L realized by the method of FIG.
An example of SI pattern is shown.

Here, 30 is an LSI chip region, 31 is an internal circuit arranged in the chip central region, 32 is a terminal block arranged in the chip peripheral region, and the input terminal 3
3, an output terminal 34, a first power supply terminal 35, and a second power supply terminal 36.

Reference numeral 37 denotes an input circuit arranged in the chip peripheral area, 38 denotes an output circuit arranged in the chip peripheral area, and 39.
And 40 are the first power supply wiring and the second power supply wiring arranged in the peripheral area of the chip.

Reference numeral 41 is a connection wiring formed between the input circuit 37 and the corresponding input terminal 33, 42 is a connection wiring formed between the output circuit 38 and the corresponding output terminal 34, and 43 is the above-mentioned connection wiring. A connection wiring formed between the first power supply wiring 39 and the first power supply terminal 35, and a connection wiring 44 formed between the second power supply wiring 40 and the second power supply terminal 36. .

Next, referring to FIGS. 1 to 4, LS
A building in which a pattern of a plurality of circuit blocks accommodating functional circuits is arranged on a pattern region corresponding to an I-chip region and a wiring pattern is formed between the plurality of circuit blocks to realize a desired integrated circuit pattern. An example of a method of automatically designing a block type semiconductor integrated circuit chip will be described.

In step S1, a pattern of a terminal block in which an input terminal, an output terminal, and a power supply terminal are arranged at an ideal terminal position in the peripheral area of an LSI chip determined for each lead frame to be mounted on the chip is automatically determined by the automatic design apparatus. Register as a design library in advance.

In step S2, each pattern of the input circuit, output circuit, and power supply wiring circuit of the LSI is set to L.
The wiring pattern is arranged in the peripheral area of the SI chip and the pattern of the internal circuit is arranged in the internal area of the LSI chip to form a required wiring pattern between the circuits.

In step S3, input terminals, output terminals, and power supply terminals are arranged at ideal terminal positions in the peripheral area of the LSI chip determined by the lead frame to be mounted with the chip. At this time, a desired terminal block pattern corresponding to the lead frame to be mounted on the chip is selected from the automatic design library. Then, it is arranged in the peripheral area of the LSI chip, and a required wiring pattern is formed between the respective circuits. The order of steps S2 and S3 may be interchanged. In step S4, a wiring pattern is formed between the input terminal, the output terminal, and the power supply terminal corresponding to each pattern of the input circuit, the output circuit, and the power supply wiring circuit.

[0026]

As described above, according to the present invention, even when each terminal is arranged at an ideal terminal position around the LSI chip, which is determined for each lead frame in which the chip is to be mounted, the LSI layout of the LSI chip is determined by the automatic layout program. It is possible to provide an automatic designing method of a semiconductor integrated circuit chip capable of designing a pattern layout in which a dead space between an input circuit or an output circuit and an internal circuit is suppressed to a minimum without impairing its function.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of a method for automatically designing a semiconductor integrated circuit chip according to the present invention.

FIG. 2 is a diagram showing an example of a connection description of a terminal block as a part of a connection description language for an automatic layout program for realizing the flowchart of FIG.

FIG. 3 is a diagram showing a state in which a pattern of a terminal block is registered as an automatic design library of an automatic design device in step S1 of FIG.

FIG. 4 is a diagram showing an example of an LSI pattern realized by the method of FIG.

FIG. 5 is a diagram showing an example of a pattern layout on a conventional LSI chip.

FIG. 6 is a diagram showing patterns of an input circuit block and an output circuit block in FIG.

7 is a diagram showing patterns of the first power supply wiring circuit block and the second power supply wiring circuit block in FIG.

FIG. 8 is a plan view showing an example of a state in which an LSI chip and a lead frame are connected by a bonding wire.

9 is a view showing a part of FIG. 8 taken out and enlarged, and showing inspection items in a bonding design.

[Explanation of symbols]

30 ... LSI chip area, 31 ... Internal circuit, 32 ... Terminal block, 33 ... Input terminal, 34 ... Output terminal, 35 ... First power supply terminal, 36 ... Second power supply terminal, 37 ... Input circuit, 38 ... Output Circuits, 39, 40 ... Second power supply wiring, 4
1-44 ... Connection wiring.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yuichiro Sanuki, 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa, Toshiba Microelectronics Co., Ltd. In Microelectronics Co., Ltd. (72) Masanao Akutagawa 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Inside Toshiba Microelectronics Co., Ltd.

Claims (2)

[Claims] 1. A desired pattern is formed by arranging a pattern of a plurality of circuit blocks accommodating functional circuits on a mask area for forming a pattern of an LSI chip and forming a wiring pattern between the plurality of circuit blocks. In the method of automatically designing a semiconductor integrated circuit chip of a building block method that realizes the integrated circuit pattern, the patterns of the input circuit, the output circuit, and the power supply wiring circuit of the LSI are arranged in the peripheral area of the LSI chip.
The step of arranging the pattern of the internal circuit of the LSI in the internal area of the LSI chip and forming the required wiring pattern between each circuit, and before or after this step, the peripheral area of the LSI chip determined by the lead frame to be mounted on the chip. The step of arranging the input terminal, the output terminal, and the power supply terminal at the ideal terminal position, and then connecting between the input terminal, the output terminal, and the power supply terminal corresponding to each pattern of the input circuit, the output circuit, and the power supply wiring circuit. A method for automatically designing a semiconductor integrated circuit chip, comprising: forming a wiring pattern. 2. The method for automatically designing a semiconductor integrated circuit chip according to claim 1, further comprising: an LS determined for each lead frame to be mounted on the chip.
A pattern of a terminal block in which input terminals, output terminals, and power supply terminals are arranged at ideal terminal positions in the peripheral area of the I-chip is registered in advance as an automatic design library, and the input terminals, output terminals, and power supply terminals are arranged. At this time, a pattern of a desired terminal block is selected from the above-mentioned library for automatic design, and an automatic design method for a semiconductor integrated circuit chip is characterized.