JPH09312340A - Manufacture of semiconductor chip and thereby formed semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently produce various types of semiconductor chips by forming equally sectioned chip regions on a semiconductor wafer with input/output circuit blocks and functional circuit blocks and dicing the wafer into individual semiconductor chips. SOLUTION: For functional circuit blocks C11 -C14 having mutually different functions are formed on the central area of a C-pattern e.g. in a gate array system. As the area is small, different wiring designs are applied to entirely formed common basic cells to form four functions collected on one chip region 1a. Around the collected functional circuits C11 -C14 , input/output circuit blocks C21 for transferring signals from and to externals are formed. Since the functional circuit blocks having a smaller area than that of IMS are collectedly formed on one chip region 1a, various types of chips can be produced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to the manufacture of semiconductor chips.

[0002]

2. Description of the Related Art In the manufacturing of semiconductors, in order to reduce the cost of semiconductor chips which can be mass-produced, the manufacturing method and the parts used are standardized, and the diameter of the semiconductor wafer is increased to increase the number of semiconductor chips to be acquired. Things are being done.

Here, in response to a user's demand for increasing the added value of a system product in a semiconductor device, the maker side provides a semiconductor device for a specific application with a short TAT (Turn).
Arround Time) is required to develop, prototype, and check the operation. Then, various methods are conceivable in order to carry out such a diversification of user needs in order to carry out small-lot production of various products.

For example, a technique of limiting the number of lots of semiconductor wafers at the time of start of construction or a single-wafer processing in order to prevent over-fabrication, a plurality of photomasks for wiring layer wiring in the gate array method, or a direct electron beam For example, a technique of forming different types of chip regions of the same size on a semiconductor wafer by using a plurality of types of writing data in a writing method. As an example in which the technology relating to the multi-product development of semiconductor chips is described in detail, for example, Nikkei BP
Published by the company, "Latest ASIC design technique '94" (issued July 20, 1993), P25 ~ P40.

[0005]

In the high-mix low-volume production, it is necessary to produce the required number of semiconductor chips without excess and deficiency and at low cost.

However, in the above-mentioned technique, the number of semiconductor chips obtained from one semiconductor wafer may be more than the required number, and at this time, the semiconductor chips are not needed due to the excess.

Further, when the semiconductor chip is formed in a chip area which is evenly divided on the semiconductor wafer, the area required for realizing the required function is not required up to the area of this chip area. There is also. Since it is not admitted from the dicing point that the chip areas of one semiconductor wafer are made different, in such a case,
An empty area will be generated in the manufactured semiconductor chip. It is sufficient if the empty area is small, but if it takes up more than half the space of the semiconductor chip, the increase in manufacturing cost cannot be ignored.

Therefore, an object of the present invention is to provide a technique capable of efficiently manufacturing a wide variety of semiconductor chips.

Another object of the present invention is to provide a technique capable of manufacturing various kinds of semiconductor chips at low cost.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the method for manufacturing a semiconductor chip according to the present invention is an input / output circuit for exchanging signals with a part of a plurality of chip regions evenly divided on a semiconductor wafer. It is characterized in that it is formed by blocks and a plurality of functional circuit blocks, and a semiconductor wafer is diced and divided into individual semiconductor chips.

In this case, the plurality of functional circuit blocks can be formed by applying different wiring designs to the common basic cell. The input / output circuit block is
It can be shared by a plurality of functional circuit blocks.

A semiconductor chip according to the present invention is characterized by being obtained by the above-mentioned method for manufacturing a semiconductor chip.

According to the above-mentioned means, the number of types of circuit patterns that can be formed on one semiconductor wafer increases, and it becomes possible to efficiently manufacture various types of semiconductor chips.

Further, since the substantial number of chips to be obtained per semiconductor wafer is increased, semiconductor chips can be efficiently obtained, and a wide variety of semiconductor chips can be manufactured at low cost.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic view showing a semiconductor wafer according to an embodiment of the present invention, and FIGS. 2, 3 and 4 are explanatory views showing a circuit arrangement in a chip region built in the semiconductor wafer of FIG. It is a figure.

As shown in FIG. 1, the semiconductor wafer 1 in this embodiment has 52 chip regions 1a which are evenly divided.
Are formed. The area of the chip region 1a is set in accordance with the pattern (A pattern described later) having the largest area in the circuit layout built in the semiconductor wafer 1. However, in consideration of productivity, for example, the area may be set to the area where the number of sheets to be produced is most expected. Of these chip areas 1a, 13 patterns have A-pattern circuit arrangements, 13 patterns have B-patterns, and 26 patterns have C-patterns.
Each pattern is formed. That is, in the present embodiment, the required number of patterns A to C is, for example, "1: 1: 2", and accordingly, 1 is required.
Each of the patterns 3, 13, and 26 is formed. The number of chip areas 1a, the number of patterns, and the number of pattern distributions described above are merely examples, and the present invention is not limited to these.

The circuit layout of each pattern is shown in FIGS.

The pattern A shown in FIG. 2 is, for example, a DRAM.
(Dynamic Random Access Memory), and the functional circuit block A, which is a memory cell, is shown in the central portion indicated by diagonal lines.
Reference numeral ₁₁ denotes an input / output circuit block A ₂₁ for transmitting and receiving a signal to and from the peripheral portion so as to be in contact with this.

The B pattern shown in FIG. 3 is, for example, S
A RAM (Static Random Access Memory) is configured, and a functional circuit block B _11, which is a memory cell, is formed in the central portion indicated by diagonal lines. This functional circuit block B ₁₁
An input / output circuit block B ₂₁ is formed in the peripheral portion with a space therebetween. In this B pattern, the functional circuit block B
_Since the required space of ₁₁ is not as large as in the case of the pattern A, a vacant area (the portion shown by white in FIG. 3) is shown, but in reality, wiring is formed in this portion. In forming the B pattern, the functional circuit block B ₁₁ and the input / output circuit block B ₂₁ are considered to be combinations of different elements, and the circuit operation is confirmed in advance by using the input / output circuit block A ₂₁ of the A pattern. After that, the functional circuit block B ₁₁ having an optimum area can be formed on the semiconductor wafer 1.

Here, the A pattern is DRAM and the B pattern is SRAM. However, various other semiconductor circuits such as a logic circuit using a gate array system can be formed, and the present invention is not limited thereto. Not a thing.

The C pattern shown in FIG. 4 has four functional circuit blocks C ₁₁ and C having centrally different functions.
₁₂ , C ₁₃ and C ₁₄ are formed by, for example, a gate array method. That is, although the functional circuit blocks are originally formed in the respective chip regions 1a one by one, since the area is small, different wiring designs are applied to the common basic cells formed over the entire area to obtain one chip. Area 1a
It is formed as a set of four types of functions.
However, logic circuits are generally used as the functional circuit blocks C ₁₁ , C ₁₂ , C ₁₃ , and C ₁₄ configured by the gate array method, but circuit connections are combined to form a memory circuit,
A part may be a logic circuit and the other part may be a memory circuit. Further, a memory circuit such as SRAM and a logic circuit or memory circuit using a gate array may be simultaneously formed on one chip. Further, the functional circuit blocks C ₁₁ , C ₁₂ , C ₁₃ and C ₁₄ may be formed by a technique other than the gate array method. The number of functional circuit blocks is not limited to four as long as it is plural.

Collected functional circuit blocks C ₁₁ , C ₁₂ , C
_An input / output circuit block C ₂₁ for exchanging signals with the outside is formed in the peripheral portions of ₁₃ and C ₁₄ . The input / output circuit block C ₂₁ is a plurality of the functional circuit blocks C described above.
_It is shared by ₁₁ , C ₁₂ , C ₁₃ , and C ₁₄ to reduce the area. Therefore, one of the functional circuit blocks C ₁₁ and C
An electrical test when ₁₂ , C ₁₃ and C ₁₄ are new circuits is performed using this input / output circuit block C ₂₁ . However,
The input / output circuit block C ₂₁ does not necessarily have to be shared.

Each functional circuit block C ₁₁ , C ₁₂ , C
_{By making 13} and C ₁₄ complementary to each other having the same function, any of the functional circuit blocks C ₁₁ , C ₁₂ , C ₁₃ and C ₁₄ determined to be defective as a result of the electrical test is replaced by another. Good. Further, when four functional circuit blocks C ₁₁ , C ₁₂ , C ₁₃ , and C ₁₄ are formed as in the present embodiment, that is, an even number, the two functional circuits block C ₁₁ , C ₁₂ , C ₁₃ , and C ₁₄ form a set and have a pair relationship. The functional circuit blocks C ₁₁ and C ₁₂ and the functional circuit blocks C ₁₃ and C ₁₄ may be complementary to each other and have mutually different functions in relation to other pairs.

The semiconductor wafer 1 having the A to C patterns formed in the chip area 1a is diced along the scribe area and divided into individual semiconductor chips. After that, the semiconductor device is mounted on a lead frame and electrically connected to the leads, and is sealed and cut and molded into a finished product as a semiconductor device.

As described above, according to the present embodiment, the IMS
Since the functional circuit blocks C ₁₁ , C ₁₂ , C ₁₃ and C ₁₄ having a small area are collectively formed in one chip region 1a (C pattern) by (Integrated Mask System), they are formed on one semiconductor wafer. As the number of possible circuit patterns increases, it becomes possible to efficiently manufacture a wide variety of semiconductor chips.

Further, since the substantial number of chips to be obtained per one semiconductor wafer is increased, the semiconductor chips can be efficiently obtained, so that various kinds of semiconductor chips can be manufactured at low cost. Become.

Furthermore, since semiconductor chips can be obtained by performing the same wafer process as the conventional one using the existing equipment without introducing a new manufacturing apparatus, it is possible to economically produce a large variety of semiconductor chips in small quantities. be able to.

Since various kinds of semiconductor chips can be obtained by the same wafer process as the conventional one, the chip manufacturing time can be shortened.

The invention made by the present inventor has been specifically described above based on the embodiments thereof, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

[0033]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1). That is, according to the present invention, the number of types of circuit patterns that can be formed on one semiconductor wafer increases, and it becomes possible to efficiently manufacture a wide variety of semiconductor chips.

(2) In addition, since the number of chips substantially obtained per semiconductor wafer increases, semiconductor chips can be efficiently obtained, and a wide variety of semiconductor chips can be manufactured at low cost. It will be possible.

(3) Further, since semiconductor chips can be obtained by using the existing equipment and undergoing the same wafer process as the conventional one, it is possible to economically carry out the production of various kinds of semiconductor chips in small quantities.

(4). Since various kinds of semiconductor chips can be obtained by the same wafer process as the conventional one, the chip manufacturing time can be shortened.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a semiconductor wafer according to an embodiment of the present invention.

2 is an explanatory diagram showing a circuit arrangement of an A pattern formed in a chip region of the semiconductor wafer of FIG.

3 is an explanatory diagram showing a circuit layout of a B pattern formed in a chip area of the semiconductor wafer of FIG.

4 is an explanatory diagram showing a circuit layout of a C pattern formed in a chip area of the semiconductor wafer of FIG.

[Explanation of symbols]

1 Semiconductor Wafer 1a Chip Area A ₁₁ Functional Circuit Block A ₂₁ Input / Output Circuit Block B ₁₁ Functional Circuit Block B ₂₁ Input / Output Circuit Block C ₁₁ , C ₁₂ , C ₁₃ , C ₁₄ Functional Circuit Block C ₂₁ Input / Output Circuit Block

Claims (4)

[Claims] 1. A part of a plurality of chip regions equally divided on a semiconductor wafer is formed by an input / output circuit block and a plurality of functional circuit blocks for transmitting / receiving a signal to / from the outside. A method of manufacturing a semiconductor chip, characterized by dicing the semiconductor wafer into individual semiconductor chips. 2. The method of manufacturing a semiconductor chip according to claim 1, wherein the plurality of functional circuit blocks are formed by applying different wiring designs to a common basic cell. Production method. 3. The method of manufacturing a semiconductor chip according to claim 1, wherein the input / output circuit block is shared by a plurality of the functional circuit blocks. 4. A semiconductor chip obtained by the method for manufacturing a semiconductor chip according to claim 1.