JPH11121723A - Semiconductor integrated circuit device and reticle for base element manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated device and a base element manufacturing reticle capable of increasing the use efficiency of a gate array by the effective utilization of the number of base elements corresponding to the number of used elements. SOLUTION: The units U repeated in units of a reticle on a semiconductor wafer 11 are the assembly of base element regions A divided into a plurality of chip corresponding regions in units of a reticle. On the peripheries of respective base element regions A, pad regions 12 are arranged while the regions A are separated by dicing lines 13. Besides, the use number of the base element regions A are made variable corresponding to the number of used elements. In such a constitution, when a plurality of the base element regions A are used, the connection wiring between separated regions A is connected by the pad region 12 and the dicing lines 13 so as to realize a desired gate array IC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is designed to quickly and from the underlayer by changing only the layer after the interconnection or after the contact while using the underlying element before the upper layer wiring or the contact, particularly the Al layer, in common. The present invention relates to a semiconductor integrated circuit device and a reticle for fabricating a base element which can produce an IC at a lower development cost.

[0002]

2. Description of the Related Art Semi-custom ICs can reduce the design cost, in particular, by producing a wide variety of ICs by changing only a part of the manufacturing process. Suitable for high-mix low-volume production and greatly shortens the development period. However, there is much waste and the area utilization efficiency is not good.

A typical method for producing a semi-custom IC is a gate array. This uses a base element in which cells composed of a group of elements forming a gate are regularly and repeatedly arranged. The term “underlying element” here means an element in which only an element is formed on a substrate except for a wiring portion formed in a later step. The elements, MOS FET, junction FET, NPN, PNP bipolar transistors, resistors, I ² L such as a capacitor (Integrated injecti
on Logic). By determining only the wiring pattern on the base element substrate according to the logic circuit diagram, an IC that realizes the necessary functions is manufactured. This manufacturing method is also called a master slice method.

In the conventional gate array IC technology, a semiconductor device is manufactured by simply combining wiring area data of the same chip size with a base element (also referred to as a base chip) corresponding to one chip size. For this reason, if the number of elements used is considerably smaller than the number of elements formed on the underlying chip, the utilization efficiency of the elements decreases, and there is a disadvantage that an IC is economically expensive for the number of circuit elements. Was.

On the other hand, if the number of elements used is larger than the number of elements formed on the underlying chip, the circuit must be divided into two or more chips, and a desired circuit configuration can be realized by a plurality of gate array ICs. Will be achieved. The cost increases with the use of multiple chips. Furthermore, when incorporated in a product, a larger portion is required as an occupied area. Therefore, the advantage of volume reduction by the integrated circuit is impaired.

In order to avoid the above problems, it is necessary to prepare bases corresponding to chips of various sizes. However, when various types of base chips are available,
As a result, the cost of fabricating the base increases, which is very disadvantageous economically. Also, in the semiconductor industry where the technological progress is remarkable, even if a large number of base chips of various sizes are prepared according to the used element scale, the process becomes obsolete quickly, it is not used in a short period of time, and only waste increases. is there.

[0007]

It is clear that preparing various types of bases corresponding to chips of various sizes is economically disadvantageous and wasteful, but an optimum chip base for the number of elements to be used is not appropriately prepared. As long as the above semi-custom I
The cost reduction and the optimization for integration cannot be realized in the gate array itself in C.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor integrated circuit device and a semiconductor integrated circuit device capable of realizing optimal and effective use of a base with respect to the number of elements used, reducing the cost of a gate array and realizing high integration. An object of the present invention is to provide a reticle for producing a base element.

[0009]

According to the present invention, there is provided a semiconductor integrated circuit device comprising: a substrate on which a base element region divided into a plurality of chips corresponding to reticle units is formed; A wiring in which the number of use of the base element region is variable, and wiring is enabled between the divided base element regions, and an arbitrary chip size corresponding to the use number of the base element region is selectively selected. It is characterized by having.

A reticle for fabricating a base element according to the present invention includes a plurality of base element areas each having a pad area provided therearound, and a first dicing in which the base element area is divided into a plurality of chip equivalent areas each having a minimum unit. Line section,
All of the divided base element regions are defined as a unit,
A second dicing line provided on the outermost periphery of the unit on which alignment marks for manufacturing on a wafer are formed. According to the present invention, the use efficiency of the underlying element is increased by making the element size of the underlying element variable according to the circuit scale of the element.

[0011]

FIG. 1 is a conceptual diagram of a bare chip in a semiconductor integrated circuit device constituted by a reticle according to a first embodiment of the present invention. Semiconductor wafer 11
The unit U, which is repeated on a reticle basis, is composed of a group of base element regions divided into a plurality of chip equivalent regions on a reticle basis. For example, here, four base element regions A are formed. A pad region 12 is provided around each base element region A.
The base element regions A are divided by dicing line portions 13 therebetween. Further, the dicing line portion 14 of the unit U is provided on the outermost periphery of a group of four base element regions A.

The present invention is characterized in that the number of use of the base element region A is variable according to the number of elements used. When a plurality of base element regions A are used, connection wirings are connected between the divided base element regions A through the pad regions 12 and the dicing line portions 13 to realize a desired gate array IC.

The four base element regions A have substantially the same structure. Thus, the semiconductor integrated circuit device of the present invention can select an arbitrary chip size according to the number of used base element regions A. For example, when forming an IC chip that requires only one base element region A, the four base element regions A are divided along all dicing line portions 13 and 14 to produce IC chips 151 to 154. When forming an IC chip in which two base element regions A are sufficient, the four base element regions A are
It is divided along a part of 4 and 13 to produce two IC chips 161 and 162. When an IC chip is configured using all four base element regions A, the IC chip is divided along the dicing line portion 14 to produce one IC chip 171.

In the above configuration, substantially the pads are formed and used in the outermost pad region 12 of the chip configuration corresponding to the selected arbitrary chip size. The pad region 12 existing inside other than the outermost periphery has no pad actually formed, is covered with an insulating layer, and is configured to be used as a wiring region.

In the above configuration, for example, the data configuration for the process in the pad region is divided into a base and a wiring stage. Thus, in the base element manufacturing stage, island-shaped regions (for example, N-type regions having a lower concentration than P-type regions) are formed in the pad regions for forming all pads in the substrate. . The pads are actually formed on the surface only of the outermost peripheral pads of the underlying element structure handled by the chip size to be used. In other words, when the pad area inside the reticle becomes a wiring area, the data at the wiring stage is changed to have a data configuration to make the wiring area. afterwards,
According to the wiring connection data, the pad area inside the chip size not used as a pad is used as a wiring area.

FIG. 2 is a plan view showing a reticle constituting a base element for a semiconductor integrated circuit according to a second embodiment of the present invention. As a basic unit to be repeated on a wafer, a reticle is formed in a 4 × 4 chip configuration with 1000 elements in a base element area. Pad regions 21 are provided around each of the underlying element regions B, and the number of connectable pads is 16 in this case. Marks necessary for manufacturing on the wafer that hinder wiring are formed only in the dicing line portion 23 (oblique lines) of the outermost frame of the reticle. The reason for this is that the formation in the dicing line portion 22 inside the reticle hinders the wiring between the underlying element regions from passing over the dicing line.

In this embodiment, since the number of base element regions (number of base chips) on one side of the reticle is 4, the integer that can be divided is 2 or 4, whereby one base unit takes 4 × 4 pieces and 4 × 2 pieces. Take 2 × 2 pieces
A gate array type semiconductor integrated circuit device corresponding to five circuit scales of 2 × 1 and 1 × 1 can be configured.

According to the above configuration, as shown in the example of selectable chip size in FIG. 3, the following IC chips can be configured for each reticle. In 4 × 4, 1 chip with 16000 elements and 76 usable pads. For 4x2, 2 chips with 8000 elements and 56 usable pads. In 2 × 2, 4 chips with 4000 elements and 36 usable pads. In 2x1 cavities, 2000 chips, 8 pads with 26 usable pads. For 1 × 1 unit, 1000 chips, 16 chips with 16 usable pads.

As a result, from 16,000 elements to 1000
It can be economically and efficiently manufactured to meet the requirements of a gate array IC up to a circuit size smaller than the element. According to each of the above embodiments, a plurality of base element region units are provided in a reticle unit, and divided by a dicing line unit,
By selecting an optimum number of base elements according to the number of base elements constituting the IC chip, it is possible to form a uniformly integrated IC chip having a high use efficiency of the gate array element and uniformly integrated. Therefore, a large amount of initial investment such as preparing various kinds of base chips according to the circuit scale to be used is not required, and one base can support ICs of various circuit scales. Therefore, the influence on obsolescence accompanying the miniaturization of the process can be reduced.

[0020]

As described above, according to the present invention,
Since the number of base element regions can be selected according to the IC to be constructed, even when a gate array is used, the use efficiency of the elements is high, and therefore, a small-sized semiconductor integrated circuit device with high integration degree Can be provided. This technology is
Since as many IC chips as possible are obtained from one wafer, a semiconductor integrated circuit device with reduced cost can be provided.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a bare chip in a semiconductor integrated circuit device configured by a reticle according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a reticle constituting a base element of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a plan view showing an example of a chip size selectable from the configuration of FIG. 2;

[Explanation of symbols]

 U: Units repeated in reticle units A, B: Base element region 11: Semiconductor wafer 12, 21, Pad region 13, 14, 22, 23 Dicing line portions 151-154, 161, 162, 171 IC chip

Claims (8)

[Claims] 1. A substrate on which a base element region divided into a plurality of chip-equivalent regions in units of a reticle is formed, and the number of the base element regions used is variable according to the number of elements used. A wiring capable of being connected between the underlying element regions, and selectively having an arbitrary chip size according to the number of the underlying element regions used. 2. The semiconductor integrated circuit device according to claim 1, wherein the underlying element regions of each of the chip equivalent regions have substantially the same structure. 3. The semiconductor integrated circuit device according to claim 1, wherein the base element regions are divided by a dicing line portion. 4. The semiconductor integrated circuit according to claim 1, wherein said base region corresponding to said chip size is configured to be divisible by each side in said reticle unit. apparatus. 5. The base element region includes a pad region around the base element region, and a pad is formed substantially in a pad region on an outermost periphery of a chip configuration corresponding to the arbitrary chip size with respect to the base element region. 5. The semiconductor integrated circuit device according to claim 1, wherein the device is used. 6. A base element region divided on a substrate by a dicing line portion, a pad region provided around the inside of the base element region, and the number of use of the base element region according to the number of elements used m
.Times.n wirings configured as one IC chip, and the base element region is divided into a plurality of M.times.N chip-equivalent regions separated by the dicing line portion in reticle units. Where M / m and N / n are integers,
The semiconductor integrated circuit device, wherein when xn is greater than 1, the wiring passes at least over the pad region and the dicing line portion. 7. A plurality of base element regions each provided with a pad region around the periphery, a first dicing line portion in which each of the base element regions is divided as a plurality of chip equivalent regions of a minimum unit, All underlying element regions as a unit,
A reticle for fabricating a base element, comprising: a second dicing line portion provided on the outermost periphery of the unit on which alignment marks for manufacturing on a wafer are formed. 8. The reticle according to claim 6, wherein the underlying element regions have substantially the same shape.