JPS61199647A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61199647A JPS61199647A JP60040483A JP4048385A JPS61199647A JP S61199647 A JPS61199647 A JP S61199647A JP 60040483 A JP60040483 A JP 60040483A JP 4048385 A JP4048385 A JP 4048385A JP S61199647 A JPS61199647 A JP S61199647A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output buffer
- circuit
- chip
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000010411 cooking Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（Ｍ東上の利用分野）
本発明は半導体集積回路装置に関し、特にＤＡ（Ｄｅｓ
ｉｇｎ Ａｕｔｏｍａｔｉｏｎ ）処理によりレイ７
’）ト構成したマスタスライス方式の半導体集積回路装
置に関するものである０
（従来技術）
近年、半導体集積回路装置は高密匿化及び大規模化して
来ており、集積度の増大は論理回路において入力、出力
の信号ピンの増大となシ、多信号ピン化の方向にある０
また設計製造期間の短縮の為にマスタスライス方式が注
目されている０第３図は従来のＤＡ処理によるマスタス
ライス方式のテ、グ構成を説明するためのレイアワト図
である。第３図においてｌはテ、グ外周、２は入出力バ
ッファ回路ブロックで、チックの周辺に規則的に並べら
れている０３は論理回路部で、各品積に共通な素子が基
本セルとしてプレイ伏に配置され、任意の論理機能をＤ
Ａ処理により実現するところであるｏ４はパッド、４′
は空パ、ドを示す。空パ、ド４′は通常電源パッドとし
て利用される。５．６．７．８の周辺領域はチェ、り素
子。DETAILED DESCRIPTION OF THE INVENTION (Field of Application of M Tojo) The present invention relates to a semiconductor integrated circuit device, and particularly to a DA (Design) device.
ign Automation) processing causes Ray 7
(Prior art) In recent years, semiconductor integrated circuit devices have become highly dense and large-scale, and the increase in the degree of integration has led to the input of logic circuits. , without increasing the number of output signal pins, there is a trend towards multi-signal pins.
In addition, the master slice method is attracting attention in order to shorten the design and manufacturing period. FIG. 3 is a layout diagram for explaining the text structure of the master slice method using conventional DA processing. In Figure 3, l is the periphery of the tick, 2 is the input/output buffer circuit block, and 03, which are regularly arranged around the tick, is the logic circuit section, in which elements common to each product are played as basic cells. Placed face down, any logical function D
o4, which is achieved by processing A, is a pad, 4'
indicates an empty pad or do. Empty pads and pads 4' are normally used as power supply pads. The surrounding area of 5.6.7.8 is a Che, Ri element.
商標９品名、その他のチェックパターン（以下周辺パタ
ーンと称す）が配置されている。周辺パターンは論理回
路を構成する素子以外の製造上必要なパターンである。Nine trademark product names and other check patterns (hereinafter referred to as peripheral patterns) are arranged. The peripheral pattern is a pattern necessary for manufacturing other than the elements constituting the logic circuit.
テップの周辺に配置された入出力パラフッ回路ブロック
２の数が信号ビンの数となる。The number of input/output parallel circuit blocks 2 arranged around the step is the number of signal bins.
（発明の解決すべき問題点）
入出力バッファ回路ブロック２の高さを５００μｍ１幅
を２００μｍの場合、テップ周辺の四隅の５００μｍＸ
５００μｍの領域には入出カバ。(Problem to be solved by the invention) When the height of the input/output buffer circuit block 2 is 500 μm and the width is 200 μm, the four corners around the tip are 500 μm
There is an input/output cover in the 500 μm area.
７７回路ブロック２を配置することは出来ない無駄な領
域となる。更に信号ビン増大の為に入出力バッファ回路
フロ、り２の幅を２００μｍから小さく例えば１６０μ
ｍとすると高さは７５０ｔｔｍとなる為、チップ四隅の
無駄な領域は７５０μｍＸ７５０μｍと増大することに
なる。又周辺パターンの領域は高密度化に伴い大きくな
って米ている。It becomes a wasted area in which the 77 circuit block 2 cannot be placed. Furthermore, in order to increase the number of signal bins, the width of the input/output buffer circuit 2 is reduced from 200 μm to 160 μm, for example.
Since the height is 750 ttm, the wasted area at the four corners of the chip increases to 750 μm×750 μm. Furthermore, the area of the peripheral pattern is becoming larger as the density increases.
マスタスライス方式の集積回路チップは用途に応じＤ
Ｉ Ｐ （ＤＵＡＬ ＩＮＬｉｎｅ Ｐａｃｋａｇ
ｅ ）の樹脂封止型（以下モールドと称す）ケースに
も搭載される場合が多（、ＤＩＰケースの電源端子はチ
、グの辺の中心付近の為電源パッドの利用が考えられる
パッド４′は使用出来なくなる０この場合コーナ部の入
出力バッファ回路２とリードとの結線時にワイヤ長が長
くなるし、テップを横切る長さが増大する為に、ワイヤ
同志の短絡あるいはワイヤとテップとの短絡の要因とな
シ、組立歩留を著しく低下してしまう問題点を有してい
る０又周辺パターンがテップの四隅にあるため第２．第
３の入出力バッファ回路ブロックをチップの四隅に設け
ても同様な結果となる０
本発明の目的はチップの四隅部に入出力バッファ回路ブ
ロックを設は多信号ピン化し、Ｌ）ＩＦ上モールドース
にも搭載可能な半導体集積回路装置を提供することにあ
る。Master slice type integrated circuit chips are available depending on the application.
I P (DUAL IN Line Packag)
It is often mounted on resin-sealed (hereinafter referred to as mold) cases such as e) (pad 4', which can be used as a power pad because the power terminal of the DIP case is near the center of the sides of In this case, the length of the wire becomes longer when connecting the input/output buffer circuit 2 at the corner with the lead, and the length that crosses the tip increases, resulting in a short-circuit between the wires or a short-circuit between the wire and the tip. The second and third input/output buffer circuit blocks were installed at the four corners of the chip because the zero or peripheral pattern, which has a problem that significantly reduces the assembly yield, is located at the four corners of the chip. The purpose of the present invention is to provide a semiconductor integrated circuit device in which input/output buffer circuit blocks are installed at the four corners of the chip and multi-signal pins can be mounted on the L) IF mold. be.
（発明の構成）
本発明によると半導体基板の主面上に論理回路を構成す
る素子をアレイ伏に配置した半導体集積回路において、
論理回路を構成する素子以外の製造上必要な鳩辺パター
ンの一部あるいは全部が入出カバ、ファ回路ブロック列
の内側に設けられたことを特徴とする半導体集積回路装
置が得られる。(Structure of the Invention) According to the present invention, in a semiconductor integrated circuit in which elements constituting a logic circuit are arranged face down in an array on the main surface of a semiconductor substrate,
A semiconductor integrated circuit device is obtained in which a part or all of the dovetail pattern necessary for manufacturing other than the elements constituting the logic circuit is provided inside the input/output cover and the F circuit block row.
（実施例） 次に本発明の実施例を図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第１図は本発明の第１の実施例を説明するためのレイア
クト図である０１はテップ外周、２は第１の入出力バッ
ファ回路ブロック、３は調理回路部、４は入出カバ、フ
ァ回路のバッドである。５゜６．７．８はチェ、クパタ
ーン、チェ、り素子。FIG. 1 is a layout diagram for explaining the first embodiment of the present invention. 01 is the outer circumference of the tip, 2 is the first input/output buffer circuit block, 3 is the cooking circuit section, 4 is the input/output cover, and the fa circuit. It's bad. 5゜6.7.8 is Che, Kupatan, Che, Rimoto.
商標品名等からなる周辺パターンが配置ちれる領域であ
る。This is an area where peripheral patterns consisting of trademark product names, etc. can be placed.
周辺パターンが入出力バラノア回路ブロック２の列の内
側に移動することによって、テップ四一部に第２の入出
カバ、ファ回路ブロック９．９′か計１２例配置された
例を示している。従って信号ビンは１２個増加し、より
多信号ビン化した半導体集積回路装置が得られたことに
なる。An example is shown in which a total of 12 second input/output covers and F circuit blocks 9 and 9' are arranged in a part of the step 4 by moving the peripheral pattern inside the row of input/output Balanor circuit blocks 2. Therefore, the number of signal bins increases by 12, and a semiconductor integrated circuit device with a larger number of signal bins is obtained.
周辺パターンは内部論理回路部の一部を減らしたことに
なるが、内部′ａｆＭ回路の周辺部はＤＡ処理によるマ
スタスライス方式の半導体集積回路においては調理回路
部か中心褪めとなり利用度が低い為、未配線が生じるこ
とは少くない。The peripheral pattern is a reduction of a part of the internal logic circuit, but in a master slice semiconductor integrated circuit using DA processing, the peripheral part of the internal 'afM circuit is not very useful because the center of the cooking circuit is faded. , it is not uncommon for unwired lines to occur.
第２．第３の入出力バッファ回路９．９′がテ、グの四
隅に設けられることにより、ケース搭載時のワイヤ長が
小さく、更にワイヤがテップを横切る長さが短くなる為
に、組立歩留がより向上す、る。人出カバ、７７回路２
の高さが増加すればする程第２．第３の入出カバ、ファ
回路９．９′の配置の効果が出てくることは明らかであ
る。Second. By providing the third input/output buffer circuits 9 and 9' at the four corners of the tips, the length of the wire when mounted on the case is small, and the length of the wire crossing the tips is also shortened, so the assembly yield is reduced. Improve even more. Crowd cover, 77 circuit 2
The higher the height of the second. It is clear that the effect of the arrangement of the third input/output cover and the amplifier circuit 9.9' is obtained.
第２図は本発明の第２の実施例を説明するためのレイア
クト図である。周辺パターンの一部５′。FIG. 2 is a layout diagram for explaining a second embodiment of the present invention. Part 5' of the peripheral pattern.
ｓ／ 、７／ 、ｓ／を入出力バッファ回路ブロック２
の列の内側に移動し、周辺パターンの一部５′。s/ , 7/ , s/ to input/output buffer circuit block 2
Move inside the column and part 5' of the peripheral pattern.
６’、７’、８’をテップの四隅に残した例を示してい
る。この場合でも同様の効果が得られる。An example is shown in which 6', 7', and 8' are left at the four corners of the tip. Similar effects can be obtained in this case as well.
以上説明してきたようにテラ１の四隅に設けられた周辺
パターン５．６．７．８の一部あるいは全部を入出カバ
ツク７回路ブロック列の内側に移動させ、チップ四隅に
第２．第３の入出力バッファ回路ブロック９．９′を配
置することによって。As explained above, part or all of the peripheral patterns 5, 6, 7, and 8 provided at the four corners of the Tera 1 are moved inside the input/output cover 7 circuit block rows, and the second pattern is placed at the four corners of the chip. By arranging a third input/output buffer circuit block 9.9'.
信号ビンの増大化が出来るとともに、組立歩留が向上す
る。The number of signal bins can be increased and the assembly yield can be improved.
（発明の効果）
本発明はチッグの四隅に入出力バッファ回路を追加でき
るため信号ビンの増加が得られ、更にＤＩＰモールドケ
ース等にｉａする場合にも組立歩留を低下しない効果が
ある０(Effects of the Invention) The present invention allows input/output buffer circuits to be added to the four corners of the chip, which increases the number of signal bins, and also has the effect of not reducing the assembly yield even when it is installed in a DIP mold case, etc.
第１図は本発明の第１の実施例を説明するためのレイア
ワト図、第２図は本発明の第２の実施例を説明するため
のレイアワト図、第３図は従来の例を説明するためのレ
イアワト図である。
ｌ・・・・・・チア１周辺、２・・・・・入出カバ、ノ
ア回路ブロック、３・・・・・・内部論理回路部、４．
４’・・・・・・パッド、５．６．７．８．５’、６’
、７’、８’、５’。FIG. 1 is a diagram for explaining a first embodiment of the present invention, FIG. 2 is a diagram for explaining a second embodiment of the present invention, and FIG. 3 is a diagram for explaining a conventional example. This is a layout diagram for. l... Cheer 1 peripheral, 2... Input/output cover, NOR circuit block, 3... Internal logic circuit section, 4.
4'...Pad, 5.6.7.8.5', 6'
, 7', 8', 5'.
Claims (2)
アレイ状に繰り返し配置した半導体集積回路において、
論理回路を構成する素子以外の製造上必要な周辺パター
ンの一部あるいは全部が入出力バッファ回路ブロック列
の内側に設けられたことを特徴とする半導体集積回路装
置。(1) In a semiconductor integrated circuit in which elements constituting a logic circuit are repeatedly arranged in an array on the main surface of a semiconductor substrate,
1. A semiconductor integrated circuit device, wherein part or all of a peripheral pattern necessary for manufacturing other than elements constituting a logic circuit is provided inside an input/output buffer circuit block array.
ッファ回路ブロックを併せ持つことを特徴とする特許請
求の範囲第（１）項記載の半導体集積回路装置。(2) The semiconductor integrated circuit device according to claim (1), further comprising an input/output buffer circuit block different from the input buffer circuit block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60040483A JPS61199647A (en) | 1985-03-01 | 1985-03-01 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60040483A JPS61199647A (en) | 1985-03-01 | 1985-03-01 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61199647A true JPS61199647A (en) | 1986-09-04 |
Family
ID=12581848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60040483A Pending JPS61199647A (en) | 1985-03-01 | 1985-03-01 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61199647A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS644055A (en) * | 1987-06-25 | 1989-01-09 | Nec Corp | Construction of semiconductor integrated circuit |
| US4941863A (en) * | 1988-03-28 | 1990-07-17 | Kubota Ltd. | Stepless speed change mechanism in belt transmission device |
| US5156983A (en) * | 1989-10-26 | 1992-10-20 | Digtial Equipment Corporation | Method of manufacturing tape automated bonding semiconductor package |
| JP2010187008A (en) * | 2010-04-12 | 2010-08-26 | Fujitsu Semiconductor Ltd | Semiconductor integrated circuit and wiring layout method of semiconductor integrated circuit |
-
1985
- 1985-03-01 JP JP60040483A patent/JPS61199647A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS644055A (en) * | 1987-06-25 | 1989-01-09 | Nec Corp | Construction of semiconductor integrated circuit |
| US4941863A (en) * | 1988-03-28 | 1990-07-17 | Kubota Ltd. | Stepless speed change mechanism in belt transmission device |
| US5156983A (en) * | 1989-10-26 | 1992-10-20 | Digtial Equipment Corporation | Method of manufacturing tape automated bonding semiconductor package |
| JP2010187008A (en) * | 2010-04-12 | 2010-08-26 | Fujitsu Semiconductor Ltd | Semiconductor integrated circuit and wiring layout method of semiconductor integrated circuit |
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