JP3204385B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art There is known a semiconductor device in which a semiconductor chip is provided with an auxiliary function such as a complementary function such as a redundancy function and a test function for performing a performance test.

Japanese Patent Application Laid-Open No. Hei 6-13447 discloses a semiconductor device in which a test circuit for performing a test function is provided in a semiconductor chip. FIG. 3 is a diagram described in the above publication, in which reference numerals 101 to 109 denote semiconductor chips, 110 denotes an auxiliary circuit for measuring characteristics of the semiconductor chip, 111 denotes a signal line, 112 denotes a power line, and 1 denotes a power line.
Reference numeral 13 denotes a GND line, and 114 denotes a scribe line.

As shown in FIG. 1, an auxiliary circuit 110 for measuring characteristics of a semiconductor chip 102 includes a scribe line 1.
It is arranged on the adjacent semiconductor chip 101 via. Similarly, an auxiliary circuit for the chip 103 is arranged on the chip 102, an auxiliary circuit for the chip 105 is arranged on the chip 104, an auxiliary circuit for the chip 106 is arranged on the chip 105, and so on. By doing so, the auxiliary circuit can be reliably disconnected at the time of scribing.

However, in this technique, the auxiliary circuit 110 for each semiconductor chip is always required at the time of manufacturing, and the auxiliary circuit cannot be eliminated.

An example of a semiconductor device in which an auxiliary circuit for performing a redundancy function is provided in a semiconductor chip will be described with reference to FIG. In FIG. 4A, a semiconductor memory device 1 as an example of a semiconductor device has a portion in which an arbitrary number of memory cell arrays and the like in an ellipse are arranged in a matrix and a redundancy control for selecting and operating a redundancy portion in the portion. A circuit 9 is provided in a peripheral portion.

More specifically, as shown in FIG. 4B, which is an enlarged view of FIG. 4A, a memory cell array 1 in which an arbitrary number of memories are arranged in a matrix, and the direction of each row and column thereof , A column redundancy memory cell array 5 and a row redundancy memory cell array 6, and a column redundancy memory cell array 5 and a row redundancy in the row and column directions of the memory cell array in order to select a desired memory cell array. A column decoder 3 and a row decoder 2 arranged in contact with the memory cell array 6 for use, a column redundancy decoder 7 arranged in contact with the column decoder in order to select the memory cell array 5 for column redundancy, and a row redundancy Memory cell array And a sense amplifier 4 arranged between and in contact with a row redundancy decoder 8 for selecting and amplifying memory cell data between a row redundancy memory cell array and a row redundancy decoder 8 for selecting and amplifying memory cell data. , Is provided.

As described above, the memory cells 5 and 6 for redundancy are arranged adjacent to the memory cell array 1, and the decoders 7 and 8 for selecting them are also row decoders 3 for selecting the memory cells. And the column decoder 2.

[0009]

The first problem is that the complementary function part is adjacent to or scattered from the original function part. In addition, since a complementary function is always required at the time of manufacture, there is also a problem that even if it becomes unnecessary, it cannot be deleted. The second problem is that, for example, the redundancy function of the semiconductor memory device has the same configuration at an arbitrary position in the chip, and therefore, the scale of the complementary function increases in proportion to the original storage capacity. Is to put it. As a result, more complementary functions were prepared than necessary for improving the yield. A third problem is that a large number of steps are required for shrink chip development.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of reducing a chip size by making an auxiliary circuit separable. Another object of the present invention is to provide a semiconductor device capable of reducing the chip size by reducing the number of redundancy circuits.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device in which a semiconductor integrated circuit comprising an electronic circuit having a specific function is formed in a semiconductor chip. auxiliary circuit for performing an auxiliary function such as completion and test function is provided, the half
The conductor integrated circuit is a semiconductor memory cell integrated circuit;
The auxiliary circuit is used when manufacturing the semiconductor memory cell integrated circuit.
Circuit for redundancy to compensate for defective functions in
The auxiliary circuit is arranged on a semiconductor chip in a peripheral portion of a region where the semiconductor integrated circuit is formed, and is arranged in a region that can be cut through a scribe line. In the semiconductor device according to the second aspect, a semiconductor chip is provided.
Semiconductors consisting of electronic circuits with specific functions
A semiconductor device on which an integrated circuit is formed;
Auxiliary functions such as complementary functions and test functions for semiconductor integrated circuits
Auxiliary circuit is provided to perform, the semiconductor integrated circuit, a semiconductor memory cell integrated circuit, the auxiliary circuit, met redundancy circuit compensates a defective function in the manufacturing of the semi <br/> conductor memory cell integrated circuit Thus, the redundancy circuit is provided at a ratio of one to a plurality of semiconductor memory cells.
And the auxiliary circuit is provided with the semiconductor integrated circuit.
On the semiconductor chip in the periphery of the
It is characterized in that it is arranged in a region that can be cut through the eve line .

According to the first aspect of the present invention, the auxiliary circuit is arranged in a peripheral portion of a region where the semiconductor integrated circuit is formed. That is, in the present invention, a portion provided with an auxiliary circuit that performs an auxiliary function such as a complementary function or a test function (hereinafter, referred to as an “auxiliary chip”) is replaced by a portion (hereinafter, referred to as “an auxiliary chip”) in which only the original functional portion is left. Chips). As a result, the auxiliary function can be arbitrarily divided, and the chip size can be reduced without changing the performance. In other words, the auxiliary function parts scattered in the chip are centrally arranged in the auxiliary chip, and are connected to maintain the same function as the conventional one. In addition, in order to enable separation, a scribe line is preferably provided between the present chip and the auxiliary chip, and the scribe line is designed in a separate data layer as in the case of the metal option. In addition, when the auxiliary chip is deleted, it becomes possible by preparing the exposure range adjusting function of the stepper or preparing a mask of only this chip. According to the second aspect of the present invention, since the auxiliary circuit is a redundancy circuit, the yield is improved, and it is easy to eliminate the redundancy circuit when the redundancy function is no longer required. According to the third aspect of the present invention, the number of the redundancy circuits can be reduced by providing one redundancy circuit for a plurality of semiconductor memory cells. Thus, the area ratio occupied by the redundancy circuit can be reduced, and the number of effective chips can be increased. That is, in the related art, a redundancy circuit (redundancy memory and its control circuit, etc.) is provided at one ratio for one semiconductor memory cell, so that more redundancy circuits than necessary are formed. As a result, the area occupied by the redundancy circuit was relatively large. On the other hand, in the present invention, the above effects can be obtained by setting the number of redundancy circuits to one for a plurality of semiconductor memory cells.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of the semiconductor device of the present invention, and shows a semiconductor memory device having a redundancy function as an example of the semiconductor device.

In FIG. 1A, a semiconductor chip is a semiconductor chip (semiconductor memory cell integrated circuit) in which an arbitrary number of memory cell arrays 1 (semiconductor memory cells) and the like are arranged in rows and columns.
A and an auxiliary chip (redundancy circuit) B in contact with the present chip.

The auxiliary chip B includes a row redundancy memory cell array 11, a row redundancy decoder and a row redundancy control circuit 10 disposed in contact therewith, and a column redundancy memory cell array 13 and is disposed in contact therewith. Decoder for column redundancy and column redundancy control circuit 1
And 2.

In this case, the row redundancy memory cell array 11 and the row redundancy decoder and row redundancy control circuit 10 arranged in contact with the memory cell array 11 are composed of a plurality of columns (six in the illustrated example). 1.) A row redundancy circuit is provided for the memory cell array 1 at a ratio of one. Similarly, the column redundancy memory cell array 13 and the column redundancy decoder and the column redundancy control circuit 12 arranged in contact therewith are provided at a ratio of one to a plurality of memory cell arrays 1 forming one row. A column redundancy circuit.

FIG. 1 is an enlarged view of FIG.
As shown in (b), this chip A has a memory cell array 1 in which an arbitrary number of memory cells are arranged in a matrix, and a column decoder 3 and a row decoder arranged on both sides in contact with the respective rows and columns. 2, sense amplifier 4,
Is provided.

The relationship between the present chip A and the auxiliary chip B will be described with reference to FIG. As shown in FIG. 2, a scribe line 18 is arranged between the present chip A and the auxiliary chip B. Across the scribe line 18, a read / write bus 19 and a line 17 such as a redundancy selection signal line, a control signal line, a power supply line, and a GND line connect the functional units of the chips A and B to each other. I have. As described above, the redundancy memory cell array 14 (the row redundancy memory cell array 11 or the column redundancy memory cell array 13) and the redundancy decoder 15 are arranged in the auxiliary chip B. A redundancy control circuit 16 is arranged adjacent to the control circuit.

In FIG. 1B, a memory cell array 1, a row decoder 2, a column decoder 3, and a sense amplifier 4 are parts for realizing the original functions of the semiconductor memory device. On the other hand, the column redundancy memory cell array 13, the row redundancy memory cell array 11, the column redundancy decoder and the column redundancy control circuit 12, the row redundancy decoder and the row redundancy control circuit 10 shown in FIG. Exist for the purpose of assisting. As can be seen, the original functional part and the auxiliary functional part are clearly separated from each other, and can be cut at the scribe line 18 as shown in FIG.

Here, the chip A and the auxiliary chip B are connected by an upper metal layer wiring in order to maintain the same function as the conventional method. This includes a read / write bus line, a signal line group for redundancy, and the like. At this time, the intersection 20 with the scribe line 18 is designed in another data layer in advance so that the auxiliary chip B
When the production is changed so as to be cut by the scribe line of this part, the metal layer of the scribe part can be easily removed by preparing a metal option mask that does not add the intersection part 20, so that the It is possible to prevent a decrease in yield due to dust.

In this way, if the auxiliary chip B can be arbitrarily cut, the production technology is improved and the yield is increased, so that the production without the auxiliary function becomes more advantageous. It can be easily deleted when it is no longer needed. This can be achieved by adjusting the exposure range with the shutter of the stepper, or preparing a mask with a different imposition, and producing only the present chip A.

[Calculation Example] Hereinafter, a conventional method and a method according to the present invention will be compared with respect to a semiconductor memory device having a redundancy function. The calculation conditions are assuming an 8-inch wafer, assuming a redundancy remedy rate of 95%, and taking no consideration other than the perfect non-defective product rate and the redundancy remedy rate (not considering test costs, etc.).
Further, in the present invention, no redundancy circuit is provided.

Example 1 In the case where the perfect non-defective rate is 70% In the conventional method, if the chip size is 4 mm × 8 mm, the number of effective chips is 850 / chip. The number of perfect non-defective products is 850 × 0.7 = 595. The number of redundancy relief products is (850-595) x 0.95 = 242
Individual. The total is 595 + 242 = 837.
In the present invention, when the chip size is 3.7 mm × 8 mm, the number of effective chips is 924 / sheet. The number of perfect non-defective products is 924 × 0.7 = 646. Therefore,
837> 646, and the conventional method is more common.

[Example 2] When the perfect non-defective rate is 92% In the conventional method, if the chip size is 4 mm × 8 mm, the number of effective chips is 850 / sheet. The number of perfect non-defective products is 850 × 0.92 = 782. The number of redundancy relief products is (850-782) x 0.95 = 64
Individual. The total is 782 + 64 = 846. In the present invention, when the chip size is 3.7 mm × 8 mm, the number of effective chips is 924 / sheet. The number of perfect non-defective products is 924 × 0.92 = 850. Therefore, 846 <850, and the present invention is more common.

In the above example, the rate at which a perfect non-defective product that does not require a supplementary function can be produced (hereinafter, referred to as "perfect non-defective product rate")
Is 70%, the conventional method is superior in the number of non-defective products. However, when the perfect non-defective ratio is as high as 92%, the method of the present invention is superior without providing a redundancy circuit. In this way, the chip size can be reduced by removing the auxiliary chip when the complete non-defective product rate is improved and the complement function is no longer required. Thereby, productivity can be improved.

[0027]

According to the semiconductor device of the present invention, the following effects can be obtained. The first effect is that when the auxiliary functions such as the test function and the complementary function become unnecessary, such auxiliary functions can be easily deleted. The reason for this is that the auxiliary functions such as the test function and the complementary function can be separated by independently arranging them. A second effect is that independent design of auxiliary functions such as a test function and a complementary function can be performed independently of the original functional part. The reason is that the auxiliary functions such as the test function and the complementary function can be separated by independently arranging them. A third effect is that design man-hours can be reduced. The reason is that the number of development steps can be reduced by easily reducing the chip size of a product whose performance has been confirmed in advance without changing the quality.

[Brief description of the drawings]

FIG. 1A is a schematic configuration diagram illustrating an embodiment of a semiconductor device according to the present invention, and FIG. 1B is an enlarged view thereof.

FIG. 2 is a schematic configuration diagram showing an enlarged auxiliary function part in the semiconductor device of FIG. 1;

FIG. 3 is a diagram showing a configuration example of a conventional semiconductor device having a test function as an auxiliary function.

FIG. 4 is a diagram showing a configuration example of a conventional semiconductor device having a redundancy function as an auxiliary function.

[Explanation of symbols]

A chip (semiconductor memory cell integrated circuit) B auxiliary chip (redundancy circuit) 1 memory cell array (semiconductor memory cell) 2 row decoder 3 column decoder 4 sense amplifier 10 decoder for row redundancy and row redundancy control circuit 11 memory for row redundancy Cell array 12 Decoder for column redundancy and column redundancy control circuit 13 Memory cell array for column redundancy 18 Scribe line

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/10 471 H01L 27/04 A (56) References JP-A-6-69297 (JP, A) JP-A-4-305960 (JP, A) JP-A-1-215040 (JP, A) JP-A-61-104640 (JP, A) JP-A-7-94588 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H01L 27/04 G11C 29/00 603 G11C 29/00 671 H01L 21/82 H01L 21/822 H01L 27/10 471

Claims (2)

(57) [Claims] In a semiconductor device in which a semiconductor integrated circuit including an electronic circuit having a specific function is formed in a semiconductor chip, an auxiliary circuit for performing an auxiliary function such as a complementary function or a test function of the semiconductor integrated circuit is provided. Wherein the semiconductor integrated circuit is a semiconductor memory cell integrated circuit.
The auxiliary circuit is a semiconductor memory cell integrated circuit.
A circuit for redundancy that compensates for defective functions during manufacturing
The semiconductor device is characterized in that the auxiliary circuit is arranged in a region that can be cut through a scribe line on a semiconductor chip in a peripheral portion of a region where the semiconductor integrated circuit is formed. 2. A semiconductor chip having a specific function.
Semiconductor integrated circuit formed of electronic circuit
In the body unit, auxiliary machines completion and testing functions of the semiconductor integrated circuit
Auxiliary circuit is provided for performing ability, the semiconductor integrated circuit, a semiconductor memory cell integrated circuit, the auxiliary circuit, with redundancy circuit to compensate for defective function in the manufacturing of the semiconductor memory cell integrated circuit
The redundancy circuit is provided at a ratio of one to a plurality of semiconductor memory cells , and the auxiliary circuit is provided in a region where the semiconductor integrated circuit is formed.
On the peripheral semiconductor chip via the scribe line
A semiconductor device, wherein the semiconductor device is arranged in an area that can be cut by cutting .