JP3866322B2 - Semiconductor integrated circuit mounted wafer and manufacturing method of semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit mounted wafer and a method for manufacturing a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit mounted wafer having a redundant circuit and a method for manufacturing a semiconductor integrated circuit device.
[0002]
[Prior art]
Conventionally, in order to manufacture a large-scale integrated circuit (LSI), a plurality of usually rectangular chips are formed on a circular Si wafer by using a lithography technique. At that time, an extra portion where a semiconductor chip cannot be formed is generated in the peripheral portion of the wafer. On the other hand, LSIs, especially semiconductor memories, are actually produced at the same time as defective chips even when they are mass-produced at the factory. For this reason, reducing the number of defective chips and increasing the yield are important issues for LSI manufacturing technology.
[0003]
At present, especially in semiconductor memories, in order to increase the yield, a redundancy circuit (redundant circuit) that replaces the defective circuit in advance is created in the integrated circuit, and when a defect occurs, the redundancy circuit is used. In general, defective chips are replaced with two-chip chips to increase the yield.
[0004]
FIG. 6A is a plan view of a semiconductor wafer on which a plurality of semiconductor chips are formed, and FIG. 6B is a plan view of the semiconductor chips. 1 is a semiconductor wafer, 20 is a semiconductor chip, 6 is a functional circuit unit, and 7 is a redundancy circuit unit. In order to increase the yield, each chip 20 has a redundancy circuit 7 of a certain scale. Each chip 20 is inspected by a tester, and when a defective part can be relieved by the redundancy circuit 7, it is replaced and relieved to make it a non-defective product and increase the yield. However, in reality, the number of defective portions is around the scale of the prepared redundancy circuit 7, and there is a semiconductor chip that becomes a defective product.
[0005]
If the size of the redundancy circuit unit 7 in the chip is increased, the probability that the defective chip can be relieved because the size of the redundancy circuit unit 7 is small so far increases, and the yield can be increased. However, when the size of the redundancy circuit unit 7 is increased, the area of each chip 20 is increased, and the number of chips 20 that can be formed on the wafer 1 is decreased. Therefore, the manufacturing cost per chip is increased. is there. For this reason, the size of the redundancy circuit is determined so as to minimize the manufacturing cost.
[0006]
[Problems to be solved by the invention]
As described above, in the manufacture of the conventional semiconductor integrated circuit device, if the size of the redundancy circuit is increased in order to increase the yield, the chip area is increased and the number of chips per wafer is reduced, which increases the manufacturing cost. There was a problem.
[0007]
An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device that can increase the yield without reducing the number of chips per wafer and can reduce the manufacturing cost.
[0008]
[Means for Solving the Problems]
(Constitution)
(1) In a semiconductor integrated circuit mounted wafer in which a plurality of semiconductor integrated circuits including redundant circuits are arranged in each chip area on the semiconductor wafer, the redundant circuit area of the chip area located in the peripheral part of the wafer among the chip areas The redundant circuit area of the chip region located in the center of the wafer is made larger.
[0009]
(2) The semiconductor wafer is divided into a plurality of chip areas, and a semiconductor integrated circuit including a redundant circuit is formed in each chip area, and then the semiconductor wafer is cut along the chip area to thereby form a plurality of semiconductor integrated circuit chips. In the method of manufacturing a semiconductor integrated circuit device, the size of the redundant circuit in the chip region located in the wafer peripheral portion of the chip region on the wafer is larger than the size of the redundant circuit in the chip region located in the wafer central portion. Was also bigger.
[0010]
(3) The semiconductor wafer is divided into a plurality of chip regions, and a semiconductor integrated circuit including a redundant circuit is formed in each chip region. Then, the semiconductor wafer is cut along the chip region, and a plurality of semiconductor integrated circuit chips are formed. In the method of manufacturing a semiconductor integrated circuit device, an additional redundant circuit is provided together with the original redundant circuit in a chip region located in the peripheral portion of the wafer among the chip regions on the wafer.
[0011]
(4) Of the chip regions on the wafer, the area of the chip region located at the wafer peripheral portion is made larger than the area of the chip region located at the wafer central portion.
(5) chip regions located at the wafer periphery, and includes a region to be the remainder which is not subjected to chip formation upon arranging a plurality rectangular chip having the same shape on a circular wafer.
[0012]
(6) A silicon single crystal substrate, an SOI substrate, or a compound semiconductor substrate was used as the semiconductor wafer.
(7) A mask used when forming a pattern in the chip region has a pattern of a semiconductor integrated circuit and a pattern of an additional redundant circuit provided adjacent to each side of the pattern.
[0013]
(8) A pattern is formed in the chip region of the wafer by step & repeat while appropriately hiding the pattern of the additional redundant circuit described in (6).
(9) The same pattern is formed in the chip region, and the pattern portion of the semiconductor integrated circuit and the pattern portion of the redundant circuit are appropriately hidden using the mask described in (6) in the chip region around the wafer. Form.
[0014]
(10) The chip region is not arranged in a fixed direction, and an additional redundant circuit is formed in the short side direction of the chip region.
(Function)
As a result of investigation by the inventors of the present invention, it has been found that it is caused by dust mixed during the manufacturing process, variation in the thickness of the deposited film, variation in etching rate, and the like. Further, it has been found that this cause of failure occurs more conspicuously in the peripheral portion of the wafer.
[0015]
Therefore, in the case of having redundancy circuits of the same scale, the number of redundancy circuits in the peripheral portion of the wafer is insufficient, and the probability that a defective product is produced is greater than that in the center portion. For example, a yield of almost 100% can be obtained with a chip at the center of the wafer, but about 70% with a chip in the peripheral portion.
[0016]
Therefore, in the present invention, the redundancy circuit of the chip in the peripheral part of the wafer is made larger than the redundancy circuit of the chip in the central part of the wafer, thereby relieving the chip that has been defective due to the lack of the redundancy circuit in the past. As a result, the yield at the peripheral portion of the wafer can be increased and the yield of the entire wafer can be increased.
[0017]
In addition, when a plurality of chips are arrayed on the wafer, there are areas in the wafer where chips cannot be formed. Therefore, by forming an additional redundant circuit for peripheral chips in an area where chips cannot be formed, a reduction in the number of chips that can be taken from one wafer can be prevented.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1A is a plan view of a semiconductor wafer on which a plurality of semiconductor chips according to the first embodiment of the present invention are formed. Semiconductor chips 2 and 3 are arranged on the surface of the wafer 1. Although not shown, the semiconductor chip 2 at the center of the wafer 1 includes a redundancy circuit (redundancy circuit). The semiconductor chip 3 arranged in the peripheral part of the wafer 1 includes a circuit part 4 and an additional redundancy circuit part 5 which are the same as the semiconductor chip 2 in the central part. Here, the chips 2 and 3 substantially indicate chip areas, and are finally cut out from the wafer to become chips.
[0019]
The present invention includes a method of manufacturing a semiconductor integrated circuit device such as the chip itself cut out as described above or an IC or LSI on which the chip is mounted. Furthermore, the present invention includes a wafer on which a semiconductor integrated circuit before being cut out as a chip is mounted.
[0020]
The wafer 1 has a region where a semiconductor chip cannot be formed because the chip pattern protrudes outside the wafer when the chip pattern is formed (hereinafter, this region is referred to as a blank region). The additional redundancy circuit section 5 of the semiconductor chip 3 is disposed in a blank area on the wafer 1. The semiconductor wafer 1 is made of a silicon single crystal, an SOI substrate, a compound semiconductor substrate, or the like.
[0021]
Hereinafter, the configuration of the semiconductor chips 2 and 3 will be described more specifically. As shown in FIG. 1B, the central semiconductor chip 2 includes a functional circuit unit 6 and a redundancy circuit unit 7 for realizing a certain function. Further, as shown in FIG. 1C, the peripheral semiconductor chip 3 has an additional redundancy circuit section 5 in addition to the same functional circuit section 6 and redundancy circuit section 7 of the semiconductor chip in the center section. .
[0022]
For example, when the functional circuit unit 6 of the semiconductor chip is a DRAM, spares corresponding to rows and columns are formed in the redundancy circuits 5 and 7. If there is a defect in a row, column, or memory cell in the memory array, it is replaced with a column or row in the redundancy circuits 5 and 7 and used as a good product.
[0023]
Next, a manufacturing method will be described. However, since formation of a thin film, etching, and the like are not different from a process of manufacturing a normal semiconductor chip, only a lithography process will be described. In the lithography process, the mask shown in FIG. 2 is used. A semiconductor integrated circuit pattern portion 9 including a normal redundancy circuit is formed in the central portion of the mask 8. Adjacent to the pattern 9, additional redundancy circuit pattern portions 10a, 10b, 10c, and 10d are formed.
[0024]
Using the mask 8, the pattern of each chip is sequentially formed by step & repeat. Here, when forming the pattern of the chip 2 in the central part, the pattern is formed while hiding all the patterns 10 of the mask 8, and when forming the pattern of the chip 3 in the peripheral part, the pattern of the mask is formed. The patterns 8 and 10a or 10b are formed at the same time while hiding other than 10a or 10b. As a result, a semiconductor chip pattern is formed on the wafer 1 as shown in FIG.
[0025]
Further, a manufacturing method as described below may be used. A circuit pattern having a redundancy circuit of the same scale is formed on the periphery and center of the wafer. Thereafter, an additional redundancy circuit part pattern is formed in the blank area of the wafer. When forming the additional redundancy circuit pattern, the pattern can be formed by using the mask of FIG. At this time, the pattern does not have to be formed in the central portion of the mask 8.
[0026]
Further, a layout different from FIG. 1 is shown. In FIG. 1, there are some chips in which the additional redundancy circuit 5 is not formed on the long side of the chip in the peripheral semiconductor chip 3, and no additional redundancy circuit is formed. Therefore, as shown in FIG. 3, an additional redundancy circuit unit 5 may be formed on the short side of the semiconductor chip 11 at the periphery of the wafer. Here, in order to form the pattern of the additional redundancy circuit 5 on the semiconductor chip 11 of FIG. 3, the upper pattern 10c or the lower pattern 10d of the mask of FIG.
[0027]
Further, a method different from the above manufacturing method will be described. After a pattern of a semiconductor chip having a normal-scale redundancy circuit is formed in the central portion of the wafer, a semiconductor chip having a redundancy circuit having a larger scale than that of the previous semiconductor integrated circuit is formed in a region including a blank region in the peripheral portion of the wafer. A pattern may be formed. In this manufacturing method, after forming a semiconductor chip having a large-scale redundancy circuit, a semiconductor chip having a small-scale redundancy circuit may be formed in the center of the wafer.
[0028]
In the case of this manufacturing method, instead of forming the additional redundancy circuit section in the blank area, as shown in FIG. 4, the entire chip including the additional redundancy circuit section can be formed in the area including the blank area.
[0029]
After the semiconductor chip is formed on the wafer, a test is performed to find a defective portion. If the defective portion can be replaced with a redundancy circuit, the defective portion is replaced with a redundancy circuit. Conventionally, a semiconductor chip that has been defective due to lack of redundancy circuits in peripheral chips also increases the probability that it can be remedied in this embodiment, so the overall yield can be increased, thus reducing the manufacturing cost. Can be lowered.
[0030]
Furthermore, the manufacturing information 6a and 6b of each chip may be marked in the area of each semiconductor chip 2 and 3. This manufacturing information includes information such as from which position on which wafer a chip is cut out. Therefore, if there is a correlation of the present invention between the size of the redundant circuit of each chip and the positional relationship obtained from the manufacturing information, it is included in the present invention.
[0031]
(Second Embodiment)
FIG. 5A is a plan view of a semiconductor wafer on which a plurality of semiconductor chips according to the second embodiment of the present invention are formed, and FIG. 5B is a plan view of the semiconductor chips. Here, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. The feature of this embodiment is that the semiconductor chips 2 and 3 are not arranged in a certain direction. Further, an additional redundancy circuit unit 5 is formed in the short side direction of the semiconductor chip 3 in the peripheral part.
[0032]
In this case, the lateral widths of the center chip 2 and the peripheral chip 3 are constant. Then, for example, the semiconductor chip 3 can be formed without changing the position of the bonding pad. Therefore, processes such as inspection by a tester, subsequent chip cutting, storage in a package, and wire bonding can be performed relatively easily as compared to the previous embodiment.
Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.
[0033]
【The invention's effect】
A yield circuit can be improved without reducing the number of chips per wafer by forming a redundant circuit having a larger scale than the chip at the center of the wafer by using an area where chips cannot be formed in the peripheral chip of the semiconductor wafer. be able to.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor wafer and a single chip according to a first embodiment.
FIG. 2 is a plan view showing a mask when a semiconductor chip is formed in the first embodiment.
FIG. 3 is a plan view (1) showing another example of the layout in the first embodiment.
FIG. 4 is a plan view (2) showing another example of the layout in the first embodiment.
FIG. 5 is a plan view showing a semiconductor wafer and a single chip according to a second embodiment.
FIG. 6 is a plan view showing a wafer on which a plurality of conventional semiconductor chips are formed and a single chip.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer 2 ... Semiconductor chip 3 ... Semiconductor chip 4 ... Circuit part 5 ... Additional redundancy circuit part 6 ... Functional circuit part 7 ... Redundancy circuit part 8 ... Mask 9 ... Semiconductor integrated circuit mask 10 ... Additional redundancy circuit mask 11 ... Semiconductor Chip

Claims (6)

  In a semiconductor integrated circuit mounting wafer in which a plurality of semiconductor integrated circuits including redundant circuits are arranged in each chip region on a semiconductor wafer, the redundant circuit area of the chip region located in the peripheral portion of the chip region A semiconductor integrated circuit mounted wafer characterized by being made larger than a redundant circuit area of a chip region located in a part. A semiconductor wafer is divided into a plurality of chip areas, and a semiconductor integrated circuit including a redundant circuit is formed in each chip area. Then, the semiconductor wafer is cut along the chip area to create a plurality of semiconductor integrated circuit chips. In a method for manufacturing a semiconductor integrated circuit device,
Of the chip regions on the wafer, the size of the redundant circuit in the chip region located in the peripheral portion of the wafer is made larger than the size of the redundant circuit in the chip region located in the central portion of the wafer. Manufacturing method. A semiconductor wafer is divided into a plurality of chip areas, and a semiconductor integrated circuit including a redundant circuit is formed in each chip area. Then, the semiconductor wafer is cut along the chip area to create a plurality of semiconductor integrated circuit chips. In a method for manufacturing a semiconductor integrated circuit device,
A manufacturing method of a semiconductor integrated circuit device, wherein an additional redundant circuit is provided together with an original redundant circuit in a chip region located in a peripheral portion of the wafer among chip regions on the wafer. Among the chip areas on the wafer, a semiconductor integrated circuit according to claim 2 or 3, characterized in that is larger than the area of the chip regions located the area of the chip regions located wafer peripheral portion in the wafer center Device manufacturing method. Chip regions located at the wafer periphery, claim 2, characterized in that it includes an area to be the remainder which is not subjected to chip formation upon arranging a plurality rectangular chip having the same shape on a circular wafer, or 4. A method of manufacturing a semiconductor integrated circuit device according to 3 . Examples semiconductor wafer, a silicon single crystal substrate, a method of manufacturing a semiconductor integrated circuit device according to claim 2 or 3, characterized by using an SOI substrate or a compound semiconductor substrate.

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