JPH06295997A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the short circuit of bit lines due to particles generated during the wiring process of a semiconductor storage device, and improve manufactureing yield. CONSTITUTION:In a semiconductor storage device which has a memory cell in each crossing position of a word line and a bit line, and individually reads stored data by selecting the word line and the bit line, first bit lines 4a and second bit lines 4B adjacently arranged to be in parallel with the first bit lines are formed by using different wiring layers. By forming the bit lines which are adjacently arranged in parallel, by using different wiring layers, the wiring width of bit lines formed in the same wiring layer can be increased without enlarging chip area, and the short circuit of bit lines due to particles generated during a wiring process can be remarkably reduced. Reliability also is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line arranging and wiring technique in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 4 is a plan view of a conventional semiconductor memory device. A is an N-channel type MOSFE which becomes a memory cell
T, 1 is a GND diffusion layer, 2a and 2b are word lines formed of polycrystalline silicon, 3a to 3d are drain electrodes of memory cells, 4a to 4d are bit lines formed of the first layer metal, Reference numerals 5a to 5d are contacts between the diffusion layer and the first metal layer. The reading of the memory data is performed by selecting the word line and the bit line. For example, when the word line 2a and the bit line 4a are selected, the storage data of the memory cell A is read.

FIG. 3 is a sectional view taken along line XY shown in FIG. 3a to 3d are drain electrodes of the memory cell, 4a
4d is a bit line formed of the first layer metal, 6 is a substrate, 7 is an insulating film formed between the bit lines 4a to 4d and the substrate 6, and 8 is formed on the bit lines 4a to 4d. The insulating film, L1, indicates the wiring interval of the bit lines. As shown in FIG. 3, the bit lines 4a to 4d formed on the insulating film 7 were formed of the same wiring layer.

[0004]

However, as the manufacturing process has been miniaturized in recent years, the bit line interval L1 has become so narrow that the influence of particles generated in the wiring process cannot be ignored. Then, due to the particles, a short of the bit line occurs, which causes a problem of malfunction of the semiconductor memory device.

Therefore, an object of the present invention is to form bit lines arranged adjacent to each other in parallel in different wiring layers so that the wiring intervals of the bit lines formed in the same wiring layer can be widened and the particles can be formed. This is to prevent the short of the bit line due to.

[0006]

A semiconductor memory device according to the present invention has a memory cell at each position where a word line and a bit line intersect, and a memory is selected by selecting the word line and the bit line. In a semiconductor memory device for individually reading data, a second bit line arranged in parallel with and adjacent to the first bit line is formed by wiring layers different from each other.

[0007]

According to the above-mentioned structure of the present invention, the bit lines formed in the same wiring layer are widened by forming the bit lines arranged in parallel in the adjacent wiring layers different from each other. -It is intended to reduce the short of the bit line due to the tickle and improve the yield of the semiconductor memory device.

[0008]

FIG. 2 is a plan view of a semiconductor memory device according to the present invention. A is an N-channel type MOSFE which becomes a memory cell
T, 1 is a GND diffusion layer, 2a and 2b are word lines formed of polycrystalline silicon, 3a to 3d are drain electrodes of memory cells, 4a and 4c are bit lines formed of a first layer metal, 4B and 4D are bit lines formed of the second layer metal, 5a and 5c are contacts between the diffusion layer and the first layer metal, and 5B and 5D are contacts between the diffusion layer and the second layer metal. The reading of the memory data is performed by selecting the word line and the bit line. For example, when the word line 2a and the bit line 4a are selected, the storage data of the memory cell A is read.

FIG. 1 is a sectional view taken along line XY shown in FIG. 3a to 3d are drain electrodes of memory cells, 4
a and 4c are bit lines formed of the first metal layer, 4
B and 4D are bit lines formed of the second metal layer, 6 is a substrate, 7 is an insulating film formed between the bit lines 4a and 4c and the substrate 6, and 8 is bit lines 4a and 4c and bit lines. 4B,
4D, an insulating film formed between the bit lines 4B and 4D
An insulating film formed on D, L1 is a wiring interval between the bit lines 4a and 4c, and L2 is a bit line 4B and a bit line 4D.
Shows the wiring interval. Bit line 4 formed on insulating film 7
a is a bit line 4B formed of the first-layer metal and arranged adjacent to and parallel to the bit line 4a on the insulating film 8.
Is formed of a second-layer metal, is arranged in parallel adjacent to the bit line 4B and is formed on the insulating film 7, is formed of a first-layer metal, and is adjacent to the bit line 4c in parallel. The bit line 4D formed on the insulating film 8 is 2
It is formed of the metal of the second layer.

Bit line 4a formed of the first metal layer
The wiring distance L1 between the bit line 4c and the bit line 4c is the sum of the wiring distance between the bit line 4a and the bit line 4B, the wiring width of the bit line 4B, and the wiring distance between the bit line 4B and the bit line 4c. The wiring interval L2 between the bit line 4B and the bit line 4D formed of the second layer metal is the wiring interval between the bit line 4B and the bit line 4c, the wiring width of the bit line 4c, and the bit line 4c and the bit line 4D. It is the sum of the wiring intervals. Therefore, the wiring interval between the bit line 4a and the bit line 4c formed of the first layer metal and the wiring interval between the bit line 4D and the bit line 4D formed of the second layer metal are the same as those of the conventional first layer. It can be made more than twice as wide as the wiring interval of bit lines formed of metal.

Here, the effect of the present invention will be examined in terms of yield. Equation (1) below is a commonly known Ein
It is a yield prediction formula of a Stein-Bose model. Y
Is the yield (%), A is the chip area (cm ² ), D is the defect density (pieces / cm ³ ), and n is the number of critical masks.

Y = 100 / (1 + AD) ⁿ (1) The yield in the prior art is Y = 30%, and the chip area A =
The number of critical masks is set to 0.88 (cm ² ) and n = 11. In this case, when the conventional defect density D is derived from the formula (1), the defect density D becomes 0.13 (pieces / cm ³ ).

Next, the predicted yield when using the present invention will be determined. The chip area A and the defect density D are 0.88 (cm ² ) and 0.13 (pieces / cm ³ ) as in the conventional case, and the number n of critical masks is N = 11 because the wiring layer is further increased.
When + 1 = 12 and the yield Y is simply calculated by the equation (1), it is 27%. This is because the number of wiring layers is further increased and the number n of critical masks is increased. At first glance, the method according to the present invention seems that the yield is deteriorated as the number of masks used is increased. However, if the yield of good products in the prior art is 30%, the actual defect cause is analyzed, and the breakdown of the remaining 70% of defective products is the function failure 8
5% and other defects 15%, and the ratio of function defects is high. Further detailed analysis of the cause of the function failure revealed that 90% of the function failures were bit line shorts due to particles. That is, in the prior art, the bit line short defect due to the particles reaches about 54% (0.7 × 0.85 × 0.9) of the whole. The present invention is intended to reduce the bit line short defect due to the particles in the prior art. If the size of the particles is smaller than the wiring interval of the bit lines widened by the present invention, the conventional problem occurs. The bit line short defect due to the particles can be almost eliminated.

Therefore, according to the present invention, when there is no functional failure due to the particles, the yield can be improved as compared with the prior art by the product of the functional failure rate × the defective rate due to the particles, specifically, about 57% (0 .73 × 0.
A yield improvement of 85 × 0.9) can be expected. That is, the yield in the present invention is 82%, which is the sum of 27% of the result of the predicted yield formula in the formula (1) and 57% described above, which is remarkably improved as compared with the yield of 30% in the conventional technique. This yield approximate estimated value is obtained by adding the expected improvement amount to the calculated value in the formula (1). If the yield improvement in the present invention is expressed only in the formula (1), the yield due to the increase in the number n of critical masks is obtained. It can be said that the yield improvement due to the decrease in the defect density D is larger than the decrease.

Further, in this rough yield estimation method, the size of the particles is smaller than the wiring interval of the bit lines widened by the present invention, and the bit line short defect due to the particles which has been conventionally generated can be almost eliminated. Although it is assumed that it is possible, it can be easily inferred that the method of widening the wiring interval of the bit lines in the present invention can contribute to the improvement of the yield even under other conditions. Further, although the embodiments of the present invention have described bit lines in a semiconductor memory device, the present invention is not limited to bit lines in a semiconductor memory device, and if the wires are arranged in parallel adjacent to each other, different wiring layers may be used. By forming, the method of the present invention can be applied.

[0016]

As described above, by forming adjacent bit lines arranged in parallel in different wiring layers from each other, wiring of bit lines formed in the same wiring layer can be performed without increasing the chip area. It is possible to provide a highly reliable semiconductor memory device in which the interval can be widened and the bit line short due to the particles generated in the wiring process can be greatly reduced, the yield can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a plan view showing an embodiment of a semiconductor memory device of the present invention.

FIG. 3 is a sectional view showing a conventional example of a semiconductor memory device.

FIG. 4 is a plan view showing a conventional example of a semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GND diffusion layer 2a, 2b Polycrystalline silicon word line 3a-3d Memory cell drain electrode 4a-4d First layer metal bit line 4B, 4D Second layer metal bit line 5a-5d Diffusion layer and first layer 5B, 5D Contact with diffusion metal and second layer metal 6 Substrate 7-9 Insulating film L1, L2 Bit line wiring interval

Claims (1)

[Claims] 1. A semiconductor memory device having a memory cell at each position where a word line and a bit line intersect, and by individually selecting the word line and the bit line, the memory data is read out individually. 2. A semiconductor memory device according to claim 1, wherein the second bit lines arranged adjacent to and parallel to the first bit line are formed in different wiring layers.