JPH06295996A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce short circuit of bit lines caused by particles generated during a wiring process, by forming a barrier composed of an insulating film between bit lines adjacently arranged in parallel. CONSTITUTION:An insulating film 7 is formed on a semiconductor substrate 6 wherein drain parts 3a, 3b, 3c of a memory cell are formed. A glass mask forming the bit lines is used as the masking material, and the insulating film 7 of bit line forming parts 11a, 11b, 11c is selectively etched. When contact apertures 5a, 5b, 5c for connecting the bit lines with the drain parts 3a, 3b, 3c are.. formed, a barrier wall composed of the insulating film 7 is formed between the contact apertures 5a and 5b and between the contact apertures 5b and 5c where the bit lines are formed. By forming the barrier composed of the insulating film between the bit lines before metal sputtering, the short circuit of bit lines due to particles generated during a metal sputtering process can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a bit line in a semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, as the manufacturing process has become finer, the distance between bit lines has become so narrow that the influence of particles generated in the wiring process cannot be ignored. Then, the particle causes a short of the bit line, which causes a malfunction of the semiconductor memory device.

FIG. 5 is a plan view of a conventional semiconductor memory device. A is an N-channel MOS transistor serving as a memory cell, 1 is a GND diffusion layer, 2a and 2b are word lines formed of polycrystalline silicon, 3a, 3b and 3c are drain parts of the memory cell, 4a and 4b, Reference numeral 4c is a bit line formed of metal, 5a, 5b and 5c are contacts between the diffusion layer and the bit line formed of metal, and 10 is a particle generated in the wiring process. The reading of the memory data is performed by selecting the word line and the bit line. For example, when the word line 2a and the bit line 4a are selected, the memory cell A
The stored data is read out. However, since the bit line 4a and the bit line 4b are shorted by the particle 10, correct reading of the memory data is not performed,
This causes malfunction of the semiconductor memory device. The particles generated in the wiring process are different from the sputter material which is generated mainly in the metal sputtering process and adheres or floats in the sputtering apparatus. Next, how the particles are generated will be described with reference to process sectional views.

FIG. 6 is a cross-sectional view of main steps of the conventional semiconductor memory device in the XY shown in FIG. The same numbers and symbols in FIGS. 6 and 5 are synonymous. FIG. 6A shows an insulating film 7 formed on the semiconductor substrate 6 on which the drain portions 3a, 3b, 3c of the memory cell are formed. FIG. 6 (b) shows the contact holes 5a, 5b and 5c for connecting the bit line and the drains 3a, 3b and 3c, respectively. FIG. 6C shows the insulating film 7 formed in FIG.
The metal 8 is formed on the contact openings 5a, 5b and 5c by the sputtering method. Reference numeral 10 denotes a particle generated during the metal sputtering process, which is shown when it is present between the contact opening 5a and the contact opening 5b. FIG. 6D shows that the bit lines 4a, 4b and 4c are selectively formed by the photo etching method. Since the particles 10 are different from the sputter material, they are hard to be removed by etching and remain between the bit lines 4a and 4b, so that the bit lines 4a and 4b are in a short state. FIG. 4 is a sectional view of a conventional semiconductor memory device, in which an insulating film 9 is formed on the surface of the semiconductor substrate formed in (d) of FIG.

At present, it is very difficult to completely eliminate the particles existing in the spatter device. Temporarily
Even if the interval between the bit lines is widened to prevent the bit line short due to the tickle, the chip area increases, and therefore there is no cost advantage.

[0006]

As described above, in the prior art,
The particles generated in the wiring process are formed between the bit lines, which causes a short of the bit lines, resulting in a malfunction of the semiconductor memory device. Therefore, it is an object of the present invention to prevent the bit line from being shorted by particles by forming a barrier made of an insulating film between the bit lines before the step of forming the bit lines.

[0007]

A semiconductor memory device according to the present invention has a memory cell at each position where a word line and a bit line intersect, and a memory is selected by selecting the word line and the bit line. In a semiconductor memory device in which data is individually read, a barrier made of an insulating film thicker than a layer for forming the bit line adjacently arranged in parallel before a wiring process is selectively formed between the bit lines. It is characterized by doing.

[0008]

According to the above structure of the present invention, by forming a barrier made of an insulating film between adjacent bit lines arranged in parallel to each other, the bit line shorts due to the particles generated in the wiring process are formed. To improve the yield of semiconductor memory devices.

[0009]

FIG. 2 is a plan view of a semiconductor memory device according to the present invention. A is an N-channel MOS transistor serving as a memory cell, 1 is a GND diffusion layer, 2a and 2b are word lines formed of polycrystalline silicon, 3a, 3b and 3c are drain parts of the memory cell, 4a and 4b, Reference numeral 4c is a bit line formed of metal, 5a, 5b, 5c are contacts between the diffusion layer and the bit line formed of metal, and 10 is a particle of about 1 μm diameter generated in the wiring process. The reading of the memory data is performed by selecting the word line and the bit line. For example, when the word line 2a and the bit line 4a are selected, the storage data of the memory cell A is read. In the figure, it seems that the bit line 4a and the bit line 4b are short-circuited by the particle 10 but this is not a practical problem. The reason for this will be described with reference to sectional views of main steps.

FIG. 3 is a sectional view showing main steps in one embodiment of the present invention in the XY direction shown in FIG. The same numbers and symbols in FIGS. 3 and 2 are synonymous. FIG. 3A shows an insulating film 7 having a thickness of 10000Å formed on the semiconductor substrate 6 on which the drain portions 3a, 3b, 3c of the memory cell are formed. In FIG. 3B, the bit line forming portion 11 is selectively formed by a photoetching method using the insulating film 7 formed in FIG. 3A as a masking material with a glass mask for forming a bit line.
The insulating films 7 of a, 11b, and 11c are etched to a thickness of 3000 Å. FIG. 3 (c) shows the contact holes 5a, 5b and 5c for connecting the bit line and the drains 3a, 3b and 3c, respectively. As shown in the figure, a barrier made of the insulating film 7 is formed between the contact opening 5a and the contact opening 5b where the bit line is formed and between the contact opening 5b and the contact opening 5c.
FIG. 3D shows a 5000 .ANG.-thick metal 8 formed by sputtering on the insulating film 7 and the contact openings 5a, 5b, 5c formed in FIG. 3C. 10 is a particle generated during the metal sputtering process,
The contact opening 5a and the contact opening 5 as in the conventional case
The case where it exists between b is shown. In this case, the insulating film 7 formed between the contact openings 5a and 5b
The particle 10 exists on the barrier consisting of. Figure 3
(E) shows that the bit lines 4a, 4b and 4c are selectively formed by the photo-etching method. As shown in FIG. 3D, since the shapes of both ends of the bit lines 4a, 4b, 4c are formed along the barrier made of the insulating film 7, the exposure amount when etching the metal is increased as compared with the conventional case. Since the particles 10 are different from the sputter material, they are hard to be removed by etching and remain between the bit lines 4a and 4b, that is, on the barrier made of the insulating film 7. It is possible to prevent the short circuit between the bit lines 4a and 4b. FIG. 1 is a sectional view showing an embodiment of the semiconductor memory device of the present invention, in which an insulating film 9 is formed on the surface of the semiconductor substrate formed in FIG.
Is formed. In this figure, the particle 10 is omitted.

Therefore, by forming a barrier made of an insulating film between the bit lines before the metal sputtering, it is possible to prevent the bit line short due to the particles generated during the metal sputtering process.

Although the positions of the particles 10 are described between the bit lines, even if the particles 10 are present on one of the bit lines, they are adjacent to each other due to the barrier made of the insulating film 7 formed between the bit lines. No short circuit with the bit line occurs. Further, although the particles generated in the wiring process have been described, the effect of the present invention is obviously great also for the particles attached after the wiring process.

[0013]

As described above, the barrier made of the insulating film is formed between the bit lines arranged in parallel adjacent to each other before the wiring process, and the glass mask for forming the bit lines is used as a masking material. , Without increasing the barrier formation mask, without increasing the chip area, the bit line short due to the particles generated in the wiring process can be significantly reduced, and the yield can be improved and the reliability is high. A semiconductor memory device can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a plan view of a semiconductor memory device of the present invention.

FIG. 3 is a sectional view showing main steps of an embodiment of a semiconductor memory device of the present invention.

FIG. 4 is a sectional view of a conventional semiconductor memory device.

FIG. 5 is a plan view of a conventional semiconductor memory device.

FIG. 6 is a sectional view showing main steps of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GND diffusion layer 2a, 2b Polycrystalline silicon word line 3a-3c Drain electrode of memory cell 4a-4c Bit line 5a-5c Contact between diffusion layer and bit line 6 Semiconductor substrate 7, 9 Insulating film 8 Metal layer 10 P -Tickle

Claims (2)

[Claims] 1. A semiconductor memory device having a memory cell at each position where a word line and a bit line intersect, and by individually selecting the word line and the bit line, the memory data is read out individually. 2. A semiconductor memory device according to claim 1, wherein a barrier made of an insulating film that is thicker than a layer for forming the bit line adjacently arranged in parallel before the wiring step is selectively formed between the bit lines. 2. A semiconductor memory device having a memory cell at each position where a word line and a bit line intersect, and reading the memory data individually by selecting the word line and the bit line. Prior to the wiring step, an insulating film thicker than a metal layer forming the bit lines adjacently arranged in parallel is formed on the semiconductor substrate, and the glass mask for forming the bit lines is selectively used as a masking material. A manufacturing method of a semiconductor memory device, characterized in that the insulating film of a bit line forming portion is etched to form a contact connecting the bit line and a diffusion layer, and a barrier made of the insulating film is formed between the bit lines. Method.