JPH0722395A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0722395A
JPH0722395A JP15194293A JP15194293A JPH0722395A JP H0722395 A JPH0722395 A JP H0722395A JP 15194293 A JP15194293 A JP 15194293A JP 15194293 A JP15194293 A JP 15194293A JP H0722395 A JPH0722395 A JP H0722395A
Authority
JP
Japan
Prior art keywords
film
photoresist
contact hole
photoresist film
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15194293A
Other languages
Japanese (ja)
Inventor
Soichi Nishida
宗一 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15194293A priority Critical patent/JPH0722395A/en
Publication of JPH0722395A publication Critical patent/JPH0722395A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance a metal wiring material in step coverage by a method wherein a tapered contact hole is provided in an interlayer insulating film only by reactive ion etching. CONSTITUTION:A photoresist film 3 high in development solubility and a photoresist film 31 lower in solubility than the film 3 are successively laminated on an interlayer insulating film 2 by spin coating, exposed to light, and developed. As the photoresist film 3 is more dissolved than the photoresist 31 tat development, a photomask pattern of large overhang structure is formed. When the interlayer insulating film 2 is removed through a reactive ion etching method using this photomask as a mask, ions not only vertical but also oblique take part enough in etching, and a sputtering phenomenon caused by oblique ions is restrained from occurring on a resist film, so that a forward tapered contact hole can be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関するものであり、特に微細なコンタクトホールの形成
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to the formation of fine contact holes.

【0002】[0002]

【従来の技術】半導体集積回路製造において、超微細加
工技術によって、現在ハーフミクロンルールの半導体装
置が製作されつつある。微細化が進むにつれて最も問題
となる工程はコンタクトホールの形成工程である。これ
は半導体集積回路のチップ面積を可能な限り小さくする
ために、平面方向での微細化が急速に進められてきた一
方、垂直方向の微細化の進行が平面方向の場合よりも遅
れてきた。例えば、コンタクトホールのアスペクト比
(コンタクトホールの深さをコンタクトホールの口径で
割った比)の増大を招いている。コンタクトホールのア
スペクト比が大きくなるとコンタクトホール部分におけ
る金属配線材料の段差被覆性の低下をもたらし、コンタ
クト抵抗の増大、信頼性の低下等を招く。図3(a)〜
(d)に従来のリアクティブイオンエッチを用いたコン
タクトホール形成の工程断面フローを示す。図3(d)
から明らかなようにアスペクト比が大きくなると金属配
線材料4の段差被覆性は極端に悪化する。コンタクトホ
ール部分における金属配線材料の段差被覆性を向上させ
るには、コンタクトホールを順テーパー状とすることが
最も効果がある。
2. Description of the Related Art In the manufacture of semiconductor integrated circuits, a semiconductor device having a half micron rule is currently being manufactured by an ultrafine processing technique. The process that becomes the most problematic as miniaturization progresses is the process of forming contact holes. In order to reduce the chip area of the semiconductor integrated circuit as much as possible, the miniaturization in the plane direction has been rapidly advanced, but the miniaturization in the vertical direction has been delayed as compared with the case of the plane direction. For example, the aspect ratio of the contact hole (ratio of the depth of the contact hole divided by the diameter of the contact hole) is increased. When the aspect ratio of the contact hole is increased, the step coverage of the metal wiring material in the contact hole portion is deteriorated, and the contact resistance is increased and the reliability is decreased. Fig.3 (a)-
(D) shows a process cross-sectional flow of contact hole formation using conventional reactive ion etching. Figure 3 (d)
As is clear from the above, when the aspect ratio is increased, the step coverage of the metal wiring material 4 is extremely deteriorated. In order to improve the step coverage of the metal wiring material in the contact hole portion, it is most effective to form the contact hole in a forward tapered shape.

【0003】しかし、一般的に用いられるリアクティブ
イオンエッチングで、シリコン酸化膜をエッチングする
場合、実用的なエッチングレートを得るためには、イオ
ン性を強くする必要があり異方性エッチングとなる。ラ
ジカル成分を用いた等方性ドライエッチングではエッチ
ングレートが小さく、実用的とは言えない。また、対ホ
トレジスト選択比(シリコン酸化膜のエッチングレート
をホトレジスト膜のエッチングレートで割った比)を低
く設定し、順テーパーに形成したホトレジストマスクを
エッチングで後退させながら、テーパーエッチングを実
現する例がある。しかしこの場合でも、微細なパターン
で順テーパー状のホトレジストパターンを形成すること
が難しく、比較的大きなパターンしか順テーパー状のコ
ンタクトホールを得ることができない。
However, when the silicon oxide film is etched by the commonly used reactive ion etching, in order to obtain a practical etching rate, it is necessary to increase the ionicity, which is anisotropic etching. Isotropic dry etching using a radical component has a low etching rate and is not practical. In addition, there is an example in which taper etching is realized by setting a low selection ratio to the photoresist (ratio of the etching rate of the silicon oxide film divided by the etching rate of the photoresist film) and retreating the forwardly tapered photoresist mask by etching. is there. However, even in this case, it is difficult to form a forward tapered photoresist pattern with a fine pattern, and a forward tapered contact hole can be obtained only with a relatively large pattern.

【0004】[0004]

【発明が解決しようとする課題】本発明はシリコン酸化
膜に順テーパーを有するコンタクトホールを等方性エッ
チングであるウェット処理を行わず、リアクティブイオ
ンエッチング工程のみで実現しうるもので、微細なコン
タクトホール部分における金属配線材料の段差被覆性を
向上させることができる。
According to the present invention, a contact hole having a forward taper in a silicon oxide film can be realized only by a reactive ion etching process without performing a wet process which is an isotropic etching. The step coverage of the metal wiring material in the contact hole portion can be improved.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置の製造方法は、層間絶縁膜上
に、オーバーハング形状を有するホトレジスト膜で、リ
アクティブイオンエッチングを行い、前記層間絶縁膜に
順テーパー状のコンタクトホールを形成する。
In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention is characterized in that a reactive ion etching is performed on an interlayer insulating film with a photoresist film having an overhang shape, A forward tapered contact hole is formed in the interlayer insulating film.

【0006】また、前記ホトレジスト膜は、現像液に対
する溶解性の高い方を上層にして形成されている。
Further, the photoresist film is formed with an upper layer having higher solubility in a developing solution as an upper layer.

【0007】[0007]

【作用】本発明を用いることにより、比較的簡単な方法
で理想的なテーパー状コンタクトホールの形成が可能と
なり、金属配線材料の段差被覆性を向上させデバイスの
信頼性を向上させることに寄与するものである。
By using the present invention, it is possible to form an ideal tapered contact hole by a relatively simple method, which contributes to improving the step coverage of the metal wiring material and improving the reliability of the device. It is a thing.

【0008】[0008]

【実施例】本発明の一実施例を図を用いて説明する。図
1(a)〜(e)は本発明を用いた半導体装置の製造方
法における工程断面フローを示している。図面中には、
分離やゲート形成の工程は省いてある。図1(a)は半
導体基板1上に分離やゲート、拡散等を形成したあと絶
縁膜2を堆積した所を示したものである。図1(b)
は、層間絶縁膜2の上にホトレジスト膜3を1.5μm
回転塗布し、さらにホトレジスト膜3よりも現像時の溶
解速度の小さいホトレジスト膜31を0.5μm回転塗
布する。
Embodiment An embodiment of the present invention will be described with reference to the drawings. 1A to 1E show process cross-sectional flows in a method for manufacturing a semiconductor device using the present invention. In the drawings,
The steps of separation and gate formation are omitted. FIG. 1A shows a place where an insulating film 2 is deposited after forming isolations, gates, diffusions, etc. on a semiconductor substrate 1. Figure 1 (b)
Has a photoresist film 3 of 1.5 μm on the interlayer insulating film 2.
The photoresist film 31 is applied by spin coating, and the photoresist film 31 having a dissolution rate lower than that of the photoresist film 3 at the time of development is applied by 0.5 μm.

【0009】次に所定のマスク(レチクル)を用いて露
光、現像を行う。この時、ホトレジスト膜3は、ホトレ
ジスト膜31よりも現像溶解速度が大きいため現像時に
大きく溶解し、図1(c)に示すような大きなオーバー
ハング状のホトレジストパターンが形成される。このよ
うに大きなオーバーハング形状のレジストパターンでリ
アクティブイオンエッチングを行うと、リアクティブイ
オンエッチング時に、垂直成分のイオンだけでなく、斜
め成分のイオンが入射し易く層間絶縁膜2がテーパー状
にエッチングされる。またオーバーハング状のホトレジ
ストパターンであるので、斜め方向のイオンがホトレジ
スト膜に衝突しにくく、ホトレジスト膜からのスパッタ
リングも少なくなる。したがって発生するポリマーの量
も少なくなり、斜め方向のエッチングレートの低下が起
こりにくい。これらの理由により順テーパー状のコンタ
クトホールが形成される(図1(d))。最後に、図1
(e)は金属配線材料4をスパッタリング法で蒸着した
図である。
Next, exposure and development are performed using a predetermined mask (reticle). At this time, the photoresist film 3 has a higher developing dissolution rate than the photoresist film 31 and thus is largely dissolved during development, and a large overhanging photoresist pattern as shown in FIG. 1C is formed. When reactive ion etching is performed using such a large overhang-shaped resist pattern, not only vertical component ions but also oblique component ions are likely to enter during the reactive ion etching, and the interlayer insulating film 2 is etched into a tapered shape. To be done. Further, since the photoresist pattern has an overhang shape, diagonal ions are less likely to collide with the photoresist film, and sputtering from the photoresist film is reduced. Therefore, the amount of polymer generated is reduced, and the etching rate in the oblique direction is less likely to decrease. For these reasons, a forward tapered contact hole is formed (FIG. 1D). Finally, Figure 1
(E) is the figure which vapor-deposited the metal wiring material 4 by the sputtering method.

【0010】以上のようにリアクティブイオンエッチン
グを用い、順テーパーを有するコンタクトホールを形成
するために、ホトマスクパターンを形成する際、現像時
の溶解速度の異なるホトレジスト膜を積層構造にした
り、あるいはホトレジスト膜表面を硬化させ、現像時に
おけるホトレジスト膜表面付近の溶解速度を小さくする
ことによってホトマスクパターンに大きな逆テーパー状
のオーバーハングを形成することができる。このホトマ
スクパターンを用いてシリコン酸化膜をリアクティブイ
オンエッチングで加工を行うと、ホトマスクパターンが
逆テーパー状のオーバーハングを有するために大きな空
間が存在し、垂直成分のイオンのみならず斜め成分のイ
オンにより積極的なテーパーエッチング加工を行うこと
が可能となる(図2)。さらに、オーバーハング形状の
ホトマスクパターンではエッチング時におけるホトマス
ク材料のスパッタリング現象の発生が抑制され、ポリマ
ー付着が抑制されるため、水平成分のエッチングレート
低下が起こりにくい。
As described above, in order to form a contact hole having a forward taper by using reactive ion etching, when forming a photomask pattern, a photoresist film having a different dissolution rate during development is formed into a laminated structure, or a photoresist film is formed. By hardening the film surface and decreasing the dissolution rate in the vicinity of the photoresist film surface during development, a large reverse taper overhang can be formed in the photoresist pattern. When the silicon oxide film is processed by reactive ion etching using this photomask pattern, there is a large space because the photomask pattern has an inverse taper overhang, and not only the vertical component ions but also the diagonal component ions. This makes it possible to perform positive taper etching processing (Fig. 2). Further, in the overhang-shaped photomask pattern, the occurrence of the sputtering phenomenon of the photomask material during etching is suppressed and the polymer adhesion is suppressed, so that the etching rate of the horizontal component is less likely to decrease.

【0011】[0011]

【発明の効果】このように本発明のテーパーを有するコ
ンタクトホール形成方法を用いることにより金属配線の
コンタクトホール部分における段差被覆性が向上し、信
頼性が向上する。
As described above, by using the tapered contact hole forming method of the present invention, the step coverage in the contact hole portion of the metal wiring is improved and the reliability is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の半導体装置の製造方法にお
ける工程順断面図
FIG. 1 is a cross-sectional view in order of the steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】オーバーハング状のホトマスクを用いたリアク
ティブイオンエッチングの状態を説明する図
FIG. 2 is a diagram illustrating a state of reactive ion etching using a photomask having an overhang shape.

【図3】従来技術による半導体装置の製造方法の工程順
断面図
3A to 3C are cross-sectional views in order of steps of a method for manufacturing a semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 層間絶縁膜 3 ホトレジスト膜 4 金属配線材料 31 ホトレジスト膜 1 Silicon Substrate 2 Interlayer Insulation Film 3 Photoresist Film 4 Metal Wiring Material 31 Photoresist Film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 層間絶縁膜上に、オーバーハング形状を
有するホトレジスト膜で、リアクティブイオンエッチン
グを行い、前記層間絶縁膜に順テーパー状のコンタクト
ホールを形成することを特徴とする半導体装置の製造方
法。
1. A method of manufacturing a semiconductor device, comprising: forming a forward tapered contact hole in the interlayer insulating film by performing reactive ion etching with a photoresist film having an overhang shape on the interlayer insulating film. Method.
【請求項2】 前記ホトレジスト膜は、現像液に対する
溶解性の異なる複数のホトレジスタ膜が積層されて構成
されており、下層のホトレジスト膜の現像液に対する溶
解性が上層のホトレジスト膜の現像液に対する溶解性に
比べて高いことを特徴とする請求項1記載の半導体装置
の製造方法。
2. The photoresist film is formed by laminating a plurality of photoresist films having different solubilities in a developing solution, and the solubility of the lower photoresist film in the developing solution is the solubility of the upper photoresist film in the developing solution. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has high conductivity.
JP15194293A 1993-06-23 1993-06-23 Manufacture of semiconductor device Pending JPH0722395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15194293A JPH0722395A (en) 1993-06-23 1993-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15194293A JPH0722395A (en) 1993-06-23 1993-06-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0722395A true JPH0722395A (en) 1995-01-24

Family

ID=15529584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15194293A Pending JPH0722395A (en) 1993-06-23 1993-06-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0722395A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067032A (en) * 2005-08-30 2007-03-15 Oki Electric Ind Co Ltd Etching method, manufacturing method of metal film structure and etching structure
JP2007335628A (en) * 2006-06-15 2007-12-27 Nippon Telegr & Teleph Corp <Ntt> Contact-hole forming method
US7405156B2 (en) 2004-07-07 2008-07-29 Nec Lcd Technologies, Ltd. Method of forming wiring pattern

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405156B2 (en) 2004-07-07 2008-07-29 Nec Lcd Technologies, Ltd. Method of forming wiring pattern
CN100449697C (en) * 2004-07-07 2009-01-07 Nec液晶技术株式会社 Method of forming wiring pattern
JP2007067032A (en) * 2005-08-30 2007-03-15 Oki Electric Ind Co Ltd Etching method, manufacturing method of metal film structure and etching structure
JP4640047B2 (en) * 2005-08-30 2011-03-02 沖電気工業株式会社 Etching method, metal film structure manufacturing method, and etching structure
JP2007335628A (en) * 2006-06-15 2007-12-27 Nippon Telegr & Teleph Corp <Ntt> Contact-hole forming method

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