JP3466289B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device containing a process defect detection circuit.

[0002]

2. Description of the Related Art As semiconductor devices become finer and more highly integrated, the process is becoming more and more complicated year by year, and failure analysis by identifying the manufacturing process that causes the failure is important and takes a huge amount of time. It's very difficult. Further, this tendency is more remarkable in the random logic device having no regularity in the pattern as compared with various memory devices.

Conventionally, a test pattern for detecting a process defect is mounted on a semiconductor device, and the mounting method has adopted the following three methods. First, a process monitor wafer is included in a lot together with a production wafer. Secondly, some points in the wafer are replaced with product chips and test patterns are inserted. Third, a region is provided at the end of the product chip adjacent to the scribe line for dicing, and a test pattern is put therein. However, the above-mentioned first method cannot cope with the single-wafer processing, and the productivity is lowered because one wafer is spent on the monitor. Further, in the second and third methods,
There is a problem that the number of product chips that can be mounted on the wafer is reduced by the area used for the test pattern.

FIG. 3 is a plan view showing a chip structure of a conventional semiconductor device for a gate array, in which a test pattern for process defect detection is mounted by the third mounting method. In the figure, 1 is the basic gate
Array cell, 2 is a scribe line for dicing,
Reference numeral 3 is an input / output circuit area arranged in the peripheral portion of the chip, and 4 is a test pattern for process defect detection.

[0005]

As shown in the drawing, the conventional test pattern 4 is arranged for each chip on the scribe line 2 for dicing or at the end of the chip and adjacent to the scribe line 2. Therefore, the area for the test pattern 4 must be secured, which hinders high-density integration. Further, in order to suppress the area of the test pattern 4 to a minute one, the scale is insufficient for detecting a process defect. further,
Since the test pattern 4 is formed in the area where the basic gate array cell 1 is not formed, the underlying state differs from the circuit actually used as a product (hereinafter referred to as the product circuit), and the reliability of process defect detection is high. However, there is a problem in that

By the way, in a circuit arranged in a chip, when the number of input / output signals increases as in recent years, the chip size is determined by the number of pads because it is necessary to arrange a large number of pads in the peripheral portion, and an empty area is formed in the chip. Occurs. Also, in the gate array of random logic products,
Since the basic gate array cells are regularly formed and arranged in advance on the entire surface in a column unit, and a desired logic circuit is wired and formed by CAD, a circuit configuration is determined by the wiring, and a portion which is not wired, That is, an empty area is created.

The present invention aims to solve the above-mentioned conventional problems by paying attention to these empty areas, and makes it possible to easily analyze process defects and reduce the area used for product chips. It is an object of the present invention to obtain a highly reliable semiconductor device having a built-in test pattern for detecting a process defect with high reliability.

[0008]

A semiconductor device according to claim 1 of the present invention has a circuit structure different from the product circuit in the product chip in an empty area in the product chip having a multilayer metal wiring structure composed of n layers. Of the memory cell is incorporated as a process failure detection circuit, and the process failure detection circuit is k = 1,
For n kinds of k of 2, ..., N, each has a circuit formed from the first layer metal wiring to the kth layer metal wiring, and the circuit includes the first layer metal wiring to the kth layer metal wiring. All formed with the same process margin as the above product circuit,
There are two types, that is, only the k-th layer metal wiring forming step which is the uppermost metal wiring is formed with a process margin larger than that of the product circuit.

In a semiconductor device according to a second aspect of the present invention, a memory cell having a circuit configuration different from that of the product circuit in the product chip is defective in a process in an empty area in the product chip having a multi-layer metal wiring structure composed of n layers. Built-in as a detection circuit, the process defect detection circuit is k = 1, 2, ..., N
For the n kinds of k in the
There is a circuit in which even the layer metal wiring is formed, and there are a plurality of types of the circuit depending on the underlying conditions, and one of the contact holes for connecting the first layer metal wiring has the same process margin as the product circuit. , Others having a process margin larger than that of the product circuit, and having the desired number of combinations of the contact holes.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the empty area in the product chip is an empty area in which the basic gate array cell is formed.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first or second aspect, wherein an input / output buffer or a boundary scan line register as a process defect detection circuit is built in an empty area in the product chip. It was done.

[0012]

In the semiconductor device according to the present invention, since the process defect detection circuit is built in the empty area in the product chip, it is not necessary to separately provide a region for the process defect detection circuit, and the area used for the product chip can be reduced. Absent.
Further, since the memory cell is used, the defective memory cell can be specified from the position of the defective bit at the time of the wafer test, so that the process defect can be easily detected. Also, this invention
According to the product chip of multi-layer metal wiring structure consisting of n layers
Smell Te, up to the first layer, from the first layer to the second layer, ...,
N in which metal wirings from the first layer to the nth layer are formed
Since each process defect detection circuit is formed,
By evaluating the process failure detection circuit,
The metal wiring to be identified can be specified, and the defective process can be detected.

Also, from the first layer metal wiring to the kth layer metal wiring
The metal layer on the top layer of the process defect detection circuit
Only the line forming process, process merge larger than the product circuit
The metal wiring of layer k is defective
In this case, the k-th layer metal wiring forming process is a process merge.
The connection hole formation process is
Good can be identified. Because of this, metal wiring formation process and connection hole shape
Process defects can be detected separately from the process steps. here
The process margin is the design dimension margin and the process margin.
Equipment, including all material variations used in the process
It's Jin.

In addition, there are several types of contact holes.
The difference is the same process margin as the product circuit, and the others are larger.
Since it was formed with a wide process margin, contact holes
Defects can be specified by type.

Also, a basic gate array cell is formed.
Built-in process defect detection circuit in the free space
Therefore, the process defect detection circuit is faithful to the product circuit formation environment.
Can be formed, and the reliability of process defect detection is improved.

In addition, a process is made in an empty area in the product chip.
I / O buffer or boundary
Small free space due to built-in scan path register
Even if a memory cell cannot be formed,
I / O buffer or boundary scan
Effective process failure detection circuit
Can be included in the product chip.

[0017]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. Note that the description of the same parts as those of the conventional one will be appropriately omitted. 1 is a plan view showing a chip structure of a semiconductor device according to a first embodiment of the present invention for a gate array. In the figure, 1 to 3 are the same as the conventional one, 5 is an empty area generated after the wiring process by CAD, 6
Is a test pattern as a process defect detection circuit formed in the empty area 5 of the product chip. This test pattern 6 is formed on the base on which the basic gate array cell 1 is formed in the empty area 5 where wiring as a product circuit is not provided, and whether the metal wiring of each layer of the multilayer metal wiring is good or not is checked. It is a memory circuit for evaluation.

In the memory circuit formed by the test pattern 6, if the product circuit is, for example, three-layer metal wiring,
A first memory cell formed up to the first layer metal wiring;
It is composed of three types of memory cells, that is, a second memory cell formed from the layer metal wiring to the second layer metal wiring and a third memory cell formed from the first layer metal wiring to the third layer metal wiring. The three types of memory cells may be independent three memories, or one type of memory may allow the three types of memory cells to be identified by addresses. In the latter case, the circuit commonly used by the three types of memory cells has a pattern with a large process margin.

The test pattern 6 as described above is formed,
By performing a wafer test, the metal wiring of each layer of the multilayer metal wiring is evaluated. In this case, the evaluation includes whether the contact hole such as a contact hole or a via hole is surely opened, and whether the metal wiring is broken or short-circuited. Here, showing the relationship between the connection hole and the metal wiring, the first layer metal wiring is formed so as to fill the contact hole, and the second layer metal wiring is formed thereon so as to fill the first via hole. A third layer metal wiring is formed thereon so as to fill the second via hole. That is, for example, if the second layer metal wiring is defective, it can be seen that the first via hole forming step or the second layer metal wiring forming step is defective. Correspondence between the evaluation of each memory cell and the evaluation of the metal wiring of each layer,
The results are shown in Table 1 below.

[0020]

[Table 1]

As shown in Table 1 above, for example, the first and second
When all the third memory cells are defective I, it is understood that at least the first layer metal wiring is defective, that is, the contact hole forming step or the first layer metal wiring forming step is considered to be defective. Also, for example, the first
And in the case where the second memory cell is good and the third memory cell is bad III, it can be seen that the first and second layer metal wirings are good and the third layer metal wirings are bad, that is, the second It is considered that there is a defect in the via hole forming process or the third layer metal wiring forming process. In this way, the defective metal wiring can be specified by the evaluation of the first to third memory cells, and the defective process can be identified. The operation test of each memory cell of the test pattern 6 may be performed by switching an existing pad used for a product chip with a switch or the like. Although pads may be separately arranged, they are not limited to the peripheral portion of the chip because they are unrelated to the product circuit.

As described above, since the test pattern 6 is formed in the empty area 5 on the base on which the basic gate array cell 1 is formed, it is not necessary to separately provide an area for the test pattern 6 and it is used for a product chip. Does not reduce the area. Moreover, since the product circuit and the underlying state are the same, the test pattern 6 can be formed faithfully in the environment in which the product circuit is formed, and the reliability of process defect detection is improved. Further, since the memory circuit is used for the test pattern 6, the defective memory cell can be easily specified from the position of the defective bit in the wafer test, and the test pattern 6 can be easily evaluated at the wafer test stage. Furthermore, for product circuits with three-layer metal wiring, up to the first layer, the second layer, the third layer
Since the test pattern 6 is composed of the three types of memory cells in which the metal wirings up to the layers are respectively formed, it is possible to reliably identify the defective metal wiring.

Example 2. Next, in the above-described first embodiment, a case will be described below in which the step of forming a contact hole such as a contact hole or a via hole and the step of forming a metal wiring formed by burying this connection hole are separately detected. In the first memory cell formed using the first layer metal wiring forming step, the memory cell A formed with the same process margin as the product circuit, and the contact hole forming step with the same process margin as the product circuit, the first layer metal In the wiring forming process, two types of memory cells, that is, the memory cell B formed with a larger process margin than the product circuit are formed. Table 2 below shows the correspondence between the evaluation of the first memory cell consisting of the two types A and B and the defective process in the wafer test.

[0024]

[Table 2]

As shown in Table 2 above, for example, when the memory cell A and the memory cell B are defective I, it is understood that at least the contact hole forming step has a defect. Further, for example, only the memory cell A is defective II
In the case of, it can be seen that the contact hole forming process is good and the first layer metal wiring forming process is defective.

When the memory cells of A and B types are formed for each of the first to third memory cells in the first embodiment, the connecting hole forming step and the metal wiring forming step of all layers of the three-layer metal wiring are formed. And can be separated to detect defects.
In this case, the memory cell B is formed by enlarging the process margin of the metal wiring forming process of the final layer for the evaluation of the contact hole.

Example 3. Next, a case will be described in which the type of contact hole is separated and the defect is detected when the defect is detected in the contact hole forming step in the second embodiment. In the contact hole,
Some are formed on the gate electrode, the N ⁺ type diffusion layer, or the P ⁺ type diffusion layer, and their shapes are slightly different depending on the thickness of the interlayer insulating film and the underlying conditions. Therefore, the occurrence of defects is not the same, and which kind of contact hole is defective is identified as follows.

In the memory cell B of the first memory cell of the test pattern 6 in the second embodiment, among the contact hole on the gate electrode, the contact hole on the N ⁺ type diffusion layer, or the contact hole on the P ⁺ type diffusion layer, Only the contact hole of interest has the same process margin as the product circuit, and the other contact holes and the first layer metal wiring are formed with a larger process margin than the product circuit. That is, the memory cell B is composed of three types of memory cells focusing on each of the three types of contact holes. Thus, when a defect is detected in any of the above-mentioned three types of memory cells in the wafer test, it can be seen that the contact hole of the type focused on by the defective memory cell is defective. In this way, defects can be detected by separating the types of contact holes.

Example 4. In the first to third embodiments, the test pattern 6 uses the memory circuit including a plurality of types of memory cells. However, in the case where the memory circuit cannot be formed due to space limitations, the input / output buffers existing in all devices, or A logic circuit including a transistor, and a boundary scan path register for testing an assembled chip on a mounted board may be used. Since these I / O buffers and boundary scan campus registers occupy a smaller area than memory cells, it is possible to construct an effective test pattern 6 even in a small area.

FIG. 2 is a schematic diagram showing the internal structure of the chip. In FIG. 2A, 7 is an input buffer, 8 is an output buffer, 9 is a random logic circuit, and 10 is a switch control circuit. A partially enlarged view of the random logic circuit 9 is shown in FIG. 2B. In FIG. 2B, 11 is a boundary scan path register, and 12 is an internal logic circuit.

In the fourth embodiment as well, the test pattern is formed in a vacant area in the chip, and like the first to third embodiments, a plurality of types of input / output buffers having different use steps or process margins in the multilayer metal wiring ( Alternatively, a boundary scan campus register) is formed, and switches are switched by the switch control circuit 10 to perform an operation test of each input / output buffer (or boundary scan campus register).

[0032]

As described above, according to the present invention, since the process defect detection circuit is built in the empty area in the product chip, the area used for the product chip is not reduced. Further, since the memory cell is used as the process defect detection circuit, the defect can be easily detected at the wafer test stage. In addition, in the multi-layer metal wiring structure consisting of n layers,
A process from the first layer metal wiring to the kth layer metal wiring
There is a defect detection circuit for n types of k = 1, 2, ...
Therefore, the defective metal wiring can be easily identified and
Can be detected. Furthermore, from the first layer metal wiring to the kth layer gold
A process defect detection circuit that includes even metal wiring is
Formed with the same process margin as the road, and the k-th layer gold
Larger process margin for metal wiring formation process than product circuit
Since it has two types, one formed with
Process defect detection process by separating the process
You can do it.

In addition, among the plural kinds of contact holes
The difference is the same process margin as the product circuit, and the others are larger.
Since it was formed with a wide process margin, contact holes
Can be separated by type to detect defects.

Also, a basic gate array cell is formed.
Built-in process defect detection circuit in the free space
Therefore, it becomes true to the production environment of the product circuit and the process failure detection
The reliability of output is improved.

Input / output as a process defect detection circuit
Using a buffer or boundary scan path register
Therefore, even if the free space is small, effective process defect detection is possible.
The circuit can be built into the product chip.

[Brief description of drawings]

FIG. 1 is a plan view showing a chip configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an internal configuration of a chip.

FIG. 3 is a plan view showing a chip configuration of a conventional semiconductor device.

[Explanation of symbols]

1 basic gate array cell, 5 free areas, 6 test pattern as process defect detection circuit, 7 input buffer, 8 output buffer, 11 boundary scan campus register.

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-2-307266 (JP, A) JP-A-5-45421 (JP, A) JP-A-5-166911 (JP, A) JP-A-6- 258390 (JP, A) JP-A-3-163844 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 21/66 H01L 27/118 H01L 27/04 G06F 17/50 G01R 31/28

Claims (4)

(57) [Claims] 1. A memory cell having a circuit configuration different from that of the product circuit in the product chip is incorporated as a process defect detection circuit in an empty area in the product chip having a multi-layered metal wiring structure composed of n layers, and the process defect detection circuit is detected. The circuit is k = 1,2,
.., for n kinds of k, each has a circuit formed from the first-layer metal wiring to the k-th layer metal wiring, and the circuit includes all of the first-layer metal wiring to the k-th layer metal wiring as described above. It is characterized by having two types: one formed with the same process margin as the product circuit, and one formed with only the k-th layer metal wiring forming step which is the uppermost metal wiring with a larger process margin than the product circuit. Semiconductor device. 2. A memory cell having a circuit configuration different from that of the product circuit in the product chip is incorporated as a process defect detection circuit in an empty area in the product chip having a multilayer metal wiring structure composed of n layers, and the process defect detection circuit is provided. The circuit is k = 1,2,
.., for n kinds of n k, each has a circuit formed from the first-layer metal wiring to the k-th layer metal wiring, and there are a plurality of types of the circuits depending on the underlying conditions. One of the contact holes for connecting the is formed with the same process margin as the above product circuit, and the other is formed with a larger process margin than the above product circuit.
A semiconductor device having a desired number of combinations of the contact holes. 3. The semiconductor device according to claim 1, wherein the empty area in the product chip is an empty area in which the basic gate array cell is formed. 4. A claim in an empty area in the product chip, characterized in that a built-in output buffer or boundary scan path register as process failure detection circuit 1
Alternatively, the semiconductor device according to item 2 .