JPH05283531A - Wiring board and formation thereof - Google Patents

Abstract

PURPOSE:To test the wiring of a semiconductor circuit device employing master slice system in a short time and to shorten the time required for correcting the process of wiring board after wiring test. CONSTITUTION:Wiring technology for semiconductor circuit device employing master slice system comprises a step for arranging power supply wirings 16G, 16V on an underlying wiring layer on the main surface of a substrate 10 and then arranging signal wirings 185, 205 on an upper wiring layer. Appearance test and electrical characteristic test of the signal wirings are then performed and a preceding step is corrected if any defect is found.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming technique,
In particular, the present invention relates to a technique effectively applied to a multilayer wiring technique of a semiconductor integrated circuit device.

[0002]

BACKGROUND ART gate array type semiconductor integrated circuit device for so-called application specific where produced by a method such as a master slice method (ASIC: A pplication S pecific I ntegra
ted C ircuit) is a variety of products, suitable for small-scale production and has the characteristic that it can be developed in a short period of time.

For example, in a semiconductor integrated circuit device adopting the master slice method, basically, a semiconductor substrate (semiconductor pellet) having a rectangular planar shape is mainly constituted. A logic circuit is arranged in the central region of the main surface of the semiconductor substrate. An interface circuit is arranged around the logic circuit, and external terminals are arranged around the interface circuit.

In a semiconductor integrated circuit device adopting a general master slice method, the logic circuit regularly arranges basic cells (basic cells), which are basic units of a repeating pattern having a basic design, in a matrix. To do. The basic cells regularly arranged in the logic circuit and the basic cells are connected by a plurality of layers of wiring, and the basic cell can form a desired logic circuit according to the application. A semiconductor integrated circuit device adopting this type of master slice system can form various logic circuits by changing the pattern of the connection without changing the arrangement of the basic cells.

In the interface circuit, similarly, basic interface cells having a basic design are regularly arranged, and the interface basic cells are connected. By changing the wiring pattern in various ways, an input or output interface circuit can be constructed according to the application.

[0006] The master slice type semiconductor integrated circuit device is a logic circuit employing a wire connection computer to apply to each of the interface circuits - automatic placement and routing system using the data: almost automatically formed by (DA D esign A utomation) To be done.

For example, when a so-called three-layer wiring structure having three wiring layers on which aluminum wiring (connection) is arranged is adopted, the first wiring layer and the second wiring layer are respectively provided. Signal wirings that connect the basic cells of the logic circuit and between the basic cells, and the basic cells of the interface circuit and between the basic cells are arranged.
The signal wiring has a small wiring width dimension and is microfabricated in accordance with the size and arrangement dimension of the semiconductor elements arranged in the basic cell. Moreover, since the integration degree of the semiconductor integrated circuit device decreases as the number of unconnected lines increases (the usage rate of basic cells decreases), the signal wiring is subjected to fine processing for the purpose of reducing the number of unconnected lines. The number is increased.

In the third wiring layer, power wiring for supplying power to the above-mentioned plurality of basic cells (particularly,
Power supply wiring as a main line) is arranged. The power supply wiring is formed with a wiring width dimension several to several hundred times larger than that of the above-mentioned signal wiring in consideration of voltage drop and current density, and is arranged over substantially the entire area of the logic circuit and the area of the interface circuit. ..

As described above, when the semiconductor integrated circuit device adopting the master slice method is designed and developed in the automatic placement and routing system, the manufacturing mask is created based on the designed information. This manufacturing mask is used in the manufacturing process of the semiconductor integrated circuit device, and when the manufacturing process is completed, the semiconductor integrated circuit device adopting the master slice method as a product is completed.

All or some of the semiconductor integrated circuit devices adopting the completed master slice method are subjected to inspections such as visual inspection and electrical characteristic inspection to determine whether they are good products or defective products. Sorting is done. In addition, especially when a defective product occurs, analyze the cause of the defect,
As a result, the manufacturing process is corrected and the manufacturing mask is corrected, and the work of increasing the yield of the semiconductor integrated circuit device adopting the master slice method is performed.

[0011]

However, the present inventor has found the following problems in the inspection such as the appearance inspection and the electrical characteristic inspection of the semiconductor slice circuit device adopting the master slice method.

(1) In the appearance inspection and electrical characteristic inspection of the semiconductor integrated circuit device adopting the above-mentioned master slice method, a part of good or defective processed by the most severe processing size used in the manufacturing process is inspected. By doing so, it is possible to judge whether the whole is good or bad. However, finely processed signal wirings are arranged in each of the first wiring layer and the second wiring layer, that is, in the lower wiring layer, and almost all areas of these signal wirings are covered. Since the power supply wiring is arranged on the uppermost layer which is the third wiring layer, the pattern of the signal wiring that affects the goodness and the badness is shielded by the power supply wiring and cannot be directly observed. For this reason, it is often the case that a flaw on the signal wiring or a foreign matter existing between the signal wirings (for example, a conductive foreign matter generated during processing of the signal wiring) is overlooked, and the signal wiring has a disconnection defect due to the flaw or a foreign matter. In many cases, it is not possible to detect a short circuit defect between signal wirings.

(2) Further, in order to inspect the above-mentioned disconnection defect and short circuit defect of the signal wiring, it is necessary to peel off the power supply wiring arranged in the uppermost wiring layer. Therefore, the time required for the inspection such as the work of peeling off the power supply wiring is increased, and the time required for the correction of the manufacturing process is increased.

It is an object of the present invention to provide a wiring technique capable of inspecting good and bad wiring in a short time.

Another object of the present invention is to provide a wiring technique,
It is an object of the present invention to provide a technique capable of shortening the time required to correct the process of a wiring board after inspecting whether the wiring is good or bad.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) Wiring having a single-layer structure formed of a metal material or an alloy material, or a wiring having a laminated structure formed by stacking a plurality of any of the above materials or stacking both materials In a method for forming a wiring board having a plurality of layers on a main surface of a substrate, a power supply wire for supplying power is arranged on a lower wiring layer on the main surface of the substrate, and an upper layer of the lower wiring layer is arranged. A signal is transmitted to the wiring layer of, and the step of arranging the signal wiring having a smaller wiring width than the power wiring and a larger number of wirings than the power wiring, the signal wiring arranged on the wiring layer above the substrate Each is provided with a step of inspecting whether the signal is good or bad, and if a defect is detected in the signal wiring as a result of the inspection, a correction process for avoiding the defect is performed in the steps up to the inspection step.

(2) A wiring having a single-layer structure formed of a metal material or an alloy material, or a wiring having a laminated structure formed by stacking a plurality of any of the above materials or stacking both materials. In a wiring board having a plurality of layers on the main surface of the substrate, power wiring for supplying power is arranged in a lower wiring layer on the main surface of the substrate, and a wiring layer above the lower wiring layer. In addition, a signal is transmitted, and a signal wiring having a smaller wiring width than the power supply wiring and a larger number of wirings than the power supply wiring is arranged.

[0020]

According to the above-mentioned means (1), the following operational effects can be obtained. (1) In the method for forming a wiring board, the power supply wiring is arranged on the lower wiring layer on the main surface of the board, the signal wiring is arranged on the upper wiring layer, and then the wiring layer covering the upper signal wiring is formed. Since it does not exist, it is possible to perform inspections such as visual inspection and electrical characteristic inspection in a short time (immediately), and disconnection defects due to scratches on the signal wiring arranged in the upper wiring layer, and the presence of foreign matter between signal wirings. It is possible to obtain an inspection result in a short time such as a short circuit failure due to.

(2) Due to the function and effect (1), the process of forming the wiring board can be corrected in a short time based on the inspection result, and the correction time of the process of forming the wiring board can be shortened.

According to the above-mentioned means (2), it is possible to provide a wiring board which can exhibit the effect (1) and the effect (2) of the means (1).

The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device adopting the master slice method.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0025]

1 is a block diagram of a semiconductor integrated circuit device adopting a master slice method according to an embodiment of the present invention.
(Layout diagram).

As shown in FIG. 1, a semiconductor integrated circuit device 1 adopting the master slice method is mainly composed of a semiconductor pellet (for example, a single crystal silicon substrate) whose plane is square. A semiconductor integrated circuit device 1 adopting a master slice method has a plurality of interface circuits (buffer circuits) 3 and a plurality of external terminals (bonding pads) 2 arranged in peripheral regions along each of four sides of a square. To be done. Each of the plurality of external terminals 2 is arranged around the outer periphery of the plurality of interface circuits 3.

Although the number of wiring layers is not limited in this embodiment, the semiconductor integrated circuit device 1 adopting the master slice method has a three-layer wiring structure. Usually, the external terminals 2 are arranged in the uppermost wiring layer (third wiring layer). The wirings arranged in the wiring layers of the respective layers have a single-layer structure of an aluminum film (metal material) or an aluminum alloy film (alloy material), or a laminated structure mainly composed of the aluminum film. The semiconductor integrated circuit device 1 adopting the master slice method of this embodiment has a single layer structure of an aluminum alloy film. The aluminum alloy film is an aluminum film to which at least one of Cu that improves electromigration resistance and Si that improves alloy spike resistance is added. The wiring of the laminated structure is, for example, Ti
The W film, the W film, or the TiN film is laminated on at least one of the lower layer and the upper layer of the aluminum film or the aluminum alloy film.

The interface circuit 3 is arranged at each position corresponding to one (or a plurality of) external terminals 2.
The interface circuit 3 is composed of a basic cell for an input circuit and a basic cell for an output circuit, although its configuration is not shown in detail. The input circuit basic cell is mainly composed of, for example, a complementary MISFET (CMOS). In addition, the basic cell for the input circuit is a protective resistance element that constitutes an electrostatic breakdown prevention circuit or a MISFET for clamping.
Are placed. Basic cell for output circuit is complementary MI
It is mainly composed of SFET (and bipolar transistor).

The semiconductor elements of the input circuit basic cell and the output circuit basic cell are respectively the second wiring layer and the third wiring layer (the uppermost wiring) of the three wiring layers. The signal wirings arranged in each layer are mainly connected.

A power supply trunk line 16 is disposed above each of the plurality of interface circuits 3. The power supply trunk line 16 extends in the same direction as the array direction of the plurality of interface circuits 3, and as shown in FIG. 1, has a ring-shaped planar shape. The power supply trunk line 16 supplies power to the interface circuit 3 and also supplies power to a logic circuit described later. The power supply main line 16 is arranged in the first wiring layer which is the lowermost layer of the three wiring layers.
The power supply trunk line 16 is composed of a total of two types of (two) trunk lines including a reference power supply trunk line 16G and an operating power supply trunk line 16V. The reference power supply main line 16G and the operating power supply main line 16V are respectively
They are separated from each other by a predetermined distance in the wiring width direction and extend substantially parallel to each other in the wiring length direction. Power main line 16
Among them, the reference power supply main line 16G is, for example, the ground potential 0 of the circuit.
[V] is supplied, and the operating power supply main line 16V is supplied with, for example, the operating potential 5 [V] of the circuit.

The signal wiring is the interface circuit 3
For the purpose of adapting to the miniaturization and micro-arrangement of semiconductor elements, and increasing the number of arrangements and reducing the unconnected ratio (improving the degree of integration), for example, with a fine wiring width dimension of about several μm. Composed. On the other hand, the power trunk line 16
For the purpose of suppressing the voltage drop and reducing the current density,
The wiring width dimension is about several tens to several hundreds [μm].

As described above, in the semiconductor integrated circuit device 1 adopting the master slice method of the first embodiment, in the region where the interface circuit 3 is arranged, the power supply trunk line 16 is formed in the lowermost first wiring layer. And the signal wiring connecting the semiconductor elements of the interface circuit 3 is arranged on the upper layer of the power supply main line 16.

As shown in FIG. 1, the central area of the semiconductor integrated circuit device 1 employing the master slice method, that is, the area surrounded by the interface circuit 3, is as shown in FIG.
This is an area where logic circuits are arranged. In a region where this logic circuit is arranged, a plurality of basic cells (basic cells) 4 having a basic design are regularly arranged in a matrix. A plurality of basic cells 4 are regularly arranged in the lateral direction in FIG. 1 to form a basic cell row 5. A plurality of the basic cell columns 5 are regularly arranged with a wiring channel region 6 interposed in the vertical direction in FIG. That is, the semiconductor integrated circuit device 1 adopting the master slice method of this embodiment adopts the fixed channel method.

In the wiring channel region 6, the power supply trunk line 16 arranged in the lowermost first wiring layer is arranged. Similar to the power supply trunk line 16 extending in the area of the interface circuit 3, the power supply trunk line 16 is composed of a set of a reference power supply trunk line 16G and an operating power supply trunk line 16V, and is arranged in the same first wiring layer. .. The reference power supply trunk line 16G and the operating power supply trunk line 16V arranged in the wiring channel region 6 are electrically connected to the reference power supply trunk line 16G and the operating power supply trunk line 16V, respectively, which are arranged in the region of the interface circuit 3, at their respective ends. Connected to each other. The reference power supply main lines 16G are integrally formed with each other, and the operation power supply main lines 16V are electrically connected to each other through a connecting wire arranged in the second wiring layer or the third wiring layer.

The reference power supply main line 16G and the operating power supply main line 16V arranged in the wiring channel region 6 are arranged in parallel with each other and extend along the arrangement direction of the basic cells 4 in the basic cell row 5. This power trunk line 16
Except for the area where the basic cells 4 are arranged, that is, the area of the basic cell row 5, the cells are arranged over almost the entire area where the logic circuits are arranged. The power supply trunk line 16 arranged in the wiring channel region 6 mainly supplies power to the semiconductor element of the basic cell 4, that is, to the logic circuit formed by the basic cell 4 (power is also supplied to the semiconductor substrate or the well region). Be done).

Although not shown in detail in FIG. 1, the basic cell 4 is mainly composed of, for example, one or a plurality of complementary MISFETs. In one basic cell 4 or a plurality of basic cells 4, each semiconductor element is connected by signal wiring, and a predetermined basic logic circuit such as an inverter circuit, NOR gate circuit, NA
A logic circuit such as an ND gate circuit and an AND gate circuit is configured.

The signal wiring (intracell wiring) for connecting the respective semiconductor elements of the basic cell 4 is the same as in the present embodiment.
Since the power supply trunk line 16 is not arranged in the first wiring layer which is the lowermost layer in the area of the basic cell column 5, it is arranged in this first wiring layer. Signal lines 18S arranged in the second wiring layer and signal lines 20S arranged in the third wiring layer connect between the basic cells 4, that is, between the logic circuits formed by the basic cells 4. The signal wiring 18S arranged in the second wiring layer extends in the vertical direction in FIG. Signal wiring 20 arranged in the third wiring layer
S extends in the lateral direction in FIG. The signal wirings arranged in the wiring layer of the first layer, the signal wirings 18S arranged in the wiring layer of the second layer, and the signal wirings 20S arranged in the wiring layer of the third layer, which are the in-cell wirings. Both of them are basically subjected to fine processing as compared with the power supply main line 16 arranged in the wiring channel region 6.

FIG. 2 (main part cross-sectional view) shows a cross-sectional structure of a part of a region in which the logic circuit of the semiconductor integrated circuit device 1 adopting the master slice system configured as described above is arranged.

As shown in FIG. 2, the semiconductor integrated circuit device 1 adopting the master slice method is mainly composed of a semiconductor substrate 10 made of single crystal silicon.
A semiconductor element is formed in the active region of the main surface portion (element formation surface) of 0. The outer periphery of the semiconductor element is defined by the element isolation insulating film 11. A MISFET is shown as a semiconductor element. This MISFET includes a semiconductor substrate 10 (which is used as a channel formation region and is usually a well region (not shown)), a gate insulating film 12, and a gate electrode 1.
3, mainly composed of a pair of semiconductor regions 14 which are source regions or drain regions. The gate electrode 13 is formed of a so-called gate material such as a polycrystalline silicon film or a refractory metal silicide film, and the wiring 13L formed of the gate material is arranged in the same gate wiring layer as this gate electrode 13 (this embodiment). In the above, the wiring 13L is not included in the concept of the three wiring layers formed of the metal material or the alloy material described above).

As shown in FIG. 2, the above-mentioned first wiring layer is formed on the surface of the interlayer insulating film 15 covering the semiconductor element, and serves as a power supply trunk line 16 (16G and 16V) and wiring in the cell. The signal wiring 16L is arranged. This power trunk line 1
6. Each of the signal wirings 16L is connected to a semiconductor element through a connection hole formed in the interlayer insulating film 15.

The second wiring layer is formed on the surface of the interlayer insulating film 17 covering the first wiring layer, and the signal wiring 18S is mainly arranged. The signal wiring 18S is the interlayer insulating film 17
The signal wiring 16S in the lower layer is connected through the connection hole formed in.

The third wiring layer is formed on the surface of the interlayer insulating film 19 covering the second wiring layer, and the signal wiring 20S is mainly arranged. The signal wiring 20S is the interlayer insulating film 19
The signal wiring 18S in the lower layer is connected through the connection hole formed in.

A protective film 2 is formed on the third wiring layer.
1 is configured.

In each of the second wiring layer and the third wiring layer, the signal wirings 18S and 20S are mainly arranged, but the power supply trunk line is partially present in one of the wiring layers. May be extended.

Next, a method of forming the semiconductor integrated circuit device 1 adopting the above-mentioned master slice method will be described with reference to FIG.
A brief explanation will be given using (Process Flow Diagram).

First, the logic function to be mounted on the semiconductor integrated circuit device 1 adopting the master slice method is designed and a logic circuit diagram is prepared <30>.

Next, based on the logic circuit diagram, an automatic placement and routing system (DA) using a computer automatically places and connects the logic circuits. <31> First, based on the logic circuit diagram, this information is input to the automatic placement and routing system as information that can be handled by the automatic placement and routing system. Next, based on the information input to the automatic placement and routing system, the external terminal 2, the interface circuit 3, the basic cell 4, the power supply trunk line 16 (16G and 16V), etc.
Preliminarily fixed ones are automatically placed. Next, based on the information input to the automatic placement and routing system, the input circuit basic cell or the output circuit basic cell of the interface circuit 3 and the basic cell 4 in the area where the logic circuit is arranged are respectively input to the input circuit basic cell or the output circuit basic cell. The wiring (signal wiring 16L) is automatically provided, and the wiring (signal wiring 18S and 2) is automatically connected between the interface circuit 3 and the basic cell 4 and between the basic cells 4, respectively.
0S) is applied. As a result, the semiconductor integrated circuit device 1 employing the master slice method is completed in the automatic placement and routing system.

Next, a semiconductor integrated circuit device 1 adopting the master slice method completed by the automatic placement and routing system.
This information is converted into mask making data based on the design rule in this automatic placement and routing system, and the wiring mask (manufacturing mask) is made by the electron beam drawing apparatus based on the mask making data. Form <32>.

Next, using the connection mask, a device process is performed <33> to complete the semiconductor integrated circuit device 1 adopting the master slice method having a predetermined logic function.

Next, appearance inspection is performed on all or some of the completed semiconductor integrated circuit device 1 employing the master slice method <34>. This visual inspection is mainly performed by the signal wiring 16L arranged in the first wiring layer, the signal wiring 18S arranged in the second wiring layer, and the signal arranged in the third wiring layer. This is performed for the purpose of confirming the respective pattern shapes of the wiring 20S and the presence of foreign matter. In other words, in the visual inspection, in the device process, the most severe processing condition is inspected to rationalize the inspection work. In the semiconductor integrated circuit device 1 adopting the master slice method, the power supply trunk line 16 is arranged in the first wiring layer which is the lowermost layer, and the power supply trunk line 16 is arranged in each of the second wiring layer and the third wiring layer. Since each of the signal wirings 18S and 20S is arranged, there is no shield and the signal wirings 18S and 20S described above are not provided.
Appearance inspection of S can be done in a short time.

In this visual inspection, the signal wiring 16 of the semiconductor integrated circuit device 1 adopting the master slice method is used.
When any of L, 18S, and 20S is scratched and it is detected that there is a disconnection defect or a possibility of disconnection defect, or a foreign substance (conductivity) is present between the signal wirings 16L, 18S, or 20S. If they are present and it is detected that there is a short-circuit defect or there is a possibility of short-circuit defect, correction is performed in the preceding step to avoid these defects. For example, in the automatic placement and routing system, modification to change the pattern of signal wiring,
In the production of the connection mask, the modification of the signal wiring pattern of the connection mask is modified, and the modification of the process condition is performed in the device process.

In addition to or instead of the above-described visual inspection, the semiconductor integrated circuit device 1 adopting the master slice method may be subjected to the electrical characteristic inspection. As the electrical characteristic inspection, for example, an inspection electrode is formed on a predetermined signal wiring by a selective electrode layer deposition technique (FIB technique), and an inspection needle (probe needle) is brought into contact with the inspection electrode to perform a predetermined inspection. Inspect the characteristics of logic circuits.

Next, an assembling process is performed, and the semiconductor integrated circuit device 1 adopting the completed master slice method.
The semiconductor integrated circuit device 1 adopting the master slice method of this embodiment by packaging <35>
Is completed.

As described above, in the method of forming the semiconductor integrated circuit device 1 employing the master slice method having the three wiring layers (16, 18 and 20), the semiconductor substrate 10 is used.
The power supply main line 16 to which power is supplied is arranged in the first wiring layer of the lower layer on the main surface of the
Signals are transmitted to the third wiring layer and the third wiring layer, and the signal wirings 18S and 2 have a smaller wiring width than the power supply trunk line 16 and a larger number of wirings than the power supply trunk line 16.
The step of arranging 0S, the second upper layer of the semiconductor substrate 10.
The signal wirings 18S and 20S arranged in the wiring layer of the third layer and the wiring layer of the third layer are inspected for good or bad, and the result of the inspection is
When a defect is detected in any of the signal wirings 18S and 20S, each process up to the inspection process includes a step of performing a correction for avoiding the defect.

With this configuration, (1) in the method of forming the semiconductor integrated circuit device 1 employing the master slice method, the power supply trunk line 16 is arranged in the lower wiring layer on the main surface of the semiconductor substrate 10, and the upper wiring is provided. After arranging the signal wirings 18S and 20S on the layer, there is no wiring layer covering the signal wirings 18S and 20S on the upper layer, so that inspection such as appearance inspection and electrical characteristic inspection can be performed in a short time (immediately). , Disconnection failure due to scratches on the signal wirings 18S and 20S arranged in the upper wiring layer, between the signal wirings 18S and 20
It is possible to obtain the inspection result in a short time such as a short circuit failure due to the presence of foreign matter between the S. (2) Due to the action and effect (1), it is possible to make a correction in a short time on the basis of the inspection result in the formation process of the semiconductor integrated circuit device 1 adopting the master slice method, and the semiconductor integrated circuit adopting the master slice method. The modification time of the forming process of the device 1 can be shortened.

Further, in the semiconductor integrated circuit device 1 adopting the master slice method, the power supply main line 16 to which power is supplied is arranged in the lower first wiring layer on the main surface of the semiconductor substrate 10, and this lower layer is arranged. A signal is transmitted to the second wiring layer and the third wiring layer, which are the upper layers of the wiring layers, and the wiring width is smaller than that of the power supply trunk line 16 and the number of wirings is larger than that of the power supply trunk line 16. The signal wirings 18S and 20S are arranged.

With this configuration, the semiconductor integrated circuit device 1 adopting the master slice method capable of exerting the effects (1) and (2) by the above-described forming method.
Can be provided. Further, since the power supply trunk line 16 is arranged in almost the entire area of the lower wiring layer, the uneven shape of the base formed by the power supply trunk line 16 is relaxed, and the surface of the interlayer insulating film 17 above the power supply trunk line 16 is flat. Can be realized. In particular, when the interlayer insulating film 17 is formed by a flattening technique such as a quartz bias sputtering technique (a film deposition technique in which film deposition and film etching coexist), the influence of the uneven shape of the base can be reduced. The flatness of the surface of the interlayer insulating film 17 can be promoted.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device adopting a master slice method having two layers, four layers or more wiring layers. Further, the present invention is
It can be applied to a semiconductor integrated circuit device adopting a master slice method adopting a spread method.

Further, the present invention can be widely applied to a wiring technique of a semiconductor integrated circuit device having a multi-layer wiring structure in addition to the semiconductor integrated circuit device adopting the master slice method.

In addition to the semiconductor integrated circuit device, the present invention also provides a printed wiring board having a resin-based substrate having a multilayer wiring structure, a wiring substrate having a silicon substrate having a multilayer wiring structure, and the like.
Widely applicable to wiring technology.

[0062]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In the wiring technique, it is possible to inspect for good and bad wiring in a short time.

In the wiring technique, it is possible to shorten the time required to inspect the wiring for goodness and defectiveness and correct the process of the wiring board.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor integrated circuit device that employs a master slice method according to an embodiment of the present invention.

FIG. 2 is a sectional view of a part of the semiconductor integrated circuit device.

FIG. 3 is a process flow diagram of the semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit device, 2 ... External terminal, 3 ... Interface circuit, 4 ... Basic cell, 5 ... Basic cell row, 6 ... Wiring channel region, 10 ... Semiconductor substrate, 1
5, 17, 19 ... Interlayer insulating film, 16G, 16V ... Power trunk line, 16L, 18S, 21S ... Signal wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 21/3205 27/04 T 8427-4M D 8427-4M 7735-4M H01L 21/88 A (72 ) Inventor Hideyuki Hosoe 2326 Imai, Ome City, Tokyo Metropolitan Government Device Development Center, Hitachi, Ltd.

Claims (3)

[Claims] 1. A wiring layer for arranging a wiring of a single layer structure formed of a metal material or an alloy material, or a wiring of a laminated structure formed by stacking a plurality of any of the above materials or stacking both materials. In the method for forming a wiring board having a plurality of layers on the main surface of the board, the following steps (1)
And the step (2). (1) A power supply line to which power is supplied is arranged in a lower wiring layer on the main surface of the substrate, and a signal is transmitted to the upper wiring layer in the lower wiring layer, which is higher than that in the power wiring. The step of arranging the signal wiring having a smaller width and a larger number of wirings than the power wiring, (2) inspecting the signal wiring arranged on the wiring layer on the upper layer of this board for good or defective, and as a result of the inspection, the signal wiring When a defect is detected in the step, a step of performing correction to avoid the defect in the steps up to the inspection step. 2. A wiring layer for arranging a wiring of a single layer structure formed of a metal material or an alloy material, or a wiring of a laminated structure formed by stacking a plurality of any of the above materials or stacking both materials. However, in a wiring board having a plurality of layers on the main surface of the substrate, power wiring to be supplied with power is arranged in a lower wiring layer on the main surface of the substrate, and a power wiring is provided on an upper wiring layer of the lower wiring layer. Signals are transmitted, and signal wirings having a smaller wiring width than the power supply wiring and a larger number of wirings than the power supply wiring are arranged. 3. The substrate according to claim 1 or 2 is a semiconductor substrate having a plurality of semiconductor elements arranged on a main surface thereof, and the power supply wiring arranged on the lower wiring layer is the semiconductor wiring board. Power is supplied to a plurality of semiconductor elements on the main surface of the semiconductor substrate, and the signal wiring arranged in the upper wiring layer is provided between a plurality of semiconductor elements on the main surface of the semiconductor substrate or a combination of these semiconductor elements. Connect between circuits.