JP4087289B2 - Semiconductor device and inspection method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a test pattern for a semiconductor integrated circuit, which can detect an open / short defect in a semiconductor integrated circuit during manufacturing, and can electrically detect the defect in the same pattern even after the manufacturing is completed. The present invention relates to a semiconductor device having the same and an inspection method thereof.
[0002]
[Prior art]
As the density and miniaturization of semiconductor devices increase, the manufacturing process becomes complicated and it takes a long time to complete a semiconductor product. Under such circumstances, early detection of defects occurring during manufacturing is important from the standpoint of securing manufacturing yield, and various inspections are still performed during manufacturing.
As one of the methods for detecting the open / short defect of a pattern, a method of detecting a defect based on a difference in potential contrast using an SEM (scanning electron microscope) is used.
FIG. 6 shows an example of a planar layout of a conventional defect detection pattern for detecting defects with the SEM. In FIG. 6, wiring 94 connected to the silicon substrate by the semiconductor substrate contact 95 and island-shaped wirings 91 and 92 that are in the same layer as the wiring 94 and are not originally connected anywhere are arranged. Here, when the wiring 94 and the island-like wiring 92 are connected by the particles 93 or the like and a short circuit defect occurs, when the state is observed from the surface of the semiconductor device with the SEM, the short circuit defect occurs and the silicon substrate is electrically connected. The island-like wiring 92 that is in the state is observed brightly, but the island-like wiring 91 that is not short-circuited is observed darkly. Such a difference in contrast is that the island-like wiring 92 is connected to the silicon substrate, so that electrons used in the SEM are emitted to the silicon substrate through the wiring 94, whereas the island-like wiring 91 is electrically insulated. This is caused by the fact that the contrast is lowered due to charging up due to the state of being made.
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-313862
[Problems to be solved by the invention]
In principle, this method is as described above. Depending on the pattern in which a short circuit actually occurs or the state of occurrence of a defect, an intermediate luminance as shown in FIG. In some cases, it may be difficult to judge whether the product is non-defective or defective. In addition to visual inspection by such SEM, it is desirable to be able to electrically confirm non-defective / defective products with the same inspection pattern.
[0005]
Therefore, in view of the above problems, the present invention is capable of performing an electrical measurement with the same pattern even in the case where it is difficult to make a determination only by contrast inspection by SEM in open / short defect detection by the potential contrast method using SEM. It is a main object of the present invention to provide a semiconductor device having an inspection pattern that can be determined and compatible with defect detection and an inspection method thereof.
[0006]
[Means for Solving the Problems]
The semiconductor device according to claim 1 includes a semiconductor substrate, a first layer and a first wiring constituting the first layer wiring formed over the first interlayer insulating film on a semi-conductor substrate, a first on a semiconductor substrate It is formed through an interlayer insulating film, a first layer second wiring formed at a distance from the first layer first wiring and the same layer a and the first layer first wiring, the upper layer of the first layer wiring A first layer second wiring having a comb shape and being electrically connected to the semiconductor substrate, and the first layer first wiring is formed of a second layer wiring formed via a two-layer insulating film. The plurality of islands are arranged between the first layer and the second wiring at a predetermined interval, and are electrically connected to the second layer wiring. .
[0007]
According to the semiconductor device of the first aspect, it is possible to achieve both open / short detection by the potential contrast method using SEM and defect detection by electrical measurement using the same pattern. This makes it possible to accurately detect open / short defects in the semiconductor inspection pattern having the above-described configuration.
[0010]
The semiconductor device according to claim 2 , wherein a semiconductor substrate, a wiring line formed by alternately connecting a plurality of N-type semiconductor wirings and a plurality of P-type semiconductor wirings via an element isolation insulating film on the semiconductor substrate, , together with the formed via an interlayer insulating film on the upper layer of the wiring array, although a plurality of N-type semiconductor wiring and the plurality of P-type semiconductor wiring are electrically connected are not connected to each other more upper wiring and provided with, one connected to the upper layer wiring on the end portion of the wiring array of electrically connected to the semiconductor substrate, connected to upper-layer wiring to the other end of the wiring array is connected to the semiconductor substrate Tei It is characterized by not .
According to the semiconductor device of the second aspect, it is possible to detect an open defect due to the non-formation of the metal silicide that occurs at the NP type wiring boundary using the SEM during the manufacturing process of the semiconductor integrated circuit device. It is possible to respond early. Furthermore, since the electrical characteristics can be evaluated with the same pattern after the circuit is completed, it is possible to accurately detect open defects due to the formation of metal silicide that could not be found by SEM observation, improving the yield of semiconductor devices, and production loss. Contributes to reduction.
[0011]
A semiconductor device according to a third aspect is the semiconductor device according to the second aspect, wherein a plurality of N-type semiconductor wirings and a plurality of P-type semiconductor wirings have a metal silicide film formed thereon.
[0012]
According to the semiconductor device of the third aspect, the same effect as that of the second aspect is obtained.
[0013]
The method for inspecting a semiconductor device according to claim 4 , wherein a plurality of island-shaped first layer first wirings are formed on a semiconductor substrate via a first interlayer insulating film, and are formed in the same layer as the first layer first wiring. A first layer second wiring is formed via a first interlayer insulating film at a distance from the first layer first wiring , and the first layer second wiring is electrically connected to the semiconductor substrate, and then using an SEM. A step of inspecting a contrast between the first layer first wiring and the first layer second wiring, and forming a second layer wiring over the first layer first wiring via a second interlayer insulating film ; after electrically connecting the first wiring and is characterized in that it comprises a step of measuring a conduction by applying a voltage between the semiconductor substrate and the second layer wiring.
According to the semiconductor device inspection method of the fourth aspect, it is possible to detect a short-circuit defect using the SEM during the manufacturing process of the semiconductor integrated circuit device, and it is possible to cope with an abnormal manufacturing process at an early stage. In addition, since the electrical characteristics can be evaluated after the circuit is completed with the same pattern, it is possible to accurately find a short-circuit defect that could not be found by SEM observation, which contributes to improving the yield of semiconductor devices and reducing production loss.
[0014]
According to a fifth aspect of the present invention, there is provided a method for inspecting a semiconductor device, comprising: using a SEM to inspect a contrast of a plurality of upper layer wirings in the semiconductor device according to the second aspect ; And a step of measuring resistance with respect to an upper layer wiring connected to the other end of the wiring row .
[0015]
According to the semiconductor device inspection method of the fifth aspect, the same effect as that of the second aspect is obtained.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
A semiconductor inspection pattern according to the first embodiment will be described. FIG. 1 is an example of an inspection pattern for detecting a short-circuit defect in a wiring according to the present invention, and FIG. 1B is a cross-sectional configuration of a semiconductor inspection pattern when cut along a broken line A in FIG. Is shown. A plurality of wirings formed of the same conductive layer as the wiring 12 such as an aluminum film with a certain interval between the wirings of the comb-shaped first-layer second wiring 12 to which one end of a plurality of long wirings are connected. The island-shaped first layer first wiring 11 is arranged, and the wiring 12 is connected to the silicon substrate 100 through the substrate contact 13 formed in the first interlayer insulating film 101. On the other hand, the island-like wiring 11 is connected to the upper second-layer wiring 15 through the through hole 14 formed in the second interlayer insulating film 102.
Here, it is assumed that the comb-shaped wiring 12 and the island-shaped wiring 11 are electrically connected in a pattern (short circuit failure) due to particles generated when the comb-shaped wiring 12 and the island-shaped wiring 11 are formed using lithography and dry etching technology. . In this case, FIG. 2 shows a schematic plan view of the inspection pattern observed with the SEM in the state where the wirings 11 and 12 are exposed to the uppermost layer of the semiconductor device. One of the island-like wirings 11 is connected to the first-layer second wirings 12 via the particles 110 to cause a short defect 110, and electrons are emitted from the SEM to the silicon substrate 100 of FIG. A path is formed. At this time, the first layer second wiring 12, the particles 110, and the first layer first wiring 111 in which a short circuit defect has occurred due to the particles 110 are brightly observed on the SEM screen. However, in the first layer first wiring 11, the first layer first wiring 112 in which no short-circuit defect has occurred is observed dark on the screen because electrons by SEM are accumulated in the pattern.
Further, after the inspection by the SEM, the manufacture of the semiconductor integrated circuit is advanced, the second interlayer insulating film 102 of FIG. 1 is formed, and the island-like shape is formed through the through-hole 14 opened on the island-like first layer first wiring 11. The first layer first wiring 11 is connected to the second layer wiring 15, and a leakage current measurement and continuity test between the second layer wiring 15 and the first layer second wiring 12 or the silicon substrate 100 are performed using a parametric tester or the like. By doing so, it is possible to reliably detect the short-circuit defect which has been overlooked on the SEM screen with almost no contrast in the inspection in the middle of the process described above.
With the above configuration, it is possible to detect a manufacturing process abnormality early and accurately by detecting a defect by SEM in the semiconductor manufacturing process using the same inspection pattern and improving inspection accuracy by confirming electrical characteristics. This configuration can be implemented as long as the island-shaped first layer first wiring 11 such as a gate electrode such as polysilicon or a metal wiring is insulated from the silicon substrate 100. Even if the first layer first wiring 11 is a diffusion layer, it can be used as long as it is insulated from the silicon substrate 100 by an element isolation insulating film like an SOI device.
(Embodiment 2)
A semiconductor test pattern according to the second embodiment of the present invention will be described. FIG. 3 is an example of an inspection pattern for detecting an open defect in a long wiring in which N-type wiring and P-type wiring are alternately connected, and FIG. 3B is a broken line in FIG. The cross section of the semiconductor inspection pattern when cut by B is shown.
[0017]
The N-type wiring 21 and the P-type wiring 22 shown in FIG. 3 are respectively an N-type polysilicon, a P-type polysilicon, and a metal silicide layer formed on the polysilicon by a salicide process (self-aligned silicidation). It has a laminated structure. Such N-type salicide wiring 21 and P-type salicide wiring 22 are alternately connected on the element isolation insulating film 103 that is insulated from the silicon substrate 100. In a specific manufacturing method, a resist mask is formed on a long wiring made of an electrically high-resistance polysilicon film into which impurities are not introduced, and ion implantation of N-type and P-type impurities is performed at a predetermined location. Can be made separately.
[0018]
The N-type salicide wiring 21 and the P-type salicide wiring 22 are connected to the first layer first wiring 24 and the first layer second wiring 28 through the through-holes 23 formed in the first interlayer insulating film 101, respectively. The first layer first wiring 24 is connected to the silicon substrate 100 through the substrate contact 26, and the first layer second wiring 28 is connected to the electrical characteristic evaluation electrode. The remaining salicide wires 21 and 22 are connected to the first layer isolated wires 25 that are not connected to each other through the through holes 23.
[0019]
Here, when N-type or P-type polysilicon is formed by ion implantation, for example, if the resist used as an ion implantation mask is not sufficiently removed and remains on the polysilicon, a high level of Ti or the like is formed on the polysilicon surface. When a melting point metal film is formed and silicidation is performed by heat treatment, the reaction is inhibited only in the portion where the resist remains, and no silicide is formed. That is, the metal silicide 30 is not formed on the N-type polysilicon 211 or the P-type polysilicon 221 by the salicide process as shown in the polysilicon wiring cross-sectional view of FIG. Unformed wiring 230 may be formed. Although the salicide wiring on which the metal silicide film 30 itself is formed has a low resistance, the N-type impurity and the P-type impurity are included in almost the same concentration in the metal silicide-unformed wiring, and therefore several orders of magnitude or more compared to the silicide wiring. In other words, the open resistance is poor.
[0020]
FIG. 5 shows an example of SEM observation of the pattern in the above state with the first layer isolated wiring 25 exposed on the surface of the semiconductor substrate during the manufacturing process. The first-layer first wiring 24 connected to the silicon substrate 100 by the substrate contact 26 in FIG. 3 and the first-layer isolated wiring 251 existing between the wiring 24 and the metal silicide-unformed wiring 230 are connected to the silicon substrate 100. Since a passage of electrons from the SEM is formed, it is brightly observed in the SEM observation. On the other hand, the first layer second wiring 28 not connected to the silicon substrate, and the first layer isolated wiring 252 existing between the first layer second wiring 28 and the metal silicide unformed wiring 230 are electrons to the silicon substrate. Since there is no loop-off, it is observed dark by SEM observation.
[0021]
However, if the length of the metal silicide-unformed wiring 230 is short, the resistance value of the wiring 230 becomes small, so that the contrast difference by SEM observation becomes small and it becomes difficult to detect a defect. Therefore, after the manufacture of the semiconductor integrated circuit on which this inspection pattern is mounted is completed, resistance measurement is performed between the first layer first wiring 24 and the first layer second wiring 28 by a parametric tester or the like, and SEM observation is performed. It becomes possible to detect an open defect due to the metal silicide not being formed that could not be detected by the inspection.
[0022]
With the above configuration, it is possible to detect an abnormality in the manufacturing process quickly and accurately by detecting open defects in the semiconductor manufacturing process and improving inspection accuracy by confirming electrical characteristics.
[0023]
Note that the PN-alternated silicided polysilicon wiring shown in the second embodiment is actually used as a dual-gate wiring in which a P-type polysilicon gate electrode and an N-type polysilicon gate electrode are directly connected. .
[0024]
【The invention's effect】
According to the semiconductor device of the first aspect, it is possible to achieve both open / short detection by the potential contrast method using SEM and defect detection by electrical measurement using the same pattern. This makes it possible to accurately detect open / short defects in the semiconductor inspection pattern having the above-described configuration.
[0025]
According to the semiconductor device of 請 Motomeko 2, it is possible to detect an open failure due to metal silicide non-forming which occurs by N-P-type wiring boundary using SEM in the semiconductor integrated circuit device manufacturing process, the manufacturing process abnormalities It is possible to respond to the problem early. Furthermore, since the electrical characteristics can be evaluated with the same pattern after the circuit is completed, it is possible to accurately detect open defects due to the formation of metal silicide that could not be found by SEM observation, improving the yield of semiconductor devices, and production loss. Contributes to reduction.
[0026]
According to the semiconductor device of the third aspect, the same effect as that of the second aspect is obtained.
According to the semiconductor device inspection method of the fourth aspect, it is possible to detect a short-circuit defect using the SEM during the manufacturing process of the semiconductor integrated circuit device, and it is possible to cope with an abnormal manufacturing process at an early stage. In addition, since the electrical characteristics can be evaluated after the circuit is completed with the same pattern, it is possible to accurately find a short-circuit defect that could not be found by SEM observation, which contributes to improving the yield of semiconductor devices and reducing production loss.
[0027]
According to the semiconductor device inspection method of the fifth aspect, the same effect as that of the second aspect is obtained.
[Brief description of the drawings]
FIGS. 1A and 1B are explanatory views of a semiconductor inspection pattern of a semiconductor device according to a first embodiment of the present invention, FIG. 1A is a plan view, and FIG.
FIG. 2 is an explanatory diagram for explaining a short defect inspection by a semiconductor inspection pattern of the present invention.
3A and 3B are explanatory diagrams of a semiconductor inspection pattern of a semiconductor device according to a second embodiment of the present invention, where FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along line AA in FIG.
FIG. 4 is an explanatory diagram showing a metal silicide disconnection in a semiconductor inspection pattern.
FIG. 5 is an explanatory diagram showing a disconnection defect inspection using a semiconductor inspection pattern according to the present invention.
FIG. 6 is a diagram showing a conventional open / short defect detection method;
[Explanation of symbols]
11, 24 First layer first wiring 12, 28 First layer second wiring 13, 26 Substrate contacts 14, 23 Through hole 15 Second layer wiring 100 Silicon substrate 101 First interlayer insulating film 102 Second interlayer insulating film 110 Short Defect 111 First layer first wiring 112 observed brightly by SEM observation First layer first wiring 21 observed dark by SEM observation N type salicide wiring 22 P type salicide wiring 25 First layer isolated wiring 27 NP type Boundary 103 Element isolation insulating film 30 Metal silicide film 211 N-type polysilicon 221 P-type polysilicon 230 Metal silicide unformed wiring 251 First layer isolated wiring 252 observed brightly by SEM observation First layer observed darkly by SEM observation Isolated wiring 91 Island-like wiring 92 observed dark by SEM observation Island-like wiring 93 brightly observed by SEM observation 94 Defect 94 Wiring 95 Board contact

Claims (5)

A semiconductor substrate, forming through said first layer first wiring constituting the first layer wiring formed over the first interlayer insulating film on a semiconductor substrate, the first interlayer insulating film on the semiconductor substrate is, the first layer and the first layer second wiring formed at a distance from the first wiring and the same layer a and the first layer first wiring, a second interlayer insulating film on the upper layer of the first layer wiring and a second layer wiring formed through said first layer second wiring and having a comb shape is electrically connected to said semiconductor substrate, said first layer first wiring A semiconductor device having a plurality of island shapes, arranged at a constant interval between the first layer and the second wiring, and electrically connected to the second layer wiring. A semiconductor substrate, a plurality of N-type semiconductor wiring and a plurality of wiring array that P-type semiconductor wiring and is formed through an element isolation insulating film on the semiconductor substrate are connected alternately, an interlayer on the upper layer of the wiring array together Once formed via an insulating film, and a plurality of upper wiring the plurality of the N-type semiconductor wiring and the plurality of P-type semiconductor wiring are electrically connected but not connected to each other wherein said one end portion connected to said upper wiring of the wiring column the semiconductor substrate to be electrically connected, connected to said upper wiring to the other end of the wiring column are connected to said semiconductor substrate A semiconductor device characterized by not . Wherein the plurality of N-type semiconductor wiring and the plurality of P-type semiconductor wiring semiconductor device according to claim 2, characterized in that on the metal silicide film is formed thereon. A plurality of island-shaped first layer first wirings are formed on a semiconductor substrate via a first interlayer insulating film, and are on the same layer as the first layer first wirings and spaced from the first layer first wirings . A first layer second wiring is formed via the first interlayer insulating film , the first layer second wiring is electrically connected to the semiconductor substrate, and then the first layer first wiring is formed using an SEM. And a step of inspecting the contrast of the first-layer second wiring, and forming a second-layer wiring over the first-layer first wiring via a second interlayer insulating film, and forming the first-layer first wiring on the first-layer first wiring after electrically connecting the inspection method of a semiconductor device which comprises the steps of measuring the conduction by applying a voltage between said semiconductor substrate and the second layer wiring. The step of inspecting the contrast of the plurality of upper layer wirings in the semiconductor device according to claim 2 using an SEM, and the upper layer wiring connected to one end of the wiring row and the other end of the wiring row a method of inspecting a semiconductor device, which comprises a step of resistance measured between the connected the upper wiring.

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