JP2003051521A - Connection hole monitor and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a connection hole monitor capable of improving inspection accuracy and efficiency. SOLUTION: A plurality of connection holes 12 lie between a common potential wiring layers 11 electrically connected to a substrate and inspection wiring layers 13, and the inspection wiring layers 13 are separated for every connection holes 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor device for determining whether or not a connection state between a conductive layer and a connection hole (contact hole) connecting the conductive layer is good or bad during a manufacturing process of a semiconductor device. is there.

In the process of manufacturing a semiconductor device, an inspection is performed to determine whether the connection state between the conductive layer and the connection hole is good or bad.
In such an inspection, an optical shape inspection, an inspection by a charge-up contrast method using a scanning electron microscope (SEM), and the like are performed on a monitor formed on a wafer, so that the monitor is formed in the same process. The connection state between the conductive layer in the chip and the connection hole is estimated. Then, it is necessary to improve the accuracy of such inspection and improve the inspection efficiency.

[0003]

2. Description of the Related Art Conventionally, an optical inspection has been performed as an inspection for determining the quality of the connection between a conductive layer and a connection hole. However, due to the miniaturization of patterns accompanying the recent high integration of semiconductor devices, Optical shape inspection cannot reliably detect abnormalities in connection holes.

Therefore, an inspection by a charge-up contrast method using a scanning electron microscope (SEM) is performed. FIG. 7 shows a connection hole monitor used for inspection by the charge-up contrast method. The diffusion layer 1 formed on the wafer substrate is connected to the first wiring layers 3a and 3b via the diffusion layer contacts 2a and 2b. The diffusion layer contacts 2a and 2b are formed in the same process as the diffusion layer contacts of other chips formed on the wafer substrate,
The first-layer wiring layers 3a and 3b are formed in the same process as the first-layer wiring layers of other chips formed on the wafer substrate.

The first wiring layer 3a is connected to the second wiring layer 5 through the connection hole 4a, and the first wiring layer 3b is connected to the connection hole 4a.
It is connected to the second wiring layer 5 via b. Connection hole 4a,
4b is formed in the same process as a connection hole of another chip formed on the wafer substrate, and the second layer wiring layer 5 is formed in the same process as a second layer wiring layer of another chip. Then, the above layers are sequentially covered with the interlayer insulating film 6.

In the connection hole monitor thus constructed,
When the connection holes 4a and 4b and the second wiring layer 5 are formed separately, the connection holes 4a and 4b are inspected by the charge-up contrast method with the connection holes 4a and 4b formed. The connection inspection between the first wiring layer 3a and the first wiring layer 3b is performed.

Next, after the second wiring layer 5 is formed, the inspection is performed again to inspect the connection between the connection holes 4a and 4b and the second wiring layer 5. In the charge-up contrast method, charge is accumulated in the second wiring layer and the connection hole where the connection hole abnormality occurs, and a potential difference occurs with other wiring and the connection hole.By detecting this potential difference, the connection hole abnormality is detected. It is something to detect.

When the connection holes 4a and 4b and the second wiring layer 5 are formed in the same process by the dual damascene method, the connection holes 4a and 4b and the second wiring layer 5 are formed. A connection check is performed at.

FIG. 8 shows a connection hole monitor using a chain pattern. This connection hole monitor includes connection holes 4a and 4b.
And the first and second wiring layers 3 and 5 are connected in series, and the first wiring layer 3 is not connected to the diffusion layer 1.

In such a connection hole monitor, charge or current does not flow in the diffusion layer, so that the inspection by the charge-up contrast method cannot be performed. Therefore, the first and second wiring layers 3 and 5 and the connection holes 4a and 4 connected in series are connected.
By detecting the resistance value by contacting the probe with the second wiring layer which is the both ends of b, it is possible to determine whether the connection state between the connection holes 4a, 4b and the first layer and the second wiring layer 3, 5 is good or bad. To be detected.

[0011]

In the connection hole monitor shown in FIG. 7, the second wiring layer 5 is connected to the plurality of connection holes 4a and 4b. Therefore, in the inspection by the charge-up contrast method after forming the second wiring layer 5, the connection hole 4
Even if a connection failure occurs between any one of a and 4b and the second wiring layer 5, the diffusion layer is formed from the normally connected connection hole through the first wiring layers 3a and 3b and the diffusion layer contact 2. Since electric charge is lost to the device, it is not possible to reliably detect the defective connection.

When the connection holes 4a and 4b and the second wiring layer 5 are simultaneously formed by the dual damascene method, as shown in the figure, one connection hole 4b and the first wiring layer 3b are formed. Even if the connection hole abnormality 7 occurs between the first connection layer 3a and the diffusion layer contact 2 through the other connection hole 4a.
Since the electric charge escapes from the diffusion layer 1 to
Can not be detected.

Further, in the charge-up contrast method, since it is necessary to charge up each wiring layer and the connection hole, if the inspection area increases, the time required for the charge-up increases, the inspection time becomes longer, and the manufacturing cost increases. Rises.

Further, when a connection hole monitor having a plurality of layers of connection holes is formed, the total extension distance of the wiring layer and the connection hole is increased, so that the capacity is increased and it takes more time to charge up.

In the connection hole monitor shown in FIG. 8, it is necessary to bring the probes into contact with both ends of the second wiring layer 5. Then, the probe contact portion of the wiring layer is deformed to generate dust, which may reduce the yield of other chips due to inspection during the manufacturing process.

In order to prevent this, if the inspection during the manufacturing process is omitted and the inspection is performed only after the end of the process, each process is executed until the end of the process even for a wafer having a connection hole abnormality, so that it is useless. There is a problem that manufacturing time is spent.

An object of the present invention is to provide a connection hole monitor which can improve inspection accuracy and inspection efficiency.

[0018]

As shown in FIG. 1, a common potential wiring layer 11 and an inspection wiring layer 1 electrically connected to a substrate.
A plurality of connection holes 12 are interposed between the inspection wiring layer 13 and the wiring 3, and the inspection wiring layer 13 is separated for each connection hole 12. The charge-up contrast method makes it possible to reliably detect the connection hole.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a first embodiment of a connection hole monitor according to the present invention. The diffusion layer 1 and the diffusion layer contact 2 of this embodiment are the same as those of the conventional example, and the common potential wiring layer 1 which is the first wiring layer.
1 is connected to the diffusion layer 1 via the diffusion layer contact 2.

A large number of connection holes 12 are connected to the common potential wiring layer 11, and each connection hole 12 is connected to an inspection wiring layer 13, which is a second layer wiring layer. The inspection wiring layer 13 is a wiring layer separated for each connection hole 12.

As shown in FIG. 2, the layout of the connection holes 12 and the inspection wiring layer 13 is provided to be dense and dense so that the layout of the connection holes 12 in the chip can be reproduced. Further, as shown in FIG. 3A, a layout in which a thick inspection wiring layer 13 is formed with respect to the connection hole 12 which is a condition in which stress migration is easily deteriorated by the dual damascene method, as shown in FIG. The layout in which the inspection wiring layer 13 and the connection hole 12 are displaced from each other, FIG.
As described above, a layout or the like to which the long inspection wiring layer 13 that causes large etching damage to the connection hole 12 is connected is also formed as the connection hole monitor.

In the connection hole monitor thus constructed,
The following effects can be obtained. (1) Since the inspection wiring layer 13 is separated for each connection hole 12, when the connection hole 12 and the inspection wiring layer 13 are formed by the dual damascene method, the connection hole 12 and the common potential wiring layer are formed as shown in FIG. Even if the connection hole abnormality 14 occurs between the connection hole 11 and the connection hole 11, the connection hole abnormality 14 can be reliably detected by the charge-up contrast method. (2) Since the inspection wiring layer 13 is separated for each connection hole 12, even when the connection hole 12 and the inspection wiring layer 13 are formed in different processes, the inspection wiring layer 13 and the connection hole 12 are separated from each other. It is possible to reliably detect the abnormal connection hole. (3) By checking the connection hole monitor, the connection hole 1
2, it is possible to perform a connection test between the common potential wiring layer 11 and the inspection wiring layer 13. Therefore, since it is not necessary to inspect the entire wafer, the charge-up time can be shortened and the inspection time can be shortened. (4) Since the connection inspection can be performed by the charge-up contrast method, it is not necessary to bring the probe into contact with the inspection wiring layer 13. Therefore, it is possible to prevent the generation of dust due to the deformation of the probe contact portion, and prevent the yield of other chips from decreasing. (Second Embodiment) FIG. 5 shows a connection hole monitor according to a second embodiment. Diffusion layer contact 2, common potential wiring layer 11, connection hole 12, and inspection wiring layer 1 of this embodiment
3 is the same as in the first embodiment.

Each inspection wiring layer 13 is connected to the third layer wiring layer 16 through the connection hole 15, and the third layer wiring layer 16 and the common potential wiring layer 11 and the connection holes 12, 15 between them and the inspection wiring. The layers 13 are connected in a chain.

The connection hole 12 and the inspection wiring layer 13 include the pattern shown in FIG. 3 so that the internal state of another chip can be reproduced. A junction 17 is formed between the diffusion layer contact 2 and the diffusion layer 1. When the junction 17 and the diffusion layer 1 are charged with positive charges at the time of inspection by the charge-up contrast method, or when the SEM having a low acceleration energy near 1 KeV is used, the junction 17 is formed as a junction.
The diffusion layer 1 is formed of an N-type impurity layer.

When negative charges are charged or when an SEM having a high acceleration energy of 3 KeV or more is used, the junction 17 is formed of an N type impurity layer and the diffusion layer 1 is formed of a P type impurity layer. To do.

With such a structure, in the process of forming the inspection wiring layer 13, the same connection inspection as in the first embodiment can be performed, and the connection hole 12 and the common potential wiring are formed by the charge-up contrast method. A connection hole abnormality between the layer 11 and the inspection wiring layer 13 can be detected.

With the third wiring layer 16 formed, connection inspection of each wiring connected in a chain can be performed.
That is, a current is applied by applying a predetermined potential difference to the chain end of the third wiring layer 16.

At this time, if the junction 17 is a P type, a voltage higher than the voltage applied to the third wiring layer 16 is supplied to the diffusion layer 1. If the junction 17 is N-type, a voltage lower than the voltage applied to the third wiring layer 16 is supplied to the diffusion layer 1.

In this state, the current flowing from the common potential wiring layer 11 to the diffusion layer 1 is cut off, so that the wirings 11, 13, 16 connected in a chain and the connection holes 12, 15 are connected.
It is possible to detect the entire resistance value of.

Then, based on the detected resistance value, it is possible to detect a connection hole abnormality between the wirings 11, 13, 16 and the connection holes 12, 15. With the connection hole monitor configured as described above, in addition to the effects obtained in the first embodiment, the following effects can be obtained. (1) By measuring the resistance value of the chain pattern, it is possible to perform an inspection for detecting a connection hole abnormality. (Third Embodiment) FIG. 6 shows a third embodiment. The diffusion layer 1, the diffusion layer contact 2 of this embodiment,
The first common potential wiring layer 11, the connection hole 12, and the first inspection wiring layer 13 have the same configurations as those in the first embodiment.

The first inspection wiring layer 13 is connected to the second common potential wiring layer 19 via the connection hole 18. The second common potential wiring layer 19 is formed in the same process as the third wiring layer of another chip.

The second common potential wiring layer 19 is connected to the second inspection wiring layer 21 via the connection hole 20. The second inspection wiring layer 21 is formed in the same process as the fourth wiring layer of another chip, and is separated for each connection hole 20.

In the connection hole monitor thus constructed,
At the time when the first inspection wiring layer 13 is formed, the connection inspection between the connection hole 12 and the first common potential wiring layer 11 and the first inspection wiring layer 13 is performed as in the first embodiment. be able to.

Further, when the second inspection wiring layer 21 is formed, the connection inspection of the connection hole 20 with the second common potential wiring layer 19 and the second inspection wiring layer 21 can be performed.
At this time, the second common potential wiring layer 19 is connected to the diffusion layer 1 if a normal connection hole exists even if a connection hole abnormality has occurred in either of the connection holes 12 and 18. , Connection test can be performed normally.

With the connection hole monitor constructed as described above, in addition to the operational effects obtained in the first embodiment, the following operational effects can be obtained. (1) First common potential wiring layer 11 and first inspection wiring layer 1
The connection hole abnormality of the connection hole 12 formed between the second common potential wiring layer 19 and the second inspection wiring layer 21 is independent of the connection hole abnormality of the connection hole 12 formed between the second common potential wiring layer 19 and the second inspection wiring layer 21. Can be inspected. (2) In the connection hole monitor shown in FIG. 6, the odd-numbered wiring layers are common potential wiring layers, but the odd-numbered wiring layers are common potential wiring layers and the even-numbered wiring layers are common. If each connection hole monitor is formed as a potential wiring layer, the connection inspection between all the wiring layers and the connection holes can be performed with the two connection hole monitors.

The above embodiment can be modified as follows. -In the second embodiment, more inspection wiring layers may be provided. (Supplementary Note 1) A connection hole monitor having a plurality of connection holes interposed between a common potential wiring layer electrically connected to a substrate and an inspection wiring layer, wherein the inspection wiring layer is separated for each connection hole. A connection hole monitor characterized by the above. (Supplementary Note 2) A diffusion layer contact is formed on a diffusion layer formed on a substrate, a common potential wiring layer is formed on the diffusion layer contact, and a plurality of connection holes are formed on the common potential wiring layer. A connection hole monitor having an inspection wiring layer formed on the connection hole, wherein the inspection wiring layer is separated for each connection hole. (Supplementary Note 3) A junction is formed between the diffusion layer and the diffusion layer contact so that the diffusion layer and the diffusion layer contact can be electrically connected and cut off, and an upper layer is connected to the inspection wiring layer through a connection hole. 3. The connection hole monitor according to appendix 2, wherein wiring layers are connected to connect the common potential wiring layer, the inspection wiring layer and the upper wiring layer in a chain shape. (Supplementary note 4) The connection hole monitor according to supplementary note 2, wherein a common potential wiring layer, a connection hole, and an inspection wiring layer are further provided on the upper layer of the inspection wiring layer. (Supplementary Note 5) A semiconductor device comprising the connection hole monitor according to at least one of Supplementary Notes 1 to 4. (Supplementary Note 6) A diffusion layer contact is formed on a diffusion layer formed on a substrate, a common potential wiring layer is formed on the diffusion layer contact, and a plurality of connection holes are formed on the common potential wiring layer. An inspection wiring layer is formed on the connection hole, and the inspection wiring layer is separated for each connection hole to form a connection hole monitor, and the connection hole is connected to the inspection wiring layer and the common potential wiring layer. A method for inspecting a semiconductor device, which comprises inspecting. (Supplementary Note 7) A diffusion layer contact is formed on a diffusion layer formed on a substrate via a junction, a common potential wiring layer is formed on the diffusion layer contact, and a plurality of connections are formed on the common potential wiring layer. A hole is formed, an inspection wiring layer is formed on the connection hole, the inspection wiring layer is separated for each connection hole to form a connection hole monitor, and a diffusion layer contact is formed as a diffusion layer via the junction. In a state of being electrically connected, the connection between the connection hole and the inspection wiring layer and the common potential wiring layer is inspected, and the upper wiring layer is connected to the inspection wiring layer through the connection hole to form the common potential wiring layer. In a state in which the inspection wiring layer and the upper wiring layer are connected in a chain shape and the junction between the diffusion layer contact and the diffusion layer is cut off at the junction,
A method for inspecting a semiconductor device, comprising detecting resistance values of wiring layers and connection holes connected in a chain.

[0037]

As described above in detail, the present invention can provide a connection hole monitor capable of improving inspection accuracy and inspection efficiency.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a connection hole monitor according to a first embodiment.

FIG. 2 is a plan view showing a connection hole monitor.

FIG. 3 is an explanatory diagram showing a layout of connection holes and inspection wiring layers.

FIG. 4 is a cross-sectional view showing a connection hole monitor in which a connection hole abnormality has occurred.

FIG. 5 is a sectional view showing a connection hole monitor according to a second embodiment.

FIG. 6 is a sectional view showing a connection hole monitor according to a third embodiment.

FIG. 7 is a cross-sectional view showing a conventional example.

FIG. 8 is a sectional view showing a conventional example.

[Explanation of symbols]

11 Common potential wiring layer 12 connection holes 13 Inspection wiring layer

Claims (5)

[Claims] 1. A connection hole monitor having a plurality of connection holes between a common potential wiring layer electrically connected to a substrate and an inspection wiring layer, wherein the inspection wiring layer is provided for each of the connection holes. A connection hole monitor characterized by being separated. 2. A diffusion layer contact is formed on a diffusion layer formed on a substrate, a common potential wiring layer is formed on the diffusion layer contact, and a plurality of connection holes are formed on the common potential wiring layer. A connection hole monitor having an inspection wiring layer formed on the connection hole, wherein the inspection wiring layer is separated for each of the connection holes. 3. A junction is formed between the diffusion layer and the diffusion layer contact so that the diffusion layer and the diffusion layer contact can be electrically connected or cut off, and the inspection wiring layer is connected to the inspection wiring layer via a connection hole. 3. The connection hole monitor according to claim 2, wherein an upper wiring layer is connected, and the common potential wiring layer, the inspection wiring layer, and the upper wiring layer are connected in a chain shape. 4. The connection hole monitor according to claim 2, wherein a common potential wiring layer, a connection hole, and an inspection wiring layer are further provided on the inspection wiring layer. 5. A semiconductor device comprising the connection hole monitor according to at least one of claims 1 to 4.