JPH065674A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH065674A JPH065674A JP4186175A JP18617592A JPH065674A JP H065674 A JPH065674 A JP H065674A JP 4186175 A JP4186175 A JP 4186175A JP 18617592 A JP18617592 A JP 18617592A JP H065674 A JPH065674 A JP H065674A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- probing needle
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特にウェハ状態でのチップ検査(以下、ウェハチェ
ックと記す)を有利に行いうる電極構造を有する半導体
集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having an electrode structure capable of advantageously performing a chip inspection (hereinafter referred to as a wafer check) in a wafer state.
【0002】[0002]
【従来の技術】LSIの製造工程においては、拡散工程
終了後に組み立て工程に先立ってウェハチェックが行わ
れる。図3は、ウェハチェック時の従来のチップ状態を
示す平面図である。同図において、1は半導体チップ、
2は電極であり、ここで、電極2は、信号電極と電源電
極とを含むものである。ウェハチェック時には信号の入
出力および電源の供給のために、電極2にテスタのプロ
ービング針を接触させて特性チェックを行う。2. Description of the Related Art In an LSI manufacturing process, a wafer check is performed after the diffusion process and prior to the assembly process. FIG. 3 is a plan view showing a conventional chip state at the time of wafer check. In the figure, 1 is a semiconductor chip,
Reference numeral 2 is an electrode, where the electrode 2 includes a signal electrode and a power supply electrode. At the time of checking the wafer, the probing needle of the tester is brought into contact with the electrode 2 for the purpose of inputting / outputting signals and supplying power, and the characteristic is checked.
【0003】通常、プロービング針の接触面積に対して
電極面積は十分広いため、例えば針が電極2の中心より
20〜30μmずれても、針が電極2からはずれてしま
うことはない。Since the electrode area is usually sufficiently large with respect to the contact area of the probing needle, even if the needle is displaced from the center of the electrode 2 by 20 to 30 μm, the needle will not be displaced from the electrode 2.
【0004】[0004]
【発明が解決しようとする課題】近年、半導体チップの
小型化あるいはウェハ面積の増大により1枚のウェハに
形成されるチップ数が増加しつつある。そのため、1枚
のウェハに対して数100回のチェックを行わなければ
ならないことがあり、そのような場合にはチェックを繰
り返しているうちにプロービング装置の誤差によりプロ
ービング針が電極2からはずれてしまうことがある。そ
して、実際のウェハチェックでは最初のプロービング針
と電極2との位置合わせ時に既に10〜20μmのずれ
を含むことが起こりうるので上記可能性はさらに高くな
る。そのため、従来の半導体集積回路装置では、本来良
品であるチップが、プロービング針の非接触のために不
良品と判定されてしまうことがあった。In recent years, the number of chips formed on one wafer has been increasing due to the miniaturization of semiconductor chips or the increase in wafer area. Therefore, it may be necessary to perform a check several hundreds of times on one wafer, and in such a case, the probing needle may come off from the electrode 2 due to an error of the probing device while the check is repeated. Sometimes. Then, in the actual wafer check, it is possible that a deviation of 10 to 20 μm is already included in the first alignment between the probing needle and the electrode 2, so the above possibility is further increased. Therefore, in the conventional semiconductor integrated circuit device, an originally good chip may be determined to be a defective product because the probing needle is not in contact with the chip.
【0005】[0005]
【課題を解決するための手段】本発明の半導体集積回路
装置は、チップ上に該半導体集積回路装置を動作させる
ための電源電極や信号を入・出力させるための信号電極
のような正規の電極の外に、ウェハチェック時のプロー
ビング針の位置ずれを検出するための、正規の電極より
面積の小さいコンタクトチェック用の電極を有してい
る。A semiconductor integrated circuit device of the present invention is a regular electrode such as a power electrode for operating the semiconductor integrated circuit device or a signal electrode for inputting / outputting a signal on a chip. In addition to the above, a contact check electrode having a smaller area than the regular electrode is provided for detecting the positional deviation of the probing needle during wafer check.
【0006】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は、本発明の第1の実施例を示す概略
平面図である。図1に示されるように、本実施例では、
半導体チップ1上には、回路に電源を供給し、信号を入
・出力させるための正規の電極2の外に、プロービング
針の接触位置をチェックするためのコンタクトチェック
用電極3がチップの対角線上に1対設けられている。こ
こで、コンタクトチェック用電極3の面積は電極2の面
積に比べて小さく形成されており、また電源電極と内部
で接続されて電源電圧が印加されるようになされてい
る。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a schematic plan view showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment,
On the semiconductor chip 1, a contact check electrode 3 for checking the contact position of the probing needle is provided on the diagonal line of the chip in addition to the regular electrode 2 for supplying power to the circuit and inputting / outputting a signal. One pair is provided. Here, the area of the contact check electrode 3 is formed smaller than the area of the electrode 2, and the contact check electrode 3 is internally connected to the power supply electrode so that the power supply voltage is applied.
【0007】今、例えば正規の電極2が100×100
μm2 、コンタクトチェック用電極3が50×50μm
2 の面積を有しているものとし、プロービング針が30
μm電極の中心からずれたとすると、電極2とプロービ
ング針は接触しているが、電極3に接触するはずのプロ
ービング針は電極からはずれ、高インピーダンス状態と
なる。針がチェック用電極3からはずれて高インピーダ
ンス状態が検出された場合には、アラームを発生させる
等してプロービング針の位置を設定し直す。Now, for example, the regular electrode 2 is 100 × 100.
μm 2 , contact check electrode 3 is 50 × 50 μm
It has an area of 2 and the probing needle is 30
If it is deviated from the center of the μm electrode, the electrode 2 and the probing needle are in contact with each other, but the probing needle that should be in contact with the electrode 3 is deviated from the electrode and a high impedance state is set. When the needle is disengaged from the checking electrode 3 and a high impedance state is detected, an alarm is generated and the position of the probing needle is reset.
【0008】ここで、コンタクトチェック用電極3がチ
ップの対角線上に2個設けられているのは、x−y方向
の位置ずればかりでなくθ方向のずれをも検知できるよ
うにするためである。The two contact check electrodes 3 are provided on the diagonal of the chip in order to detect not only the displacement in the xy direction but also the displacement in the θ direction. .
【0009】図2は、本発明の第2の実施例を示す部分
平面図である。同図に示されるように、電源電極2aか
ら導出される電源ライン4と、コンタクトチェック用電
極3との間は、第1層金属配線5、第2層金属配線6お
よびスルーホール7を介して接続されている。FIG. 2 is a partial plan view showing a second embodiment of the present invention. As shown in the figure, the power supply line 4 derived from the power supply electrode 2a and the contact check electrode 3 are provided with a first layer metal wiring 5, a second layer metal wiring 6 and a through hole 7. It is connected.
【0010】本実施例では、コンタクトチェック用電極
3を用いてプロービング針の位置ずれの検出ができる
外、この電極と電源電極2aとの間の抵抗を測定するこ
とによりスルーホール抵抗のチェックを行うことができ
る。In this embodiment, the contact check electrode 3 can be used to detect the displacement of the probing needle, and the through hole resistance is checked by measuring the resistance between this electrode and the power supply electrode 2a. be able to.
【0011】[0011]
【発明の効果】以上説明したように、本発明は、チップ
上に正規の電極の外に正規の電極より面積の狭い正規の
電極とプロービング針との間の相対的位置ずれを検出す
るためのコンタクトチェック用電極を増設したものであ
るので、本発明によれば、プロービング針がずれた場
合、プロービング針が正規の電極からはずれる前にコン
タクトチェック用電極との接触がとれなくなるようにす
ることができる。従って、本発明によれば、チェック用
電極とプロービング針との間が非接触となったときにア
ラーム等が発せられるようにすることによりプロービン
グ針の正規の電極からのはずれを未然に防止することが
でき、本来良品であるチップを不良品と判定してしまう
不都合を回避することができる。As described above, according to the present invention, in addition to the regular electrode on the chip, the relative displacement between the regular electrode having a smaller area than the regular electrode and the probing needle is detected. Since the contact check electrode is additionally provided, according to the present invention, when the probing needle is displaced, it is possible to prevent contact with the contact check electrode before the probing needle comes off the regular electrode. it can. Therefore, according to the present invention, when the check electrode and the probing needle are not in contact with each other, an alarm or the like is generated to prevent the probing needle from being separated from the regular electrode. Therefore, it is possible to avoid the inconvenience that a chip which is originally a good product is determined to be a defective product.
【図1】本発明の第1の実施例の平面図。FIG. 1 is a plan view of a first embodiment of the present invention.
【図2】本発明の第2の実施例の部分平面図。FIG. 2 is a partial plan view of the second embodiment of the present invention.
【図3】従来例の平面図。FIG. 3 is a plan view of a conventional example.
1 半導体チップ 2、2a 電極 3 コンタクトチェック用電極 4 電源ライン 5 第1層金属配線 6 第2層金属配線 7 スルーホール 1 Semiconductor Chip 2, 2a Electrode 3 Contact Check Electrode 4 Power Line 5 First Layer Metal Wiring 6 Second Layer Metal Wiring 7 Through Hole
Claims (1)
るためのあるいは信号を入・出力させるための正規の電
極が形成され、さらにこれら正規の電極よりも面積が狭
いプロービング針位置ずれ検出用電極が形成されている
半導体集積回路装置。1. A probing needle position deviation detection device having a regular electrode formed on a semiconductor substrate for applying a power supply voltage to a circuit or for inputting / outputting a signal, and having a smaller area than these regular electrodes. A semiconductor integrated circuit device in which electrodes are formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4186175A JPH065674A (en) | 1992-06-19 | 1992-06-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4186175A JPH065674A (en) | 1992-06-19 | 1992-06-19 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH065674A true JPH065674A (en) | 1994-01-14 |
Family
ID=16183706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4186175A Pending JPH065674A (en) | 1992-06-19 | 1992-06-19 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH065674A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08115958A (en) * | 1994-08-24 | 1996-05-07 | Nec Corp | Semiconductor device |
US6184569B1 (en) * | 1998-01-13 | 2001-02-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor chip inspection structures |
JP2010010197A (en) * | 2008-06-24 | 2010-01-14 | Renesas Technology Corp | Semiconductor integrated circuit device |
JPWO2021255842A1 (en) * | 2020-06-16 | 2021-12-23 |
-
1992
- 1992-06-19 JP JP4186175A patent/JPH065674A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08115958A (en) * | 1994-08-24 | 1996-05-07 | Nec Corp | Semiconductor device |
US6184569B1 (en) * | 1998-01-13 | 2001-02-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor chip inspection structures |
JP2010010197A (en) * | 2008-06-24 | 2010-01-14 | Renesas Technology Corp | Semiconductor integrated circuit device |
JPWO2021255842A1 (en) * | 2020-06-16 | 2021-12-23 | ||
WO2021255842A1 (en) * | 2020-06-16 | 2021-12-23 | 日本電信電話株式会社 | Semiconductor wafer |
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