JP2978883B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of performing highly accurate evaluation using a bonding pad regardless of the configuration of a device element is provided. SOLUTION: Bonding pads 1, 2 and 3 are electrically divided into a plurality of parts by slits 9 at the time of an electrical inspection on a semiconductor substrate before assembly, and a part 1b, 2b, 3b is electrically connected to the drain electrode pad 5, the gate electrode pad 6, and the source electrode pad 7 of the internal circuit via the fuse 8 when inspecting the electrical characteristics of the internal circuit 4. A measuring needle is brought into direct contact with each electrode to input and output signals, and the electrical characteristics of the internal circuit are inspected. At the time of assembling the device, the slits are embedded in
a, 1b, electrode pads 2a, 2b, electrode pads 3a, 3
b is repaired as one electrode pad, and the bonding pad and the electrode pad of the internal circuit 4 are bonded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device assembled after inspecting electrical characteristics on a semiconductor substrate.

[0002]

2. Description of the Related Art The capacity of semiconductor devices, especially semiconductor memory devices, is increasing rapidly, and their chip sizes are also increasing rapidly and steadily.

At present, the multilayer wiring structure is mainly used in the DRAM process, and in order to reduce the chip size, the incorporation of device elements below the upper wiring has become an issue.

In recent years, with the development of process (diffusion) technology, restrictions on the layout have increased, and one of them is to insert accessories into a chip.

Among the accessories, the one having a great influence on the layout is particularly a transistor pattern evaluation check pattern accessory, which has a dedicated pad for testing due to its nature (Japanese Unexamined Patent Publication No. Hei. 19
6536 and JP-A-4-133338).

[0005] When these dedicated pads have fulfilled their role at the time of evaluation, they become irrelevant to product functions and operations thereafter. Even if it has a pad, it is not bonded.

A technique for performing evaluation using a bonding pad without providing a dedicated evaluation pad is disclosed in JP-A-4-296038.

[0007]

By the way, Japanese Patent Application Laid-Open No.
The technique disclosed in Japanese Patent Application Laid-Open No. 296038 performs evaluation using a bonding pad connected to an external terminal for inputting an input signal or outputting an output signal as a test pad.

However, in the technique disclosed in JP-A-4-296038, a bonding pad connected to an external terminal for an input signal or an output signal is used as a test pad. May be input, and it is not always desirable to use a bonding pad coupled to an external terminal as a test pad.

Further, depending on the device element, a plurality of bonding pads may be commonly connected to an external terminal for grounding. In such a case, it is impossible to use the bonding pads as test pads. In some cases, the configuration is not applicable to all device elements.

It is an object of the present invention to provide a semiconductor device capable of performing a highly accurate evaluation irrespective of the configuration of a device element by using bonding pads necessary for product functions and operations. .

[0011]

Means for Solving the Problems] To achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a carbon dengue pad connected from the internal circuit to the outside of the semiconductor device, evaluated at electrical inspection Used as a terminal for
For this reason, a part of the bonding pad is provided with a slit so that it can be used as an integrated electrode pad when assembling the device.
It consists of two divided electrode pads, and
One of the divided electrode pads is the internal circuit to be evaluated.
It is connected to the road via a fuse .

[0012]

[0013]

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

In the figure, the semiconductor device according to the present invention is a semiconductor device having bonding pads 1, 2, and 3, and the bonding pads 1, 2, and 3 are connected to the electrode pads 5, 6, and 7 of the internal circuit 4 during assembly. Each of the bonding pads 1, 2, 3 is electrically divided into a plurality of parts at the time of an electrical inspection on the semiconductor substrate before assembly, and each of the divided bonding pads 1, 2 is bonded.
a, 1b, 2a, 2b, part 1b, 2b of 3a, 3b,
Reference numeral 3b is used as an evaluation terminal at the time of electrical inspection.

The divided evaluation terminals 1b, 2b, 3
Between the electrode b and the electrode pads 5, 6, and 7 of the internal circuit 4 to be evaluated, a fuse 8 to be trimmed at the time of assembling the device is provided as needed.

Each of the divided bonding pads 1
a, 1b, 2a, 2b, 3a and 3b are repaired as integral electrode pads at the time of assembling the device, and the repaired bonding pads 1, 2, 3 and the electrode pads 5, 6, 7 of the internal circuit 4 are connected. Bonded and electrically connected,
It is designed to be completed as a device.

Next, a specific example of the present invention will be described as an embodiment.

Embodiment 1 FIG. 1 is a configuration diagram showing a semiconductor device according to Embodiment 1 of the present invention.

In FIG. 1, an internal circuit 4 including device elements is provided on a semiconductor substrate, which is a chip base of a semiconductor device.
And bonding pads 1, 2, 3 are formed.

The bonding pads 1, 2, 3 are bonded to the electrode pads 5, 6, 7 of the internal circuit 4 at the time of assembling, and the bonding pads 1, 2, 3 according to the first embodiment of the present invention. Are electrically divided into a plurality of parts by slits 8 at the time of electrical inspection on the semiconductor substrate before assembly, and each divided bonding pad 1 is
a, 1b, 2a, 2b, part 1b, 2b of 3a, 3b,
Reference numeral 3b is used as an evaluation terminal at the time of electrical inspection.

The bonding pads 1, 2, and 3 in the first embodiment of the present invention shown in FIG. 1 are used as input electrode pads, output electrode pads, and grounding electrode pads when assembling the apparatus. At the time of the electrical inspection on the semiconductor substrate before assembly, it is electrically divided into a plurality by the slit 9 and each of the divided bonding pads 1.
a, 1b, 2a, 2b, part 1b, 2b of 3a, 3b,
Reference numeral 3b is used as a drain electrode pad, a gate electrode pad, and a source electrode pad which are evaluation terminals at the time of an electrical test.

In the first embodiment of the present invention shown in FIG.
Between the divided evaluation terminals 1b, 2b, 3b and the electrode pads 5, 6, 7 of the internal circuit 4 to be evaluated, a fuse 8 to be trimmed at the time of assembling the device is provided.

When the electrical characteristics of the internal circuit 4 are to be inspected, the drain electrode pad 5 and the gate electrode pad electrically connected to the electrode pads 5, 6, and 7 of the internal circuit 4 through the fuse 8 are used. 6. A measuring needle of a measuring device (not shown) is brought into direct contact with the source electrode pad 7 to input / output a signal and to inspect an electrical characteristic of the internal circuit 4.

After the measurement, the drain electrode pad 1b and the drain electrode 5, the gate electrode pad 2b and the gate electrode 6,
Fuse 8 is trimmed to electrically cut source electrode pad 3b and source electrode 7, respectively, and fuse 8 is cut.

By cutting the fuse 8, the drain electrode pad 1b, the gate electrode pad 2b, the source electrode pad 3b and the electrode pads 5 and 5 of the internal circuit 4 to be evaluated.
6 and 7 are electrically non-conductive.

At the time of assembling the device, the input electrode pad 1a, the drain electrode pad 1b, and the output electrode pad 2a
, The gate electrode pad 2b, the ground electrode pad 3a, and the source electrode pad 3b are respectively repaired as one electrode pad (bonding pads 1, 2, 3), and the bonding pads 1, 2, 3 and the electrode pad 5 of the internal circuit 4 are repaired. , 6,7
To complete the device.

(Embodiment 2) FIG. 2 is a configuration diagram showing a semiconductor device according to Embodiment 2 of the present invention.

The semiconductor device according to the second embodiment of the present invention shown in FIG. 2 has a structure in which two bonding pads 2 and 3 are electrically connected via a wiring 10 when completed as a device. It is assumed that.

As shown in FIG. 2, when the two bonding pads 2 and 3 are electrically connected via the wiring 10, it may hinder the inspection of the electrical characteristics of the internal circuit 4. is there.

Therefore, in the semiconductor device according to the second embodiment of the present invention shown in FIG.
3 is electrically divided into a plurality of parts by slits 8 at the time of electrical inspection on a semiconductor substrate before assembly.

As a result, each of the bonding pads 1, 2, 3 including the two bonding pads 2, 3 electrically connected via the wiring 10 is electrically disconnected from the bonding pads 1a, 1b, 2a, 2b, 3a and 3b are divided, and a part 1b, 2b and 3b is used as a drain electrode pad, a gate electrode pad and a source electrode pad which are evaluation terminals at the time of an electrical test.

In the second embodiment of the present invention shown in FIG.
The two bonding pads 2 and 3 are electrically connected via the wiring 10 at the time of assembling the device, but are separated by the slit 9 at the time of evaluation. Between 6, 7
The fuse 8 to be trimmed at the time of assembling the device is not provided, and only the fuse 8 to be trimmed at the time of assembling the device is provided between the evaluation terminal 1b and the electrode pad 5 of the internal circuit 4 to be evaluated.

In FIG. 2, when the electrical characteristics of the internal circuit 4 are inspected, the electrode pads 5 and 5 of the internal circuit 4 are checked.
A measuring needle of a measuring device (not shown) is brought into direct contact with the drain electrode pad 5, the gate electrode pad 6, and the source electrode pad 7 which are electrically connected to the drain electrodes 6 and 7 via the fuse 8, and a signal is inputted and outputted. The electrical characteristics of the circuit 4 are inspected.

After the measurement is completed, the fuse 8 is trimmed to electrically disconnect the drain electrode pad 1b and the drain electrode 5, and the fuse 8 is cut.

At the time of assembling the device, the input electrode pad 1a, the drain electrode pad 1b, and the output electrode pad 2a are embedded in the slit 9 during bonding.
, The gate electrode pad 2b, the ground electrode pad 3a, and the source electrode pad 3b are respectively repaired as one electrode pad (bonding pads 1, 2, 3), and the bonding pads 1, 2, 3 and the electrode pad 5 of the internal circuit 4 are repaired. , 6,7
To complete the device.

[0037]

As described above, according to the present invention, the bonding pad is separated from the external terminal for input signal or output signal and used as a test pad.
Input of an external noise signal from an external terminal can be avoided, and highly accurate evaluation can be performed.

Also, depending on the device element, a plurality of bonding pads may be commonly connected to an external terminal for grounding. In the case of the present invention, the bonding pads are individually separated and used as test pads. For,
Highly accurate evaluation can be performed regardless of the configuration of the device element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

 1,2,3 Bonding pad 4 Internal circuit 5,6,7 Electrode pad 8 Slit 9 Fuse

Continuation of the front page (56) References JP-A-3-196536 (JP, A) JP-A-10-12680 (JP, A) JP-A-3-211843 (JP, A) JP-A 64-86536 (JP) JP-A-2-184403 (JP, A) JP-A-10-223801 (JP, A) JP-A-2-216475 (JP, A) JP-A-3-200347 (JP, A) 7-7058 (JP, A) JP-A-2-112261 (JP, A) JP-A 1-165247 (JP, U) JP-A 60-129139 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/66 H01L 21/60 301 H01L 21/82

Claims (1)

(57) [Claims] 1. A semiconductor device having a bonding pad connected from an internal circuit to the outside of a semiconductor device , wherein a part of the bonding pad is integrated at the time of assembling the device so as to be used as an evaluation terminal during an electrical test. Divided by slits so that they can be used as
Electrode pad, and the two divided electrodes
One of the pole pads is the internal circuit and fuse to be evaluated
A semiconductor device characterized by being connected via a .