JP3245562B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP3245562B2 JP3245562B2 JP28575698A JP28575698A JP3245562B2 JP 3245562 B2 JP3245562 B2 JP 3245562B2 JP 28575698 A JP28575698 A JP 28575698A JP 28575698 A JP28575698 A JP 28575698A JP 3245562 B2 JP3245562 B2 JP 3245562B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- semiconductor integrated
- functional blocks
- dimensions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路装
置に関し、特に同一ウェハ上に動作マ−ジンを確認する
ためのテスト専用の回路を有する半導体集積回路装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a dedicated test circuit for checking an operation margin on the same wafer.
【０００２】[0002]
【従来の技術】近年、集積回路は、素子の微細化により
高集積化や高機能化がはかられてきた。この素子の微細
化に伴って、ウェハ内のチップ間の製造ばらつきが問題
となっている。特に、コスト低減の一手段としてウェハ
の大口径化が進んで、ウェハ内のチップ間の特性の均一
化は難しさを増してきたため、製造ばらつきの問題はま
すます重要課題となってきた。2. Description of the Related Art In recent years, integrated circuits have become highly integrated and highly functional due to miniaturization of elements. With the miniaturization of these elements, there is a problem of manufacturing variation between chips in a wafer. In particular, as the diameter of a wafer has been increased as a means of reducing costs, it has become more difficult to make characteristics uniform among chips in a wafer, and thus the problem of manufacturing variation has become an increasingly important issue.
【０００３】従来、機能ブロックを構成するトランジス
タ、コンタクトホ−ル、アルミ配線、スル−ホ−ル等
は、設計基準上の最小寸法のみを用いて設計されてお
り、製造プロセスの変動による製造ばらつきでトランジ
スタ、コンタクトホ−ル、アルミ配線、スル−ホ−ル等
の寸法が所望の寸法と異なって出来上がってしまった場
合でも、設計マ−ジン上許容できる範囲であれば、その
機能ブロックに電気的な不具合は生じない。すなわち、
製造ばらつきは、電気的な不具合を生じない許容できる
範囲のものであるか否かの判定が重要である。Conventionally, transistors, contact holes, aluminum wirings, through holes, etc., constituting functional blocks have been designed using only minimum dimensions according to design standards, and manufacturing variations due to manufacturing process variations. Even if the dimensions of transistors, contact holes, aluminum wiring, through-holes, etc., differ from the desired dimensions, the functional blocks will still be electrically connected if they are within the design margin. No inconvenience occurs. That is,
It is important to determine whether or not the manufacturing variation is within an allowable range that does not cause an electrical failure.
【０００４】[0004]
【発明が解決しようとする課題】従来、製造ばらつきに
よる設計寸法とのずれで生じる電気的不具合のチェッ
ク、あるいは、電気的な動作において許容できる動作マ
−ジンのチェックは、集積回路を構成する各要素単位で
行ってきた。しかしながら、そのようなチェックはより
製品に近いレベルで行うほうが望ましい。Heretofore, it has been known to check for an electrical defect caused by a deviation from a design dimension due to manufacturing variations, or to check an allowable operation margin in an electrical operation. I went on an element-by-element basis. However, it is desirable to perform such a check at a level closer to the product.
【０００５】本発明は、上述した事情に鑑みてなされた
もので、集積回路を構成する要素が組み合わさった機能
ブロックについての動作マ−ジンをチェックすることが
可能な半導体集積回路装置を提供する事を目的とする。The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit device capable of checking an operation margin of a functional block in which elements constituting an integrated circuit are combined. For the purpose.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
の本発明は、以下の構成を採用した。To achieve the above object, the present invention employs the following constitution.
【０００７】請求項１に記載の半導体集積回路装置は、
集積回路に搭載された機能ブロックの設計基準の最小寸
法を比例縮小した、集積回路の寸法に対する動作マージ
ンを確認するために動作の良・不良判定を行うことがで
きる複数の機能ブロックが、前記集積回路とは別に同一
ウェハ上に形成されていることを特徴とする。[0007] The semiconductor integrated circuit device according to claim 1 is
Operational merging of integrated circuit dimensions by proportionally reducing the minimum design criteria of the functional blocks mounted on the integrated circuit
Good / bad operation can be determined to confirm
A plurality of functional blocks are formed on the same wafer separately from the integrated circuit.
【０００８】この半導体集積回路装置では、集積回路に
搭載された機能ブロックの設計基準で定められた最小寸
法を比例縮小して設計された機能ブロックについて、そ
の動作の良・不良判定を行うことにより、集積回路の寸
法に対する動作マ−ジンを確認できる。そうして得られ
た動作マ−ジンのデ−タから、集積回路中の電気的な不
具合の原因となる部位を検出することが可能になる。こ
の場合の動作マ−ジンのデ−タは、集積回路を構成する
要素についてのものではなく、その要素を組み合わせた
機能ブロックについてのものであり、より集積回路に近
いレベルでのものなので有益である。In this semiconductor integrated circuit device, for a functional block designed by proportionally reducing the minimum dimension defined by the design standard of the functional block mounted on the integrated circuit, the operation of the functional block is judged as good or bad. The operation margin for the dimensions of the integrated circuit can be confirmed. From the data of the operation margin obtained in this way, it becomes possible to detect a portion of the integrated circuit that causes an electrical failure. The data of the operation margin in this case is not about the elements constituting the integrated circuit, but about the functional blocks in which the elements are combined, and is useful at the level closer to the integrated circuit. is there.
【０００９】[0009]
【発明の実施の形態】以下、本発明に係る半導体集積回
路装置の好適な実施の形態を図１を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a semiconductor integrated circuit device according to the present invention will be described below with reference to FIG.
【００１０】図１は、本発明に係る半導体集積回路装置
の概念図である。この半導体集積回路装置１では、集積
回路２とは別に同一ウェハ上に、その集積回路２に搭載
された機能ブロックの設計基準の最小寸法を比例縮小し
た機能ブロック３、４、５、・・・が形成されている。
この機能ブロック３、４、５、・・・１を構成するトラ
ンジスタ、コンタクトホ−ル、アルミ配線、スル−ホ−
ル等の寸法は、設計基準で定められた最小寸法を比例縮
小して設計されている。例えば、最小寸法の０．９５
倍、０．９倍、０．８５倍、・・・の複数の寸法で設計
されたものである。FIG. 1 is a conceptual diagram of a semiconductor integrated circuit device according to the present invention. In this semiconductor integrated circuit device 1, on the same wafer as the integrated circuit 2, on the same wafer, the functional blocks 3, 4, 5,. Are formed.
The transistors, contact holes, aluminum wiring, through-holes constituting the functional blocks 3, 4, 5,...
The dimensions such as the size are designed to be proportionally reduced from the minimum dimensions determined by the design standards. For example, the minimum dimension of 0.95
.., 0.95, 0.85,...
【００１１】機能ブロック３、４、５、・・・は、集積
回路２に搭載された機能ブロックの設計基準の最小寸法
を比例縮小したものなので、集積回路の寸法に対する動
作マ−ジンを確認することができる。各機能ブロック
３、４、５、・・・は、それぞれに入力端子６、６、
６、・・・および出力端子７、７、７、・・・を有して
おり、それぞれに対して電気的動作のチェックを行い、
良・不良判定を行う。そうして、寸法の異なる機能ブロ
ックごとに電気的動作がチェックされるので、集積回路
における寸法に対する動作マ−ジンを確認できる。Since the functional blocks 3, 4, 5,... Are obtained by proportionally reducing the design standard minimum dimensions of the functional blocks mounted on the integrated circuit 2, the operation margin for the dimensions of the integrated circuit is confirmed. be able to. Each of the functional blocks 3, 4, 5,... Has an input terminal 6, 6,.
.. And output terminals 7, 7, 7,...
Perform good / bad judgment. Thus, the electrical operation is checked for each of the functional blocks having different dimensions, so that the operation margin for the dimensions in the integrated circuit can be confirmed.
【００１２】[0012]
【発明の効果】以上詳細に説明したように、本発明に半
導体集積回路装置によれば、以下のような効果を奏す
る。As described above in detail, according to the semiconductor integrated circuit device of the present invention, the following effects can be obtained.
【００１３】請求項１に記載の半導体集積回路装置によ
れば、集積回路に搭載された機能ブロックの設計基準の
最小寸法を比例縮小した複数の機能ブロックが、前記集
積回路とは別に同一ウェハ上に形成されているので、そ
れら複数の機能ブロックについてその動作の良・不良判
定を行うことにより、集積回路の寸法に対する動作マ−
ジンを確認できるという効果が得られる。そうして得ら
れた動作マ−ジンのデ−タから、集積回路中の電気的な
不具合の原因となる部位を検出することが可能になると
いう効果が得られる。According to the semiconductor integrated circuit device of the first aspect, a plurality of functional blocks in which the minimum dimensions of the design criteria of the functional blocks mounted on the integrated circuit are proportionally reduced are provided on the same wafer separately from the integrated circuit. By determining whether the operation of each of the plurality of functional blocks is good or bad, the operation block for the dimensions of the integrated circuit is determined.
The effect that the gin can be confirmed is obtained. From the data of the operation margin obtained in this way, it is possible to detect an area in the integrated circuit that causes an electrical failure.
【図１】 本発明に係る実施形態の半導体集積回路装置
の概念図である。FIG. 1 is a conceptual diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.
１ 半導体集積回路装置 ２ 集積回路 ３ 機能ブロック DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Integrated circuit 3 Function block
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/66 G01R 31/28 H01L 21/822 H01L 27/04 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/66 G01R 31/28 H01L 21/822 H01L 27/04
Claims (1)
計基準の最小寸法を比例縮小した、集積回路の寸法に対
する動作マージンを確認するために動作の良・不良判定
を行うことができる複数の機能ブロックが、前記集積回
路とは別に同一ウェハ上に形成されていることを特徴と
する半導体集積回路。1. A method for reducing the size of an integrated circuit, in which the minimum dimension of a design standard of a functional block mounted on the integrated circuit is proportionally reduced .
Good / bad operation to check the operating margin
A plurality of functional blocks capable of performing the steps are formed on the same wafer separately from the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28575698A JP3245562B2 (en) | 1998-10-07 | 1998-10-07 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28575698A JP3245562B2 (en) | 1998-10-07 | 1998-10-07 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000114336A JP2000114336A (en) | 2000-04-21 |
| JP3245562B2 true JP3245562B2 (en) | 2002-01-15 |
Family
ID=17695655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28575698A Expired - Fee Related JP3245562B2 (en) | 1998-10-07 | 1998-10-07 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3245562B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115101509B (en) * | 2022-08-25 | 2022-11-11 | 合肥新晶集成电路有限公司 | Wafer structure and chip yield detection method |
-
1998
- 1998-10-07 JP JP28575698A patent/JP3245562B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000114336A (en) | 2000-04-21 |
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