JPH05264676A - Method and device for detecting fault - Google Patents

Abstract

PURPOSE:To detect a bridge fault between wirings without adding a fault detecting circuit by determining input logical values for making logical values 1 and 0, respectively, to the combination of the wirings having the possibility of bridge fault, and applying them to an inspection target to measure power source current. CONSTITUTION:For example, adjacent wirings 1, 2, wirings 2, 3 are extracted as those having the possibility of causing a bridge fault between wirings, and input logical patterns for making the logical values to the combinations of the wirings 1 and 0, respectively, are determined by a logical pattern generator 15, and applied to an IC/LSI of an inspection target. The power source current supplied to the IC/LSI is measured 16 and compared with the power source current of the normal IC/LSI containing no bridge fault, whereby the bridge fault between the wirings 1-3 of the IC/LSI of the inspection target is detected. Since the outflow of the power source current from power source to ground is increased when the bridge fault is caused, the fault can be easily detected.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a manufactured IC / LSI.
The present invention relates to failure detection for detecting the presence or absence of manufacturing defects when testing the.

[0002]

2. Description of the Related Art Conventionally, in order to inspect a manufactured IC / LSI for manufacturing defects, especially for completely detecting a bridge between wirings, there is a method of manually creating an input pattern. There is a method called a cross-check method, in which an inspection circuit is preliminarily formed in an IC / LSI in a grid pattern and an inspection circuit is used to inspect with a test pattern automatically obtained by a computer.

FIG. 5 is a circuit configuration diagram showing an example in which a testing circuit is preliminarily built in an IC / LSI in a grid pattern in order to detect a bridging fault between wiring lines. Figure 5
With the circuit configuration as shown in (1), a signal at an arbitrary point where the probe line 21 and the sense line 22 intersect inside the IC / LSI can be observed.

In order to detect a bridging fault between wirings in FIG. 5, first, an inverted value (logical value 1 to logical value 0) is set for two wirings that are considered to have a bridging fault. Such an input pattern is supplied to the IC / LSI. Next, by simultaneously observing the signal values of the two wirings, the bridging fault between the wirings can be detected.

[0005]

Since the conventional failure detection method is constructed as described above, the IC is previously prepared.
A circuit for inspection has to be built in the inside of the / LSI, and a wasteful circuit that is not used in the actual operation is required, and there is a problem that the actually used area is reduced.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a failure detection method or apparatus for detecting a bridge failure between wirings without making an inspection circuit in advance. And

[0007]

A fault detecting method according to the present invention comprises a step of extracting an adjacent wiring in which a bridge may occur from a semiconductor layout pattern, and an input logic in which the adjacent wiring is a combination of logical values 1 and 0. A step of obtaining a value and a step of adding the input logical value for detecting a failure and comparing the current consumption value at that time with the current consumption value at the normal time are provided. Alternatively, as a failure detection device, a pattern generator that gives an input logic value in which adjacent wiring that may cause a bridge has a logic value of 1 and 0 level, and a current measuring device that measures current consumption when the input logic value is added are provided. It was

[0008]

In the fault detecting method according to the present invention, the wiring is set to the logical value 1 and the logical value 0, respectively, so that when a bridge fault occurs between the wirings, the bridge between the wirings short-circuits the power supply and the ground to penetrate the wiring. The current flows and the bridge is detected.

[0009]

【Example】

Example 1. Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a flow chart showing each means constituting a failure detection method according to the present invention. FIG. 2 is a designed logic circuit diagram which is an example of an inspection target. Figure 3
It is the figure which showed the layout pattern of this actually used logic circuit. Further, FIG. 4 is a diagram for explaining the connections when actually inspecting the logic circuits of FIGS. 2 and 3.
The specific processing procedure will be described below according to the flow chart shown in FIG.
An example of detecting a failure will be described with reference to FIGS.

First, from the layout pattern data, adjacent wirings on the pattern are extracted as a combination of wirings which may cause a bridge failure between the wirings (step S1). Specifically, in the case of the layout pattern data of FIG. 3, since the wiring 1 and the wiring 2 are adjacent to each other and the wiring 2 and the wiring 3 are also adjacent to each other, a combination of these wirings is described as “wiring 1 and wiring 2”. , And “wiring 2 and wiring 3” are extracted as those in which a bridging failure between wirings may occur.

Next, based on the wiring combinations extracted in step S1, an input logic pattern (combination of logic 1 and 0) for setting the wiring combinations to a logical value of 1 and a logical value of 0 is derived (step). S2). The layout pattern data shown in FIG. 3 is a layout of the logic circuit diagram shown in FIG. 2, and the respective wirings correspond to each other. In the logic circuit diagram shown in FIG. 2, input logic patterns for setting "wiring 1 and wiring 2" and "wiring 2 and wiring 3" to logical values 1 and 0, respectively, are obtained. Several algorithms for obtaining this logical pattern have already been published. For example, the input logic pattern for setting “wiring 1 and wiring 2” to the logical value 1 and the logical value 0, respectively, is the input terminal A
Is a logical value 0, the input terminal B is a logical value 0, and the input terminal C is a logical value 1. Further, in order to set the "wiring 2 and the wiring 3" to the logical value 1 and the logical value 0, respectively, the input terminal C is
The logical value of the input terminal D should be 1.

When inspecting the manufactured IC / LSI, the connection shown in FIG. 4 is performed, and the input logic pattern (combination of input logic values) as in the above example obtained in step S2 of FIG.
Is applied by the input logical value (logical pattern) generator 15. At that time, the power supply current supplied to the IC / LSI to be inspected is measured by the power supply current measuring device 16 and compared with the power supply current of a normal IC / LSI which does not include a bridging fault, so that the IC / LSI to be inspected It is possible to detect a bridging fault between the wirings of the LSI (step S3). If the bridge is generated, the outflow of the power supply current from the power supply to the ground is suppressed, which facilitates detection.

Embodiment 2. Although the example of the failure detection method has been described in the first embodiment, a semiconductor mounted logic circuit inspecting apparatus having the same concept will be described below. FIG. 4 is also a block diagram showing such an inspection device, which is composed of 15 input logic value generators, 16 power supply current measuring devices, and 17 semiconductor inspection jigs. This operation is as follows. An input logic value, which is obtained in advance, and in which the wiring in which the bridge is likely to occur is logic 1 and 0, is added to the object to be inspected by the input logic value generator 15, and the current is measured by the power supply current measuring device 16. For example, it is possible to make an automatic comparison with a previously obtained normal current.

[0014]

As described above, according to the present invention, a combination of wirings having a possibility of a bridging failure between the wirings is extracted, and the input logical value is set to logical value 0 and logical value 1 for the combination. The power supply current is measured by applying the logical value to the IC / LSI at the time of the bridge fault inspection. Therefore, the circuit for fault detection is not added to the fault detection target IC / LSI, This has the effect of being able to detect a bridging fault.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention.

FIG. 2 is a logic circuit diagram which is an example of a failure detection target.

FIG. 3 is a diagram showing a layout pattern of a logic circuit of the embodiment.

FIG. 4 is a connection diagram at the time of inspection according to the embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a conventional method.

[Explanation of symbols]

 1-9 wiring 10-13 element 14 DC power supply 15 logic pattern generator 16 power supply current measuring device 17 IC / LSI inspection jig 18 inspection target IC / LSI

Claims (2)

[Claims] 1. A step of extracting an adjacent wiring in which a bridge may occur from a semiconductor layout pattern, a step of obtaining an input logical value in which the adjacent wiring is a combination of logical values 1 and 0, and the input for detecting a failure. A failure detection method comprising a step of adding a logical value and comparing a current consumption value at that time with a current consumption value at a normal time. 2. An adjacent wiring in which a bridge may occur is extracted from a layout pattern of a semiconductor, an input logical value in which the adjacent wiring is a combination of logical values 1 and 0 is obtained, and the obtained input logical value is used for detecting a failure. A failure detection device that includes a pattern generator that adds a current consumption value when the input logic value is added, and a current measuring device that measures a current consumption value when the input logical value is added.