JPH05264676A - Method and device for detecting fault - Google Patents
Method and device for detecting faultInfo
- Publication number
- JPH05264676A JPH05264676A JP4064941A JP6494192A JPH05264676A JP H05264676 A JPH05264676 A JP H05264676A JP 4064941 A JP4064941 A JP 4064941A JP 6494192 A JP6494192 A JP 6494192A JP H05264676 A JPH05264676 A JP H05264676A
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- lsi
- fault
- value
- bridge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は製造されたIC/LSI
をテストする際、製造上の欠陥の有無を検出する故障検
出に関するものである。The present invention relates to a manufactured IC / LSI.
The present invention relates to failure detection for detecting the presence or absence of manufacturing defects when testing the.
【0002】[0002]
【従来の技術】従来、製造されたIC/LSIに製造上
の欠陥、特に配線間のブリッジを完全に検出するための
検査を行うためには、人手により検査を行う入力パター
ンを作成する方法か、またはクロスチェック法と呼ばれ
る、あらかじめIC/LSI内に格子状に検査用の回路
を作り込み、その回路を利用して計算機により自動的に
求めたテストパターンで検査する方法がある。2. Description of the Related Art Conventionally, in order to inspect a manufactured IC / LSI for manufacturing defects, especially for completely detecting a bridge between wirings, there is a method of manually creating an input pattern. There is a method called a cross-check method, in which an inspection circuit is preliminarily formed in an IC / LSI in a grid pattern and an inspection circuit is used to inspect with a test pattern automatically obtained by a computer.
【0003】図5は従来の配線間のブリッジ故障を検出
するために、あらかじめIC/LSI内に格子状に検査
用の回路を作り込んだ例を示す回路構成図である。図5
に示すような回路構成をとると、IC/LSIの内部に
おけるプローブライン21とセンスライン22の交差す
る任意の点の信号を観測することができる。FIG. 5 is a circuit configuration diagram showing an example in which a testing circuit is preliminarily built in an IC / LSI in a grid pattern in order to detect a bridging fault between wiring lines. Figure 5
With the circuit configuration as shown in (1), a signal at an arbitrary point where the probe line 21 and the sense line 22 intersect inside the IC / LSI can be observed.
【0004】図5において配線間のブリッジ故障の検出
を行うためには、まずブリッジ故障が発生していると思
われる2つの配線に対して反転値(論理値1に対して論
理値0)となるような入力パターンをIC/LSIに供
給する。次にその2つの配線の信号値を同時に観測する
ことにより配線間のブリッジ故障は検出できる。In order to detect a bridging fault between wirings in FIG. 5, first, an inverted value (logical value 1 to logical value 0) is set for two wirings that are considered to have a bridging fault. Such an input pattern is supplied to the IC / LSI. Next, by simultaneously observing the signal values of the two wirings, the bridging fault between the wirings can be detected.
【0005】[0005]
【発明が解決しようとする課題】従来の故障検出方法
は、上記のように構成されていたので、あらかじめIC
/LSI内部に検査用の回路を格子状に作り込まなけれ
ばならず、実際の動作には使用しない無駄な回路が要
り、実使用面積が減るという課題があった。Since the conventional failure detection method is constructed as described above, the IC is previously prepared.
A circuit for inspection has to be built in the inside of the / LSI, and a wasteful circuit that is not used in the actual operation is required, and there is a problem that the actually used area is reduced.
【0006】本発明は上記のような課題を解決するため
になされたもので、あらかじめ検査用の回路を作り込む
ことなく配線間のブリッジ故障を検出する故障検出方法
または装置を提供することを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a failure detection method or apparatus for detecting a bridge failure between wirings without making an inspection circuit in advance. And
【0007】[0007]
【課題を解決するための手段】本発明に係わる故障検出
方法は、半導体のレイアウトパターンからブリッジが起
こり得る隣接配線を抽出するステップと、この隣接配線
が論理値1と0の組み合わせになる入力論理値を求める
ステップと、故障検出のために上記入力論理値を加え
て、その時の消費電流値を正常時の消費電流値と比較す
るステップを備えた。または故障検出装置として、ブリ
ッジが起こり得る隣接配線が論理値1と0レベルになる
入力論理値を与えるパターン発生器と、この入力論理値
を加えた時の消費電流を測定する電流測定器を設けた。A fault detecting method according to the present invention comprises a step of extracting an adjacent wiring in which a bridge may occur from a semiconductor layout pattern, and an input logic in which the adjacent wiring is a combination of logical values 1 and 0. A step of obtaining a value and a step of adding the input logical value for detecting a failure and comparing the current consumption value at that time with the current consumption value at the normal time are provided. Alternatively, as a failure detection device, a pattern generator that gives an input logic value in which adjacent wiring that may cause a bridge has a logic value of 1 and 0 level, and a current measuring device that measures current consumption when the input logic value is added are provided. It was
【0008】[0008]
【作用】本発明における故障検出方法は、その配線をそ
れぞれ論理値1と論理値0にすることにより、配線間の
ブリッジ故障が発生した場合、その配線間のブリッジに
より電源とグラウンドが短絡し貫通電流がながれてブリ
ッジが検出される。In the fault detecting method according to the present invention, the wiring is set to the logical value 1 and the logical value 0, respectively, so that when a bridge fault occurs between the wirings, the bridge between the wirings short-circuits the power supply and the ground to penetrate the wiring. The current flows and the bridge is detected.
【0009】[0009]
実施例1.以下、本発明をその実施例を図に基づき具体
的に説明する。図1は本発明に係わる故障検出方法を構
成する各手段を表すフロー図である。また、図2は検査
対象の一例である設計した論理回路図である。図3は、
この実際に使われる論理回路のレイアウトパターンを示
した図である。さらに図4は、この図2、図3の論理回
路を、実際に検査する場合の接続を説明する図である。
以下具体的な処理手順を図1に示すフロー図に従って、
図2ないし図4を用いて故障検出を行う例について説明
する。Example 1. Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a flow chart showing each means constituting a failure detection method according to the present invention. FIG. 2 is a designed logic circuit diagram which is an example of an inspection target. Figure 3
It is the figure which showed the layout pattern of this actually used logic circuit. Further, FIG. 4 is a diagram for explaining the connections when actually inspecting the logic circuits of FIGS. 2 and 3.
The specific processing procedure will be described below according to the flow chart shown in FIG.
An example of detecting a failure will be described with reference to FIGS.
【0010】まずレイアウトパターンデータから、パタ
ーン上で隣接する配線を配線間のブリッジ故障の発生す
る可能性のある配線の組み合わせとして抽出する(ステ
ップS1)。具体的には、図3のレイアウトパターンデ
ータの場合なら、配線1と配線2が隣接しており、また
配線2と配線3も隣接しているためこれらの配線の組み
合わせ、「配線1と配線2」、「配線2と配線3」を配
線間のブリッジ故障が発生する可能性があるものとして
抽出する。First, from the layout pattern data, adjacent wirings on the pattern are extracted as a combination of wirings which may cause a bridge failure between the wirings (step S1). Specifically, in the case of the layout pattern data of FIG. 3, since the wiring 1 and the wiring 2 are adjacent to each other and the wiring 2 and the wiring 3 are also adjacent to each other, a combination of these wirings is described as “wiring 1 and wiring 2”. , And “wiring 2 and wiring 3” are extracted as those in which a bridging failure between wirings may occur.
【0011】次にステップS1で抽出した配線の組み合
わせに基づき、それらの配線の組み合わせをそれぞれ論
理値1と論理値0にするための入力論理パターン(論理
1、0の組み合わせ)を導出する(ステップS2)。図
3に示すレイアウトパターンデータは、図2に示す論理
回路図をレイアウトしたものであり、それぞれの配線は
対応している。図2に示す論理回路図で「配線1と配線
2」、「配線2と配線3」をそれぞれ論理値1と論理値
0にするための入力論理パターンを求める。この論理パ
ターンを求めるアルゴリズムは既に幾つか公表されてい
る。例えば、「配線1と配線2」をそれぞれ論理値1と
論理値0にするための入力論理パターンは、入力端子A
を論理値0、入力端子Bを論理値0、入力端子Cを論理
値1とする。また「配線2と配線3」をそれぞれ論理値
1と論理値0にするためには、入力端子Cは上記入力、
入力端子Dを論理値1にすればよい。Next, based on the wiring combinations extracted in step S1, an input logic pattern (combination of logic 1 and 0) for setting the wiring combinations to a logical value of 1 and a logical value of 0 is derived (step). S2). The layout pattern data shown in FIG. 3 is a layout of the logic circuit diagram shown in FIG. 2, and the respective wirings correspond to each other. In the logic circuit diagram shown in FIG. 2, input logic patterns for setting "wiring 1 and wiring 2" and "wiring 2 and wiring 3" to logical values 1 and 0, respectively, are obtained. Several algorithms for obtaining this logical pattern have already been published. For example, the input logic pattern for setting “wiring 1 and wiring 2” to the logical value 1 and the logical value 0, respectively, is the input terminal A
Is a logical value 0, the input terminal B is a logical value 0, and the input terminal C is a logical value 1. Further, in order to set the "wiring 2 and the wiring 3" to the logical value 1 and the logical value 0, respectively, the input terminal C is
The logical value of the input terminal D should be 1.
【0012】製造されたIC/LSIを検査する場合は
図4の接続を行い、図1のステップS2で求めた上記例
のような入力論理パターン(入力論理値の組み合わせ)
を入力論理値(論理パターン)発生器15により印加す
る。その際、検査対象のIC/LSIに供給している電
源電流を電源電流測定器16で測定し、ブリッジ故障を
含まない正常なIC/LSIの電源電流と比較すること
により、検査対象のIC/LSIの配線間のブリッジ故
障を検出することができる(ステップS3)。ブリッジ
が発生していれば、それにより電源からグラウンドへの
電源電流の流出がふえるので検出が容易である。When inspecting the manufactured IC / LSI, the connection shown in FIG. 4 is performed, and the input logic pattern (combination of input logic values) as in the above example obtained in step S2 of FIG.
Is applied by the input logical value (logical pattern) generator 15. At that time, the power supply current supplied to the IC / LSI to be inspected is measured by the power supply current measuring device 16 and compared with the power supply current of a normal IC / LSI which does not include a bridging fault, so that the IC / LSI to be inspected It is possible to detect a bridging fault between the wirings of the LSI (step S3). If the bridge is generated, the outflow of the power supply current from the power supply to the ground is suppressed, which facilitates detection.
【0013】実施例2.実施例1では故障検出方法の例
を説明したが、以下に同様の考えの半導体搭載の論理回
路の検査装置について説明する。図4はこうした検査装
置をも表す構成図で、検査装置は、15の入力論理値発
生器、16の電源電流測定器、17の半導体検査治具で
構成される。この動作は次のようになる。予め求めてお
いたブリッジが発生し易い配線が論理1と0になる入力
論理値を、入力論理値発生器15により被検査対象に加
え、電源電流測定器16の部分で電流測定する。予め求
めておいた正常時の電流と、例えば自動比較が可能であ
る。Embodiment 2. Although the example of the failure detection method has been described in the first embodiment, a semiconductor mounted logic circuit inspecting apparatus having the same concept will be described below. FIG. 4 is also a block diagram showing such an inspection device, which is composed of 15 input logic value generators, 16 power supply current measuring devices, and 17 semiconductor inspection jigs. This operation is as follows. An input logic value, which is obtained in advance, and in which the wiring in which the bridge is likely to occur is logic 1 and 0, is added to the object to be inspected by the input logic value generator 15, and the current is measured by the power supply current measuring device 16. For example, it is possible to make an automatic comparison with a previously obtained normal current.
【0014】[0014]
【発明の効果】以上のように本発明によれば、配線間の
ブリッジ故障の可能性のある配線の組み合わせを抽出
し、その組み合わせに対してそれぞれ論理値0と論理値
1にする入力論理値を求め、その論理値をブリッジ故障
検査時にIC/LSIに印加して、電源電流を測定する
ようにしたので、故障検出対象のIC/LSIに故障検
出用の回路を追加することなく、配線間のブリッジ故障
を検出することができる効果がある。As described above, according to the present invention, a combination of wirings having a possibility of a bridging failure between the wirings is extracted, and the input logical value is set to logical value 0 and logical value 1 for the combination. The power supply current is measured by applying the logical value to the IC / LSI at the time of the bridge fault inspection. Therefore, the circuit for fault detection is not added to the fault detection target IC / LSI, This has the effect of being able to detect a bridging fault.
【図1】本発明の実施例を示すフロー図である。FIG. 1 is a flow chart showing an embodiment of the present invention.
【図2】故障検出対象の一例である論理回路図である。FIG. 2 is a logic circuit diagram which is an example of a failure detection target.
【図3】実施例の論理回路のレイアウトパターンを示し
た図である。FIG. 3 is a diagram showing a layout pattern of a logic circuit of the embodiment.
【図4】本発明の実施例の検査の際の接続図である。FIG. 4 is a connection diagram at the time of inspection according to the embodiment of the present invention.
【図5】従来の方法を示す回路構成図である。FIG. 5 is a circuit configuration diagram showing a conventional method.
1〜9 配線 10〜13 素子 14 直流電源 15 論理パターン発生器 16 電源電流測定器 17 IC/LSI検査用治具 18 検査対象IC/LSI 1-9 wiring 10-13 element 14 DC power supply 15 logic pattern generator 16 power supply current measuring device 17 IC / LSI inspection jig 18 inspection target IC / LSI
Claims (2)
ジが起こり得る隣接配線を抽出するステップと、 上記隣接配線が論理値1と0の組み合わせになる入力論
理値を求めるステップと、 故障検出のために上記入力論理値を加え、その時の消費
電流値を正常時の消費電流値と比較するステップを備え
た故障検出方法。1. A step of extracting an adjacent wiring in which a bridge may occur from a semiconductor layout pattern, a step of obtaining an input logical value in which the adjacent wiring is a combination of logical values 1 and 0, and the input for detecting a failure. A failure detection method comprising a step of adding a logical value and comparing a current consumption value at that time with a current consumption value at a normal time.
ジが起こり得る隣接配線を抽出し、上記隣接配線が論理
値1と0の組み合わせになる入力論理値を求め、故障検
出のために上記求めた入力論理値を加えるパターン発生
器を設け、 また上記入力論理値を加えた時の消費電流値を測定する
電流測定器を設け、 上記測定電流値を正常時の消費電流値と比較する故障検
出装置。2. An adjacent wiring in which a bridge may occur is extracted from a layout pattern of a semiconductor, an input logical value in which the adjacent wiring is a combination of logical values 1 and 0 is obtained, and the obtained input logical value is used for detecting a failure. A failure detection device that includes a pattern generator that adds a current consumption value when the input logic value is added, and a current measuring device that measures a current consumption value when the input logical value is added.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4064941A JP2966185B2 (en) | 1992-03-23 | 1992-03-23 | Failure detection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4064941A JP2966185B2 (en) | 1992-03-23 | 1992-03-23 | Failure detection method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05264676A true JPH05264676A (en) | 1993-10-12 |
JP2966185B2 JP2966185B2 (en) | 1999-10-25 |
Family
ID=13272566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4064941A Expired - Fee Related JP2966185B2 (en) | 1992-03-23 | 1992-03-23 | Failure detection method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2966185B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7120890B2 (en) | 2002-10-28 | 2006-10-10 | Kabushiki Kaisha Toshiba | Apparatus for delay fault testing of integrated circuits |
JP2006317398A (en) * | 2005-05-16 | 2006-11-24 | Sharp Corp | Semiconductor integrated circuit and test method of product loading the semiconductor integrated circuit |
US7538558B2 (en) | 2006-03-24 | 2009-05-26 | Nec Electronics Corporation | Failure detection apparatus and failure detection method for a semiconductor apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0442923A (en) * | 1990-06-07 | 1992-02-13 | Oki Electric Ind Co Ltd | Formation of wiring pattern of semiconductor device |
-
1992
- 1992-03-23 JP JP4064941A patent/JP2966185B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0442923A (en) * | 1990-06-07 | 1992-02-13 | Oki Electric Ind Co Ltd | Formation of wiring pattern of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7120890B2 (en) | 2002-10-28 | 2006-10-10 | Kabushiki Kaisha Toshiba | Apparatus for delay fault testing of integrated circuits |
JP2006317398A (en) * | 2005-05-16 | 2006-11-24 | Sharp Corp | Semiconductor integrated circuit and test method of product loading the semiconductor integrated circuit |
US7538558B2 (en) | 2006-03-24 | 2009-05-26 | Nec Electronics Corporation | Failure detection apparatus and failure detection method for a semiconductor apparatus |
Also Published As
Publication number | Publication date |
---|---|
JP2966185B2 (en) | 1999-10-25 |
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