JP2000088914A - Method for testing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for testing a semiconductor integrated circuit device capable of screening according to a power source current at the time of standing still. SOLUTION: The method for testing a semiconductor integrated circuit device 1 comprises the steps of measuring a power source current at the time of standing still in two or more logic combination states of the device 1, measuring a maximum value Imax of the current and a minimum value Imin of the current by a current measuring unit 12 of a semiconductor integrated circuit device (IC tester) 10, and calculating a difference Id = ImaxImin of the value Imax and the value Imin of the current by a CPU 15 via an A-D converter 13. As a result, if the difference Id exceeds a threshold value by comparing the difference with a predetermined value (threshold value) (for example, 10 μA) previously stored in a memory 14, the device 1 is decided to be a fault in the screening.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to the measurement and selection (screening) of a semiconductor integrated circuit device.
g) Method.

[0002]

2. Description of the Related Art Conventionally, it has been difficult to create a functional test program covering all nodes in an LSI circuit when selecting non-defective products of a semiconductor integrated circuit device. It is better if you have achieved it. When the power supply current at rest is measured in multiple logical combination states to compensate for the shortage of the fault detection rate, a normal logic circuit does not flow a finite current by design and only leak current flows. Is measured, it indicates that there is a defective portion in the corresponding LSI, and even if it is a non-defective product as a function test, L which causes a defect in reliability
It is effective for screening SI.

[0003]

However, the above screening method cannot be applied to an LSI designed to allow a steady power supply current to flow even when the circuit is at rest. It is an object of the present invention to provide a test method of a semiconductor integrated circuit device capable of screening by a power supply current when the conventional circuit is designed to allow a steady power supply current to flow even when the circuit is stationary. .

[0004]

According to the present invention, there is provided a method for testing a semiconductor integrated circuit device, comprising the steps of: measuring a power supply current at rest in a plurality of logical combination states; The maximum value and the minimum value of the current are calculated, and the static leakage current other than where the steady current flows is measured based on the difference between the maximum value and the minimum value.

[2] In the test method for a semiconductor integrated circuit device according to the above [1], the power supply current at the time of rest is measured a plurality of times within a cycle of a commercial power supply frequency, and is obtained by calculating an average. It was done. Therefore,
The effect of noise caused by the commercial frequency can be eliminated.

[0006]

Embodiments of the present invention will be described below in detail. FIG. 1 shows a first embodiment of the present invention.
FIG. 1 is a schematic configuration diagram of an SI test system. In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device (test device) comprising a plurality of logic combination circuits, which is provided with a power supply Vcc terminal 2, logic terminals 3, 4, 5, a GND terminal 6, and the like.

A semiconductor integrated circuit device test apparatus (IC)
The test device 10 includes a power supply 11, a current measuring device 12, an A /
D converter 13, memory 14, CPU (central processing unit) 15, clock circuit 16, interface circuit (I /
F) 17, a display device 18, and the like. As described above, the semiconductor integrated circuit device test apparatus 10 is connected to the semiconductor integrated circuit device 1 including a plurality of logic combination circuits.

Therefore, in the state of two or more logical combinations of the semiconductor integrated circuit device 1, the power supply current at rest is measured, and the maximum value Imax of the power supply current and the minimum value Imax of the power supply current are measured.
min is measured by the current measuring device 12 of the semiconductor integrated circuit device testing device 10, and the CP is measured via the A / D converter 13.
In U15, the difference Id = Imax-Imin between the maximum value Imax of the power supply current and the minimum value Imin of the power supply current is calculated.

As a result, if the difference Id exceeds a predetermined value (threshold) (for example, 10 μA) stored in the memory 14 and exceeds the threshold, the semiconductor integrated circuit device 1 has a screening failure. And FIG. 2 is a flowchart for screening a semiconductor integrated circuit device according to the first embodiment of the present invention.

Hereinafter, the screening method will be described in detail with reference to FIG. (1) First, the semiconductor integrated circuit device 1 and the semiconductor integrated circuit device test device 10 are connected (step S1). (2) Next, in the state of two or more logical combinations, the maximum value Imax of the power supply current at rest and the minimum value Imin of the power supply current
Is measured (step S2).

(3) Next, a difference Id between the maximum value Imax of the power supply current and the minimum value Imin of the power supply current is calculated (step S3). (4) It is checked whether the difference Id is larger than a threshold value I _TH (for example, 10 μA) (step S4). (5) If YES in step S4, display as a defective screening product on the display device 18 (step S5).

(6) If NO in step S4, a non-defective product is displayed on the display device 18 (step S6). As described above, by measuring the power supply current at rest in the state of two or more logical combinations, even if there is a path through which a steady current flows in the LSI circuit, the leakage current generated in the specific operation state is not It can be detected as a difference from a power supply current value in an operation state in which no leak current flows.

Therefore, according to this embodiment, the LSI
By detecting and removing the defective portion inside by the leak current, the mixing ratio of a potential shipping defect due to an insufficient defect detection ratio can be reduced to 1/10 or less. Next, a second embodiment of the present invention will be described. In this embodiment, in order to accurately measure the power supply current, when the commercial power supply frequency of the power supply is 50 Hz (period: 20 msec),
The power supply current is increased by 20 m by the timing circuit 16 shown in FIG.
The measurement is performed a plurality of times (for example, 50 times) within a cycle of sec, and the average is calculated.

As described above, according to the second embodiment, in addition to the effect of the first embodiment, by measuring the power supply current a plurality of times within the cycle of the commercial power supply frequency, the noise induced from the commercial power supply can be reduced. The effect can be eliminated. In the above embodiment, the leak current is detected by measuring the current value. Alternatively, the leak current may be detected by measuring the voltage and the resistance. . Needless to say, the present invention can be applied to other than the LSI.

The present invention is not limited to the above-described embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0016]

As described above, according to the present invention, the following effects can be obtained. (A) According to the first aspect of the present invention, by detecting and removing a defective portion inside the LSI by a leak current, the mixing ratio of a potential shipping defect due to an insufficient failure detection ratio is 1/10 or less. Can be (B) According to the second aspect of the invention, in addition to the effect of the above (A), the influence of induced noise from the commercial power supply is removed by measuring the power supply current a plurality of times within the cycle of the commercial power supply frequency. can do.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an LSI test system showing a first embodiment of the present invention.

FIG. 2 is a flowchart of the screening of the semiconductor integrated circuit device according to the first embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device (test device) 2 Power supply Vcc terminal 3,4,5 Logic terminal 6 GND terminal 10 Semiconductor integrated circuit device test device (IC test device) 11 Power supply 12 Current measuring device 13 A / D converter 14 Memory 15 CPU (Central Processing Unit) 16 Clock circuit 17 Interface circuit (I / F) 18 Display device

Claims (2)

[Claims] 1. A power supply current in a static state is measured in a plurality of logical combination states, a maximum value and a minimum value of the power supply current are calculated, and a constant value is calculated based on a difference between the maximum value and the minimum value. A test method for a semiconductor integrated circuit device, comprising measuring a static leakage current other than where a current flows. 2. The test method for a semiconductor integrated circuit device according to claim 1, wherein the power supply current at rest is measured a plurality of times within a cycle of a commercial power supply frequency, and is obtained by calculating an average. For testing semiconductor integrated circuit devices.