JPH11142471A - Burn-in test method and burn-in test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability and efficiently conduct a test by measuring the static power current of a device under test(DUT) during the burn-in test, storing the quality judged result and the serial number of the DUT, and selecting the DUT based on the judged result after the burn-in test. SOLUTION: A power voltage VDD is fed to a DUT1 from a power voltage feeding means 3, a test pattern is fed from a test pattern feeding means 2, and a power current IDD is generated when the DUT 1 is operated. A DUT selecting means 5 selects the DUT 1 and applies the DUT serial number information ID to it. A power current detecting means 4 detects a static power current Iddq in the internal stable state of the DUT 1. A quality judging means 6 judges the DUT 1 by comparing the detected value and the standard current value set in advance. The judged result is stored in a quality judged result storing means 7 together with the serial number ID of the DUT 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a burn-in device, and more particularly to a burn-in device having a function of measuring a quiescent power supply current (Idddq). More specifically, the present invention relates to a burn-in test method and a burn-in test apparatus used for a burn-in test performed under a high temperature condition in order to remove a CMOS type integrated circuit that causes an initial failure.

[0002]

2. Description of the Related Art In recent years, CMOS type integrated circuits have been used in various industrial fields, and high reliability is often required. The following burn-in devices are used in burn-in tests performed under high-temperature conditions to exclude CMOS integrated circuits that cause initial failure.

[0003] Generally, a static burn-in device is
It is configured by providing a thermostat, a DC power supply unit, and a power supply circuit to the device under test.

A dynamic burn-in apparatus is constructed by adding a test pattern generator for operating a device under test to the static burn-in apparatus, a driver circuit, and the like.

Further, the monitor (test) burn-in apparatus is constructed by adding a comparator circuit for monitoring (testing) whether the operation of the device under test is normal to the dynamic burn-in apparatus.

FIG. 3 shows a configuration of a burn-in device proposed as a conventional burn-in device in Japanese Patent Laying-Open No. 6-102312. Referring to FIG. 3, this conventional burn-in apparatus includes a power supply current ICC that causes a frequency of a pulse supplied from a pulse supply unit 19 to a device under test 11 to flow into the device under test 11 by a pulse supply control unit 18.
Is controlled to be a desired constant value. In the figure, reference numeral 12 denotes a power supply voltage supply means for supplying the power supply VCC to the device under test, and 13 denotes a power supply current detection means for detecting the power supply current Icc as a voltage magnitude.

Next, the quiescent power supply current (IDD quies)
The cent current (hereinafter referred to as “Iddq”) test is based on the fact that in a CMOS type integrated circuit that does not include a dynamic circuit, only a small leaf current flows in a steady state (state in which a signal is stable). , For detecting a failure inside the integrated circuit.

[0008] The advantages of the Iddq test are that the fault detection capability is high and, if the fault can be activated, it is not necessary to propagate the fault to the external terminals of the integrated circuit. Can be shortened.

[0009]

The above prior art has the following problems.

A first problem is that, in the prior art, in the case of a large-scale CMOS (logic) integrated circuit, a screen is implemented by a static burn-in device, but the screening effect is small.

The reason is that the static burn-in apparatus only applies a power supply bias to the test device or operates only a part of the circuit by inputting a pulse or the like.

Further, if a dynamic burn-in device for actually operating the internal circuit is implemented, the screening effect can be improved. However, a CMOS type integrated circuit has many very complicated patterns, and if a tester capable of processing such patterns is provided, it is necessary to attach a tester. Very expensive, and rarely used.

A second problem is that there is an Iddq test as a test for removing the initial failure of the device.
The ddq test means that the test time is long.

The reason is that when performing the Iddq test, it is necessary to perform the test after the CMOS integrated circuit enters a steady state.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a CMOS integrated circuit with improved reliability and to improve the efficiency of testing. To provide a burn-in method and apparatus.

[0016]

In order to achieve the above object, a burn-in test method according to the present invention measures a quiescent power supply current (Idddq) of a device under test during a burn-in test, and evaluates a pass / fail judgment result and a test result. A device identification number is stored, and after the burn-in test, the device under test is selected using the pass / fail judgment result.

Further, the burn-in apparatus of the present invention comprises a test pattern supply means for generating a test pattern and supplying the test pattern to the device under test, and a power supply voltage supply means for supplying a power supply voltage (VDD) to the device under test. ,
Power supply current detection means for detecting a quiescent power supply current (Idddq) flowing into the device under test from the power supply voltage supply means, and a test device selection for selecting the device under test and generating device identification number information (ID) for the device under test Means for comparing the static power supply current value detected by the power supply current detection means with a preset standard current value to determine whether the device under test is a non-defective product or a defective product; Means for storing a result of the pass / fail judgment by the means together with the device identification number information (ID) under test.

[Summary of the Invention] A burn-in apparatus according to the present invention comprises a test pattern supply means (2 in FIG. 1) for generating a test pattern and supplying the test pattern to a device under test (1 in FIG. 1). The power supply voltage (V
Power supply voltage supply means (3 in FIG. 1) for supplying DD), power supply current detection means (4 in FIG. 1) for detecting Iddq flowing into the device under test from the power supply voltage supply means,
A pass / fail determination unit (6 in FIG. 1) configured to compare the detected static power supply current value with a preset standard current value to determine whether the device under test is a good product or a bad product. .

According to the burn-in method and apparatus of the present invention, the Iddq of the device under test is measured during the burn-in test, and the device under test is selected using the pass / fail judgment result and the ID information.

As a result, a highly reliable device can be supplied by performing the Iddq test having a high fault detection capability during the burn-in test. Further, since the Iddq test having a long test time is performed during the burn-in test, the test time of the device after the burn-in test can be reduced, and an inexpensive device can be supplied.

[0021]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a preferred embodiment of the present invention. Referring to FIG. 1, in a burn-in apparatus according to a preferred embodiment of the present invention, a device under test 1 test pattern supply means 2, power supply voltage supply means 3, power supply current detection means 4, and test device selection means 5 are provided. Non-defective determining means 6 and non-defective determining result storing means 7
And

The device under test 1 is stored inside a thermostat. It is preferable that the thermostat can be maintained at, for example, 125 ° C.

The test pattern supply means 2 is a pulse generator for operating the device under test.

The power supply voltage supply means 3 is formed by a constant voltage circuit for making the power supply voltage VDD constant.

The power supply current detecting means 4 includes the device under test 1
Is an ammeter for detecting a power supply current flowing through the power supply.

The test device selecting means 5 comprises a driver circuit for sequentially selecting devices to be measured.

The pass / fail judgment means 6 is provided with a preset pass / fail judgment current value and the power supply current (I
ddq).

The pass / fail judgment result storage means 7 receives the result (data) of the pass / fail judgment means 6 and also inputs the data of the target test device from the test device selecting means 5.
Each data is stored together.

FIG. 2 is a flowchart for explaining the processing flow of the embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

(1) The power supply voltage VDD from the power supply voltage supply means 3 and the test pattern from the test pattern supply means 2 are supplied to the device under test 1 (step 201).

(2) The device under test 1 starts operating in step 201. As a result, a power supply current is generated (step 202).

(3) The device under test is selected by the test device selecting means 5, and the identification number information (ID) is set (step 203).

(4) When the selected device under test is in a stable state, the quiescent power supply current Iddq is
(Step 204).

(5) The detected power supply current Iddq is compared with the standard current and judged by the pass / fail judgment means 6 (step 205).

(6) The result of the pass / fail determination means 6 and the device under test identification number information (ID) are stored in the pass / fail determination result storage means 7 (step 206). That is, by comparing the detected Iddq value with a preset standard current value, the pass / fail determination unit 6 determines whether the device under test 1 is a good product or a bad product. Thereafter, the result determined by the pass / fail judgment means 6 is stored in the pass / fail judgment result storage means 7 together with the device under test identification number (ID).

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-mentioned embodiment of the present invention in more detail, an embodiment of the burn-in apparatus of the present invention will be described.

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a device under test, 2 denotes a test pattern supply unit that supplies a test pattern to the device under test 1, 3 denotes a power supply voltage supply unit that supplies a power supply voltage VDD to the device under test, and 4 denotes a device under test 1. Power supply current detection means for detecting the power supply current of the power supply.

Reference numeral 5 denotes pass / fail determination means for selecting the device under test 1, generating device identification number information (ID) under test, and performing pass / fail judgment of the device under test 1 on the associated unit. Reference numeral 7 denotes a pass / fail judgment result storage unit that stores the result of pass / fail judgment by the pass / fail judgment unit 6 together with the device-under-test ID information generated by the device-under-test selection unit 5.

The power supply voltage supply means 3 is formed by a constant voltage circuit for making the power supply voltage VDD constant. The voltage is 5.0
It is desirable to have a voltage accuracy of up to one digit (100 mV) below V or 3.3V.

The power supply current detecting means 4 is provided for the device under test 1.
Is an ammeter for detecting a power supply current flowing through the power supply, and is preferably capable of measuring a current of at least 1 pA.

The pass / fail judgment result storage means 7 is a memory circuit,
For example, it is composed of a DRAM or the like.

Next, the operation of one embodiment of the present invention will be described.
This will be described in detail with reference to FIG.

When the power supply voltage VDD is supplied from the power supply voltage supply means 3 to the device under test 1 and the test pattern is supplied from the test pattern supply means 2 and the device under test 1 operates, a power supply current IDD is generated. Here, the device under test is selected by the device under test selection means 5 and device identification number information (ID) is added to the device under test.

Next, the quiescent power supply current (Idddq) is detected by the power supply current detecting means 4 while the inside of the selected device under test is stabilized. By comparing the detected Iddq value with a preset standard current value, the pass / fail determination unit 6 determines whether the device under test 1 is a good product or a bad product. Thereafter, the result determined by the pass / fail determination means 6 is stored in the pass / fail determination result storage means 7 together with the device identification number (ID) under test.

[0046]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that a screening effect can be improved by removing a defective initial part by a burn-in apparatus to which an Iddq test is added. As a result, the burn-in test cost can be reduced and a highly reliable CMOS integrated circuit can be produced at low cost without using an expensive dynamic burn-in device having a tester function.

The reason is that the Iddq test used in the present invention has a high capability of detecting a failure in a CMOS type integrated circuit, particularly in a logic portion.

A second advantage of the present invention is that the screening time can be greatly reduced because the Iddq test is performed during the burn-in test. This allows
Manufacturing time and manufacturing cost can be reduced.

The reason is that, in the present invention, the Iddq test having a long measurement time can be performed during burn-in, and is unnecessary at the time of selection.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a burn-in test apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of the burn-in test apparatus according to the present invention.

FIG. 3 is a diagram showing a configuration of a conventional static burn-in test device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Device under test 2 Test pattern supply means 3 Power supply voltage supply means 4 Power supply current supply means 5 Device under test selection means 6 Pass / fail judgment means 7 Pass / fail judgment result storage means 8 Pulse supply control means 9 Pulse supply means

Claims (3)

[Claims] 1. A quiescent power supply current (Idddq) of a device under test is measured during a burn-in test, a pass / fail judgment result and an identification number of the device under test are stored, and after the burn-in test, the pass / fail judgment result is used. A burn-in test method, wherein the device under test is selected. 2. In a burn-in test, (a) a power supply voltage and a test pattern are supplied to a device under test to start operation of the device under test, and (b) a device under test is selected and identification number information (ID) is set. (C) detecting a quiescent power supply current (Idddq) when the selected device under test is in a stable state; and (d) comparing the detected power supply current (Idddq) with a standard current to determine pass / fail. (E) storing the result of the pass / fail judgment together with the identification number information (ID) of the device under test in a result storage means. 3. A test pattern supply means for generating a test pattern and supplying the test pattern to the device under test, a power supply voltage supply means for supplying a power supply voltage (VDD) to the device under test, and the power supply voltage supply means Power supply current detection means for detecting a quiescent power supply current (Idddq) flowing into the device under test from the device; test device selection means for selecting the device under test and generating device identification number information (ID) under test; A pass / fail determination means for comparing the static power supply current value detected by the current detection means with a preset standard current value to determine pass / fail of the device under test; Storing at least the test device identification number information (ID) together with the pass / fail determination result storage means. N'in apparatus.