JP4043743B2 - Semiconductor test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test apparatus for testing a semiconductor integrated circuit.
[0002]
[Prior art]
Conventionally, a shipping test has been carried out when shipping CMOS-structured semiconductor integrated circuits. There are various contents of the shipping test, and as one of them, an Iddq (Idid quiescent) test is performed. In this test, a power supply current in a stationary state of a semiconductor integrated circuit (hereinafter referred to as a “quiescent power supply current”) is measured, and pass / fail is determined based on a reference value.
[0003]
Generally, in a normally manufactured semiconductor integrated circuit, the power supply current at rest is the sum of OFF leakage currents of CMOS transistors formed on the semiconductor integrated circuit, and this value is about several μA. However, when a defect occurs in the semiconductor integrated circuit due to a defect in the manufacturing process, an abnormal current path is formed inside the semiconductor integrated circuit. In this case, the power supply current at rest is often a large value that is ten times or more than that of a normally manufactured power source. A test for judging the quality of the semiconductor integrated circuit based on the current value difference is an Iddq test.
[0004]
As an Iddq test pass / fail judgment method, the inside of the semiconductor integrated circuit is set to a constant logic state, and the power supply current at rest at that time is compared with a constant reference value for determination. By repeating this operation as necessary, it is often determined whether or not a plurality of logical states are acceptable.
[0005]
However, recent semiconductor integrated circuits tend to increase the OFF leakage current of the CMOS transistor due to the lower threshold voltage of the transistor accompanying the miniaturization of the CMOS process. At the same time, high integration is also progressing, and the power supply current at rest, which is the sum of the OFF leakage currents of the CMOS transistors, increases exponentially. As a result, in the Iddq test, the current due to the OFF leak of the semiconductor integrated circuit is equal to or more than the abnormal current due to the defect of the semiconductor integrated circuit. Furthermore, the fluctuation range of the OFF leakage current value of the semiconductor integrated circuit due to manufacturing variations often exceeds the magnitude of the abnormal current due to defects in the semiconductor integrated circuit, and it is acceptable only to compare the quiescent power supply current with a certain reference value. Judgment is difficult.
[0006]
Therefore, various methods have been devised in order to accurately perform the Iddq test even when the OFF leak of the semiconductor integrated circuit is large.
[0007]
For example, in Japanese Patent Laid-Open No. 2001-21609, the power supply current at rest is continuously measured while sequentially changing the internal state of the semiconductor integrated circuit, and whether the current value difference between the measured values is below a certain reference value. A method has been devised for determining pass / fail by failure.
[0008]
According to this method, by taking the difference in the power supply current value at rest, the OFF leak current of the semiconductor integrated circuit cancels out, and an abnormal current due to a defect in the semiconductor integrated circuit can be detected with high accuracy.
[0009]
[Problems to be solved by the invention]
However, according to the method disclosed in Japanese Patent Laid-Open No. 2001-21609, it is necessary to measure, calculate, and determine all the power supply currents at rest of the semiconductor integrated circuit in each internal state. Consider a case where a series of processing is realized by a semiconductor test apparatus for testing a normal semiconductor integrated circuit. First, in order to set an internal state, a test pattern is executed and given to a semiconductor integrated circuit from a semiconductor test apparatus. Thereafter, in order to measure the power supply current at rest, the test pattern is stopped and the measurement process is started. And it measures with an ammeter, after waiting for the electric current value to stabilize. At this time, the semiconductor test apparatus converts the current value from an analog value to a digital value so that an operation can be performed, and stores the value. By repeating this series of operations, measured values in a plurality of internal states are acquired. However, when executing or stopping a test pattern, measuring a current value, or converting a measured value into a digital value, the time required for software processing in the semiconductor test apparatus cannot be ignored, and the Iddq test is performed in an actual apparatus. One point of measurement requires about 1 millisecond, and measurement of about 1000 points takes about 1 second. Semiconductor test equipment is expensive, and therefore has a problem that it cannot be economically tested.
[0010]
In a semiconductor test apparatus, if the test can be performed without executing or stopping the test pattern every time one point is measured and without directly measuring the current value, the test time can be greatly reduced. Therefore, a means for solving the above problems is desired.
[0011]
[Means for Solving the Problems]
The present invention has been made to solve such problems.
[0012]
In the present invention (first invention), current value output means capable of outputting a current value flowing between the power supply terminal of the semiconductor integrated circuit and the device power supply of the semiconductor test apparatus, and a timing signal output from the timing circuit, Current value holding means for holding a current value at a previous time point output from the current value output means and continuously outputting the held current value until a next timing signal is input; and current value output means Current value difference output means for outputting a value obtained by subtracting the current value output from the current value holding means from the current value output from the current value, and the current value output from the current value difference output means and the determination reference current value. There is provided a semiconductor test apparatus comprising current value comparison / determination means for outputting a determination result converted into a logical value by comparison.
[0013]
Also, in the present invention (second invention), in the semiconductor test apparatus of the first invention, the current value output means, the current value holding means, and the current value difference output means are output in part or all of them. Provided is a semiconductor test apparatus characterized in that a value is a voltage value corresponding to a current value.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0015]
FIG. 1 is a block diagram of a semiconductor test apparatus according to an embodiment of the present invention. In this example, a system configuration of a semiconductor test apparatus according to the present invention is shown. Here, the device power supply 11, the timing circuit 12, the reference value output circuit 13, and the determination result input circuit 14 are naturally included in a general semiconductor test apparatus. Detailed description is omitted.
[0016]
First, a current value output means 21 for outputting a power supply current value given to the semiconductor integrated circuit 2 is connected between the device power supply 11 of the semiconductor test apparatus 1 and the power supply terminal of the semiconductor integrated circuit 2. Next, the current value output from the current value output unit 21 is input to the current value holding unit 22. The current value holding means 22 holds the current value at an arbitrary time point according to the timing signal output from the timing circuit 12, and continuously outputs the held current value until the next timing signal is input. Furthermore, the current value difference output unit 23 is connected to each of the current value output unit 21, the current value holding unit 22, and the current value comparison / determination unit 24. In the current value difference output means 23, the current value from the current value output means 21 and the current value at a past time determined by the timing circuit 12 from the current value holding means 22 are input. The value difference is output to the current value comparison / determination means 24. Finally, the current value comparison / determination means 24 compares the determination reference value output from the reference value output circuit 13 with the current value output from the current value difference output means 23, and sets the determination result to a logic of 0, 1. A value is output to the determination result input circuit 14.
[0017]
As described above, according to the system configuration of the semiconductor test apparatus according to the present invention, it is possible to eliminate the influence even when the OFF leak of the semiconductor integrated circuit 2 is large by determining the quality by the difference between the power supply current values at any two time points. In addition to satisfying the test purpose of providing an Iddq test capable of detecting an abnormal current due to a defect in the semiconductor integrated circuit 2, it further includes a step of directly measuring the power supply current value and performing statistical processing, and the determination result is logical. Since it is obtained by value, the Iddq test can be carried out in the same manner as a normal function test. As a result, only about 10 microseconds is required for the measurement of one point at a maximum, and the measurement time of 1000 points is 10 milliseconds, which is 1/100 of the conventional time, and the test time required for the Iddq test can be greatly reduced. Therefore, the time for using an expensive semiconductor test apparatus is reduced, and the test can be performed economically. In addition, since any of the circuits used in the system configuration of the semiconductor test apparatus according to the present invention can be configured with simple components that are generally commercially available, the implementation of the present invention does not increase the price of the semiconductor test apparatus. It should be noted that the present invention can be added not only to a semiconductor test apparatus but also as an external circuit that complements a general semiconductor test apparatus.
[0018]
FIG. 2 is a timing chart showing signals of respective parts in the embodiment shown in FIG. In each cycle, the semiconductor integrated circuit 2 is operated immediately after the start of the cycle to obtain a desired internal state, and then the operation is stopped until the end of the cycle to stabilize the current value. In cycle 1, after the current value 31 is stabilized, the current value 31 is held by the rise of the timing signal 32, and the holding current value 33 is obtained. In cycle 2, the difference between current value 31 and holding current value 33 is current value difference 34. When the current value difference 34 exceeds the reference value 35, the determination result 36 is output from the logic value “1”, and when it does not exceed, the logic value “0” is output from the current value comparison / determination unit 24. When the determination result 36 is input to the determination result input circuit 14, the logic of the determination result 36 is determined at a predetermined determination timing 37. If the logic is “0”, it is determined as “OK”. Thereafter, the holding current value 33 is updated by the timing signal 32, and the process proceeds to the next cycle. In a subsequent cycle, this series of processes is repeated. In cycle 3, an abnormal current is generated in the current value 31 due to a failure of the semiconductor integrated circuit 2. As a result, at the determination timing 37, the determination result 36 outputs a logic “1” and is determined to be “NG”. In cycle 4, since the holding current value 33 is the abnormal current value in cycle 3, the determination timing 37 is less than the zero point, but the determination result 36 is logic “0” and “OK”. Determined. Of course, if a cycle determined as “NG” appears as in cycle 3, the test may be immediately terminated as a defective product. In this example, the current value difference 34 and the reference value 35 are determined to be large or small, but the magnitude determination based on the absolute value may be performed, and the cycle 4 may be determined as “NG”. Furthermore, in this example, the timing signal 32 is changed and the holding current value 33 is updated in each cycle. However, for example, the timing signal 32 is changed only in the cycle 1, and the holding current held in the cycle 1 is changed in the subsequent cycles. A configuration using the value 33 may be adopted.
[0019]
FIG. 3 is a configuration diagram of a specific example in which the semiconductor test apparatus 1 is configured to output the current value output from the current value output means 21 as a corresponding voltage value.
[0020]
Here, the current detection resistor 41 and the differential amplifier 42 are used as the current value output means 21, the voltage value sample / hold (S / H) circuit 43 is used as the current value holding means 22, and the differential amplifier 44 is used as a current. The value difference output means 23 and the comparator 45 correspond to the current value comparison determination means 24, respectively.
[0021]
Hereinafter, the operation will be described using specific values. First, when the resistance value of the current detection resistor 41 is 100 [Ω] and the power supply current value flowing through the semiconductor integrated circuit 2 is 100 [μA], the voltage value difference between both ends of the current detection resistor 41 is 10 [mV]. . The differential amplifier 42 amplifies the voltage value difference between both ends of the current detection resistor 41 by 100 times, and the output voltage value becomes 1 [V]. This value is held by the timing circuit 12 and the voltage value sample / hold (S / H) circuit 43. In the next cycle, when the power supply current value flowing through the semiconductor integrated circuit 2 becomes 200 [μA], the voltage value output by the differential amplifier 42 becomes 2 [V]. The differential amplifier 44 outputs a difference between 2 [V], which is the current voltage value, and 1 [V], which is the voltage value at a past time point, and the output voltage value is 1 [V]. When a reference voltage value of 0.5 [V] is output from the reference value output circuit 13, the comparator 45 determines “NG” because the output voltage value of the differential amplifier 44 is larger. If the reference value from the reference value output circuit 13 is 1.5 [V], it is determined as “OK”. Incidentally, in this example, the reference voltage value 1 [V] of the reference value output circuit 13 corresponds to the power supply current value 100 [μA]. Note that the above numerical values are merely examples, and any numerical values may be used as long as the same function such as the resistance value of the current detection resistor 41 and the amplification factor of the differential amplifier 42 can be achieved. In addition, each system component reaching the determination result input circuit 14 may change its form as long as it can perform the same function.
[0022]
【The invention's effect】
As described above in detail, according to the semiconductor test apparatus of the present invention, the time required for the Iddq test can be reduced by simply adding a simple circuit to the semiconductor test apparatus in the shipping test of the semiconductor integrated circuit with a lot of OFF leakage. Since it can be significantly shortened, the usage time of an expensive semiconductor test apparatus can be reduced, the test can be carried out economically, and the cost can be reduced. Specifically, in semiconductor test equipment, when executing or stopping a test pattern, current value measurement processing, or measurement value digital value conversion, the software operation time for that processing cannot be ignored, so that one-point measurement is performed. However, according to the present invention, a test pattern can be executed and stopped once in a semiconductor test apparatus, while it takes about 1 second to measure about 1000 points. Because the current value difference of the power supply current at rest in the internal state can be logically determined, the measurement of one point is 10 microseconds, and the measurement of about 1000 points is about 10 milliseconds, which is 1 / 100th of the conventional, economical A typical Iddq test can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor test apparatus according to an embodiment of the present invention.
FIG. 2 is a timing chart showing changes in time and values of respective parts in the embodiment.
FIG. 3 is a configuration diagram showing a specific configuration example of the embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 2 Semiconductor integrated circuit 11 Device power supply 12 Timing circuit 13 Reference value output circuit 14 Determination result input circuit 21 Current value output means 22 Current value holding means 23 Current value difference output means 24 Current value comparison determination means 31 Current value 32 Timing signal 33 Holding current value 34 Current value difference 35 Reference value 36 Determination result 37 Determination timing 41 Current detection resistor 42 Differential amplifier 43 Voltage value sample / hold (S / H) circuit 44 Differential amplifier 45 Comparator

Claims (2)

In a semiconductor test apparatus for testing a semiconductor integrated circuit,
Current value output means capable of outputting a current value flowing between the power supply terminal of the semiconductor integrated circuit and the device power supply of the semiconductor test apparatus;
Based on the timing signal output from the timing circuit, the current value at the previous time point output from the current value output means is held, and the held current value is continuously output until the next timing signal is input. Current value holding means;
Current value difference output means for outputting a value obtained by subtracting the current value output from the current value holding means from the current value output from the current value output means;
A semiconductor test apparatus comprising: a current value comparison / determination unit that outputs a determination result converted into a logical value by comparing a current value output from the current value difference output unit with a determination reference current value.   The output value is a voltage value corresponding to a current value in a part or all of the current value output means, the current value holding means, and the current value difference output means. The semiconductor test apparatus described.

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