JP3148576B2 - Test circuit and test method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static power supply current test (hereinafter, referred to as "I _DDQ test") circuit for a semiconductor integrated circuit having CMOS (hereinafter, referred to as "CMOS semiconductor integrated circuit"). _DDQ test method.

[0002]

2. Description of the Related Art Conventionally, in a CMOS semiconductor integrated circuit, a power supply current flows only when an internal state transitions, and when a static state is reached, the power supply current becomes almost zero. The power supply current in the stationary state is called a stationary power supply current. If there is any failure inside the CMOS semiconductor integrated circuit, the stationary power supply current flows. Therefore, the I _DDQ test is to measure the stationary power supply current I _DDQ to detect the presence or absence of the failure. In the I _DDQ test, the internal state is changed while a test pattern is applied to the CMOS semiconductor integrated circuit, and the power supply current is measured after the state is stabilized, that is, after the quiescent state.

As a technique for measuring the above-mentioned static power supply current, Japanese Patent Laid-Open Publication No. Hei 5-273298 (hereinafter referred to as "Publication Document 1") and Japanese Patent Laid-Open Publication No. Hei 6-58981 (hereinafter referred to as "Prior Art Document"). 2 "). A measuring circuit is configured outside the CMOS semiconductor integrated circuit of the known document 1, whereas a known circuit 2 is different only in that the measuring circuit is built in the CMOS semiconductor integrated circuit. Insert a resistor to detect the current into the
The voltage generated at both ends is measured and compared with the limit value one by one by a comparator to judge the quality.

[0004]

However, the above-mentioned I _DDQ
In the test method, when the static power supply current does not flow, it is judged to be a good product.Therefore, some failure occurs in the circuit of the part detecting the static power supply current, and the static power current measured by the failure always If it becomes zero, for example, a CMOS integrated circuit under test (hereinafter, referred to as “DUT”)
Is determined to be good even if it has a failure. That is, if there is any failure in the stationary power supply current detection unit and the measured value becomes zero, the conventional method has a problem that even if there is a failure in the DUT, it is determined to be a good product.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide means for detecting both a failure of a DUT and a failure of a test circuit used for an _IDDQ test of the DUT.

[0006]

According to a first aspect of the present invention, there is provided a test circuit for a semiconductor integrated circuit according to the present invention, wherein an input terminal to which a power supply current is input from a device power supply for supplying a power supply current to a CMOS semiconductor integrated circuit to be inspected. A detection circuit for detecting a value of a current flowing between the input terminal and a power supply terminal of the tested CMOS semiconductor integrated circuit; a comparator for comparing an output value from the detection circuit with a predetermined limit value;
A first storage element that latches an output of the comparator at a predetermined first timing, an OR gate that receives an output of the first storage element and an output of the comparator,
A second storage element for latching the output of the OR gate at a predetermined second timing.

In the test circuit for a semiconductor integrated circuit according to the second aspect, an output from the second storage element is input to the OR gate. It is a test circuit of a circuit device.

According to a third aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit, comprising: a power supply current input terminal from a device power supply for supplying a power supply current to the CMOS integrated circuit to be tested; In the test method of the power supply current at the time of quiescent state, which detects a value of a current flowing between the power supply terminal and the power supply terminal, determines whether the detected value exceeds a predetermined limit value, and determines whether the LSI to be inspected is good or not. Is determined to be non-defective only when the power supply current flowing at the time of the transition is greater than or equal to a predetermined limit value and the power supply current in a stationary state after a lapse of a predetermined time is less than or equal to a predetermined limit value. It is assumed that.

[0009]

With the above arrangement, if the current flowing at the time of signal transition is not less than the limit value and the current at the strobe timing is not less than the limit value, the second storage element is set and the power supply current at rest is set. The presence or absence of a failure in the test circuit can be detected at the same time, and the reliability is improved.

Further, according to the second aspect of the present invention, when the output once fails, the output is maintained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment.

FIG. 1 is a circuit diagram of an embodiment of a static power supply current test circuit of a CMOS semiconductor integrated circuit according to the present invention.
FIG. 2 is a configuration diagram of a CMOS semiconductor integrated circuit to be inspected and a test circuit at the time of testing when the test circuit of FIG. 1 is used, and FIG. 3A shows a case where there is no failure in the static power supply current test circuit. FIG. 4B is a diagram illustrating a timing chart of each unit at the time of a test, and FIG. 4B is a diagram illustrating a timing chart of each unit at the time of a test when the static power supply current test circuit has a failure.

In FIG. 2, reference numeral 1 denotes a device power supply, 2 denotes a quiescent power supply current test circuit (hereinafter referred to as an “ _IDDQ test circuit”), and 3 denotes a controller, which controls each unit of the test apparatus. _{Reference numeral} 4 denotes a timing generation circuit which generates necessary timing in each section, and supplies a signal MCL ′ indicating a test rate and a strobe signal to the I _DDQ test circuit 2. Note that the signal MCL ′ is a signal obtained by delaying the signal MCL by the delay of the change in the power supply current during the state transition.

Reference numeral 5 denotes a test pattern application circuit, a memory for storing the test pattern, a waveform shaping circuit for shaping data read from the memory, and an actual D.
It consists of a driver circuit that converts the signal level to drive the UT. The clock from the timing generation circuit 4 is used for waveform shaping. Reference numeral 6 denotes a semiconductor integrated circuit (DUT) having a CMOS to be inspected.

In FIG. 1, reference numeral 7 denotes a relay,
It has a role of bypassing the resistor 8 when measuring the power supply current at rest. Reference numeral 8 denotes a resistor for detecting a power supply current at rest, and reference numeral 9 denotes a phase compensation capacitor. 1
Reference numeral 0 denotes a diode, which has a role of supplying a current flowing when the DUT 6 transitions to the state, bypassing the resistor 8.

Reference numeral 11 denotes a differential amplifier, which outputs the voltage between both ends of the resistor 8 with reference to the ground potential. Reference numeral 12 denotes an amplifier, which amplifies the output of the differential amplifier 11 by α times. The voltage drop due to the current flowing through the resistor 8 is amplified as much as possible so that the operation can be performed with high accuracy. And 14
Is a first flip-flop. The output of the comparator 13 is input to a data input terminal D, and the signal MCL 'is input to a clock input terminal.

An OR gate 15 receives the inverted output of the first flip-flop 14 and the comparator 13. Reference numeral 16 denotes a second flip-flop. The output of the OR gate 15 is input to the data input terminal D, and the strobe signal is input to the clock input terminal. The output Q of the second flip-flop 16 enters the input of the OR gate 15, and once the second flip-flop 16 goes high, has the role of maintaining that state thereafter.

Next, with reference to FIG. 3 (a), when there is no fault in the I _DDQ test circuit 2, one embodiment of the present invention I _DDQ
The operation at the time of the test using the test circuit will be described.

First, the first flip-flop 14
And the second flip-flop 16 is reset.

Next, when an input signal shown in the uppermost stage in FIGS. 3A and 3B is applied, the internal state of the DUT 6 changes every fixed cycle. This cycle is called a test rate. Then, at the beginning of each test rate, D
The internal state of the UT 6 changes to a transition state, and the internal state stabilizes after a certain period of time. The power supply current waveform at this time is an output waveform like the amplifier 12. The broken lines in the output waveforms of the amplifier 12 in FIGS. 3A and 3B indicate the limit values. That is, when the output waveform of the amplifier 12 is above the broken line, it exceeds the limit, and when it is below the broken line, it means below the limit.

Next, the comparator 13 compares the output of the amplifier 12 with the preset limit value. Thereafter, the output of the comparator 13 is a signal MC obtained by delaying the signal MCL indicating the test rate by the delay time of the current change.
The data is latched by the first flip-flop 14 at the timing of L '. Note that in FIG. 3A, the signal MCL ′
Since the output of the comparator 13 is always high at the rising edge of the first flip-flop, the internal state of the first flip-flop 14 remains high, and the inverted output of the first flip-flop 14 becomes low. In such a case, it means that the _IDDQ test circuit 2 is normal and there is no failure.

However, at the fourth test rate in FIG. 3A, there is some failure in the DUT 6, and the power supply current exceeds the limit value. Therefore, the output of the second flip-flop 16 becomes high at the strobe timing of the fourth test rate. Since the output Q of the second flip-flop 16 is connected to the input of the OR gate 15, the output Q of the second flip-flop 16
Once it goes high, it keeps high thereafter.

That is, the fact that a failure has occurred is stored until the end of the test, and the controller 3 reads this value at the end so that the presence or absence of a failure in the DUT 6 can be determined. As described above, when there is no failure in the I _DDQ test circuit 2, an abnormality can be detected when the quiescent power supply current (I _DDQ ) exceeds the limit value.

Next, with reference to FIG. 3B, a case will be described in which a failure occurs in the _IDDQ test circuit 2 during the test and the output of the amplifier 12 becomes zero.

First, the _IDDQ test circuit 2 has no failure until the second test rate in FIG. 3B, and the power supply current at the output of the amplifier 12 at the time of input transition until the second test rate is increased. Flowing. However, at the third test rate, the output of the amplifier 12 becomes zero due to the failure of the I _DDQ test circuit 2. Therefore, the inverted output of the first flip-flop 14 changes from low to high at the timing of the signal MCL 'at the third test rate.

This change is transmitted to the OR gate 15, and the second flip-flop 16 becomes high with the strobe signal at the third test rate. As a result, I _DDQ
Even when a failure occurs in the test circuit 2, the output of the second flip-flop 16 becomes high, and an abnormality can be detected.

In this embodiment, by connecting the output Q of the second flip-flop 16 to the input of the OR gate 15, once the second flip-flop 16 becomes high, the circuit configuration is maintained. However, if the output Q of the second flip-flop 16 is checked at the end of each test rate, it is not necessary to connect the output Q of the second flip-flop 16 to the input of the OR gate 15. .

[0028]

As described in detail above, by using the present invention, even when a failure occurs in the _IDDQ test circuit, a fail signal is generated and the C
This prevents the MOS semiconductor integrated circuit from being overlooked and improves the reliability of the test circuit, and at the same time improves the quality of the device because a device having a fault is not overlooked.

By using the present invention, it is not necessary to check the output of the second storage element at the end of each test rate, thereby simplifying the test process.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a static power supply current test circuit of a CMOS semiconductor integrated circuit according to the present invention.

2 is a configuration diagram of a tested CMOS semiconductor integrated circuit and a test circuit at the time of a test using the test circuit of FIG. 1;

3A is a diagram showing a timing chart of each unit at the time of a test when there is no failure in the static power supply current test circuit, and FIG. 3B is a diagram showing a test when there is a failure in the static power supply current test circuit; It is a figure showing a timing chart of each part at the time.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Device power supply 2 Static power supply current test circuit 3 Controller 4 Timing generation circuit 5 Test pattern application circuit 6 Semiconductor integrated circuit (DU having a CMOS under inspection)
T) 7 relay 8 resistor 9 phase compensation capacitor 10 diode 11 differential amplifier 12 amplifier 13 comparator 14 first flip-flop 15 OR gate 16 second flip-flop

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 21/822 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/04 G01R 31/26 G01R 31/28 H01L 21/66 H01L 21/822

Claims (3)

(57) [Claims] 1. An input terminal to which a power supply current is input from a device power supply for supplying a power supply current to a CMOS semiconductor integrated circuit under test, and flows between the input terminal and a power supply terminal of the CMOS integrated circuit under test. A detection circuit for detecting a current value; a comparator for comparing an output value from the detection circuit with a predetermined limit value; a first storage element for latching an output of the comparator at a predetermined first timing; An OR gate to which the output of the first storage element and the output of the comparator are input, and a second storage element that holds the output of the OR gate at a predetermined second timing. Test circuit for a semiconductor integrated circuit. 2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein an output of said second storage element is input to said OR gate. 3. A method for detecting a value of a current flowing between an input terminal to which a power supply current is supplied from a device power supply device for supplying a power supply current to the CMOS semiconductor integrated circuit under test and a power supply terminal of the CMOS semiconductor integrated circuit under test. A method for determining whether or not the detected value exceeds a predetermined limit value and determining whether or not the LSI to be inspected is good or defective, wherein the power supply current flowing at the time of transition of the input signal is a predetermined limit value. A test method for a semiconductor integrated circuit device, wherein a non-defective product is determined only when the power supply current in a stationary state after a lapse of a predetermined time is equal to or less than a predetermined limit value.