JP2002131368A - Cmos-lsi testing method and device for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for easily and surely detecting a failure of a CMOS-LSI. SOLUTION: An electric current is measured when reverse voltage is impressed between a Vdd terminal and Vss terminal of the CMOS-LSI in the opposite direction to the driving voltage impression direction. Using a difference of a V-I characteristic between that (a curved line III) in the case of a failure and that (a broken line IV) in the case of a normal condition, a failure inside the CMOS-LSI is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test technique, and more particularly, to a completely new type of test method and apparatus for detecting a fault inside a CMOS-LSI.

[0002]

2. Description of the Related Art In an LSI test, a conventional ATE
(Automatic test equipment) function tests. In the function test, L
Check whether the SI operates according to the predetermined function. To this end, test patterns are sequentially applied to the input terminals of the LSI, and a comparison check is made as to whether the pattern appearing at the output terminals is as expected.

In recent years, CMs having excellent low power consumption characteristics have been developed.
A CMOS-LSI in which each gate is configured by an OS is widely used. In testing a CMOS-LSI (CMOS device), an Iddq test may be performed. In the Iddq test, a test pattern is applied to the device, and the quiescent power supply current (Id
The failure is detected by measuring d).

[0004]

By the way, in recent years, LS
I is becoming larger and larger. For this reason, a test pattern having an enormous data amount is required for the function test and the Iddq test, and the test apparatus is becoming expensive. Further, as the circuit configuration of the LSI becomes complicated, the LS
It has become difficult to completely test all gates inside I.

The present invention has been made in view of the above circumstances, and has as its object to provide a technique for easily and surely detecting a failure in a CMOS-LSI.

[0006]

According to a first aspect of the present invention, there is provided a CMOS-LSI test method, comprising the steps of: applying a driving voltage to a power supply terminal of a CMOS-LSI in a direction opposite to a driving voltage application direction; The reverse voltage is applied in the direction, the current flowing to the power supply voltage terminal when the reverse voltage is applied is measured, and the CMO is determined based on the voltage-current characteristic when the reverse voltage is changed.
This is a method for detecting a failure inside the S-LSI.

Further, a CMOS-type semiconductor device according to claim 2 of the present invention.
According to the LSI test method, a reverse current in a direction opposite to the direction of a current flowing during driving is applied to a power supply voltage terminal of a CMOS-LSI, and a voltage appearing at the power supply voltage terminal when the reverse current is applied is measured. This is a method for detecting a failure inside the CMOS-LSI based on the voltage-current characteristics when the reverse current is changed.

In a CMOS circuit, a parasitic diode is usually formed at a junction between a substrate and two FETs constituting the CMOS circuit. Therefore, when a reverse voltage in the reverse direction to the drive voltage is applied to the power supply terminal of the CMOS-LSI, a voltage in the forward bias direction is applied to the parasitic diode portion. As a result, the voltage-current characteristic (VI characteristic) when a reverse voltage is applied to a normal CMOS circuit is the VI characteristic when a forward bias voltage is applied to two diodes connected in series to each other. Is equivalent to

On the other hand, F which forms a CMOS circuit
When a short-circuit fault exists between the source and the drain of the ET, the state is equivalent to a state where a low resistance is connected in parallel with the parasitic diode. As a result, the VI characteristics when a reverse voltage is applied to the defective CMOS are different from the VI characteristics when a reverse voltage is applied to the normal CMOS. Therefore, by detecting the difference in VI characteristics between a defective LSI having a defective CMOS inside and a normal LSI,
A failure inside the LSI can be detected. Therefore, according to the CMOS-LSI test method according to the first or second aspect of the present invention, as described above, the failure of the LSI is detected based on the VI characteristics of the reverse voltage and the reverse current.

According to the third aspect of the present invention, there is provided a method for displaying a measured current in a logarithmic manner in a voltage-current characteristic. In this way, if the measured current is displayed in a logarithmic manner, the difference between the VI characteristics of the normal LSI and the defective LSI can be further clarified.

Incidentally, a large scale CMOS-LSI
The number of gates is extremely large, for example, several hundred thousand to several million. When the number of gates is large, the difference in current value between a defective LSI having one failure and a normal LSI is small. Therefore, according to the fourth aspect of the present invention, there is provided a method of displaying a logarithmically expressed measured current in a voltage-current characteristic as a second derivative.

VI characteristic curve of normal LSI and defective LSI
In general, the position and number of inflection points are different from the VI characteristic curve. Therefore, if the current is expressed by the second derivative, the inflection point is represented as a peak (maximum point), so that the position and number of the inflection point can be easily obtained. As a result, even in a CMOS-LSI having a large number of gates, the difference in VI characteristics can be further clarified, the presence or absence of a failure can be easily determined, and a failure can be detected.

According to the LSI test apparatus of the present invention, there is provided a CMOS-LSI test apparatus in which a parasitic diode is formed in a circuit.
A voltage application / current measurement unit for applying a reverse voltage in the direction opposite to the drive voltage direction to the power supply voltage terminal of I, and measuring a current flowing to the power supply voltage terminal when the reverse voltage is applied, and changing the reverse voltage. CMOS based on the voltage-current characteristics
And a failure detection unit that detects a failure inside the LSI.

As described above, according to the present invention, the voltage application
By applying a reverse voltage by the current measuring unit and measuring the current, and detecting the failure based on the voltage-current characteristics by the failure detection unit, the failure inside the CMOS-LSI can be easily and reliably achieved with an inexpensive test device. Can be detected.

According to the present invention, the voltage application / current measurement section includes a voltage application section, a current measurement section, and a control section, and the voltage application section applies a reverse voltage when changing the reverse voltage. Each reverse voltage value is stored in association with an address, and a voltage value memory for sequentially outputting a voltage value corresponding to the address sequentially specified by the control unit, and a voltage value input from this voltage value memory as D A / D (digital / analog) conversion and a D / A converter for outputting a reverse voltage, and the current measuring unit converts the measured current to A / D (analog / digital) and outputs a measured current value And a current value memory for sequentially storing the measured current values input from the A / D converter in correspondence with addresses sequentially designated by the control unit.

As described above, if a memory for storing an applied voltage value and a measured current value to which an address is given is provided, the applied voltage value and the measured current value can be associated with each other via the address. The VI characteristic can be obtained at the same time.

According to an LSI inspection apparatus according to a seventh aspect of the present invention, there is provided a CMOS-LSI test apparatus in which a parasitic diode is formed in a circuit.
A current application / voltage measurement unit for applying a reverse current in the direction opposite to the direction of the current flowing during driving to the power supply voltage terminal of I, and measuring the voltage applied to the power supply voltage terminal when the reverse current is applied; And a failure detection unit that detects a failure inside the CMOS-LSI based on the voltage-current characteristics when the reverse current is changed.

As described above, according to the present invention, the current application
A voltage measurement unit applies a reverse current to measure a voltage, and a failure detection unit detects a failure based on the voltage-current characteristics, thereby easily and reliably detecting a failure inside the CMOS-LSI with an inexpensive test device. can do.

According to the present invention, the current application / voltage measurement unit includes a current application unit, a voltage measurement unit, and a control unit, and the current application unit applies the reverse current when changing the reverse current. Each reverse current value is stored in association with an address, and a current value memory for sequentially outputting current values corresponding to addresses sequentially designated by the control unit, and a current value inputted from this current value memory as D And a D / A converter that outputs a reverse current after performing the A / A conversion. The voltage measuring unit A / D converts the measured voltage and outputs a measured voltage value.
/ D converter and a voltage value memory for sequentially storing the measured voltage values input from the A / D converter in correspondence with addresses sequentially specified by the control unit.

As described above, if a memory for storing an applied current value and a measured voltage value each having an address is provided, the applied voltage value and the measured current value can be associated with each other via the address. The VI characteristic can be obtained at the same time.

Further, according to the LSI test method according to the ninth aspect of the present invention, when testing a CMOS-LSI in which a parasitic diode is formed in a circuit, a CMOS-LSI
An AC voltage is applied to the power supply voltage terminal of I, and the current flowing through the power supply voltage terminal when the AC voltage is applied is measured. Based on the frequency spectrum of the measured current corresponding to the frequency of the AC voltage, the CMOS-LSI This is a method for detecting a failure.

When an AC voltage is applied, the frequency spectrum of the current differs depending on whether or not there is a failure. Therefore, by detecting the difference between the spectrum of the normal LSI and the spectrum of the defective LSI, it is possible to easily and reliably detect a failure inside the LSI.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] In the first embodiment, claims 1, 2, 4
An example of the CMOS-LSI test method according to the fifth and fifth aspects and an example of the CMOS-LSI test apparatus according to the sixth and seventh aspects will be described.

Here, referring to FIG. 1, the short-circuit failure location S of the CMOS-LSI of the first embodiment and the CMOS-LSI
The configuration and test method of the LSI test apparatus (hereinafter, also simply referred to as “LSI test apparatus”) 5 will be described. In FIG. 1, two CMOSs 4 are shown as a circuit configuration of the CMOS-LSI for convenience, and illustration of other parts is omitted.

As shown in FIG. 1, a CMOS test target
Each gate of the LSI (DUT) 1 is configured by a CMOS circuit 4. And for all CMOS circuits,
Parasitic diodes are formed. In the example shown in FIG.
Among the CMOS circuits 4 constituting the CMOS-LSI 1,
A state in which a short-circuit defect S has occurred in one CMOS circuit 4 is schematically shown as a low-resistance defect.

The LSI test apparatus 5 for testing the CMOS-LSI 1 comprises a voltage application / current measuring device 51 and a failure detecting section 52. The voltage application / current measuring device 51 is connected to a power supply voltage terminal (Vd
d terminal) 2 and a ground voltage terminal (Vss terminal) 3
A reverse voltage in a direction opposite to the direction of the drive voltage is applied, and a current flowing between the Vdd terminal 2 and the Vss terminal 3 when the reverse voltage is applied is measured.

Although the Vss terminal is referred to as a ground voltage terminal here, the potential of the Vss terminal is not necessarily limited to the ground potential (0 V). To apply a reverse voltage to the Vdd terminal means to apply a voltage so that the potential of the Vdd terminal is lower than the potential of the Vss terminal.

Here, the configuration of the voltage application / current measuring device 51 will be described with reference to FIG. As shown in FIG. 2, the voltage application / current measurement device 51 includes a control unit 511,
It comprises a voltage value memory 512, a D / A converter 514, a current value memory 513, and an A / D converter 515.

The control unit 511 indicates the same address to the voltage value memory 512 and the current value memory 513. The voltage value memory 512 stores each reverse voltage value applied when changing the reverse voltage in association with an address, and sequentially outputs the voltage values corresponding to the addresses sequentially specified by the control unit 511. Then, the D / A converter 514 D / A converts the voltage value input from the voltage value memory 512 and outputs a reverse voltage.

On the other hand, A / D converter 515 A / D converts the measured current and outputs a measured current value. Then, the current value memory 513 sequentially stores the measured current values input from the A / D converter 515 in association with the addresses sequentially specified by the control unit 511.

Then, each voltage value stored in the voltage value memory 512 and each measured current value stored in the current value memory 513 are sent to the defect detecting section 52. Defect detection unit 52
Calculates a VI characteristic by associating an applied voltage value with a measured current value via an address. Then, a short-circuit failure inside the CMOS-LSI is detected based on the VI characteristics when the reverse voltage is changed.

Next, FIG. 3 shows a CMOS having several gates.
-An example of measurement of VI characteristics when an LSI is a test object (DUT) is shown. The horizontal axis of the graph in FIG. 3 represents the applied voltage (V), and the vertical axis represents the current (μA) in a linear display. A curve I in the graph of FIG. 3 represents a VI characteristic of a defective LSI in which a short-circuit fault exists. A dashed line II indicates VI characteristics of a normal LSI. In the graph of FIG. 3, the value of the applied voltage is displayed with the forward direction being positive. For this reason, the reverse voltage is indicated by a negative value.

As shown by the curve I, when there is a short-circuit fault, the current value is larger than that of the normal broken line II. That is, the dashed line II has an applied voltage of -0.90 V
While the curve I clearly rises from the vicinity, the curve I clearly rises at an early stage near the applied voltage of −0.40 V. As described above, the current value with respect to the same applied voltage is different between the case where the short-circuit fault is present and the case where the short-circuit fault is normal, so that the defect can be detected.

Next, FIG. 4 is a graph showing a case where the current (A) is logarithmically displayed with respect to the measurement results shown in FIG. The horizontal axis of the graph in FIG. 4 represents the applied voltage (V),
The vertical axis represents the current (A) in logarithmic representation. Curve III in the graph of FIG. 4 indicates a defect L in which a short-circuit fault exists.
5 shows the VI characteristics of SI. The broken line IV indicates a normal L
5 shows the VI characteristics of SI.

In the graph of FIG. 3 in which the measured current is linearly displayed, a defect was detected based on a difference in current value between a normal case and a short-circuit failure. On the other hand, in the graph of FIG. 4 in which the measured current is logarithmically displayed, a defect can be detected by the ratio of the current values.

For example, in FIG. 3, the applied voltage is -0.60
Near V, the difference between the current value indicated by the curve I and the current value indicated by the dashed line II is about 10 μA. On the contrary,
In FIG. 4, when the applied voltage is around -0.60 V, the current value indicated by the curve III is 1000 times (three digits) larger than the current value indicated by the broken line IV. Therefore, by displaying the measured current logarithmically, the defect can be detected more easily.

When the number of LSI gates increases from several hundred thousand to several million, the total value of the current flowing through each parasitic diode increases. For this reason, even if the measured current is displayed in logarithm, the difference in VI characteristics between a normal case and a short-circuit failure (abnormal) becomes small. However, if the current is measured by a device having a wide dynamic range, it is sufficiently possible to obtain a difference in VI characteristics.

Here, as an example, the number of gates is one million (1).
0 ⁶⁾ to examine the dynamic range of current measurements required from a number of CMOS-LSI to detect one of the short-circuit failure. Assuming that the value of the current of the normal LSI (normal current) is “1”, the dynamic range necessary for testing the one million gate LSI is given by the following equation (1).

(Normal current) × 6 digits (number of gates) −3 digits (abnormal current) = 3 digits (1)

Therefore, it can be seen that if the dynamic range of the current measuring device is four digits or more, the failure of the one million gate LSI can be detected. A current measuring device having a 5-digit dynamic range can be easily created by a conventionally known technique.

Even if the current value in the normal case and the current value in the case of a short-circuit fault are close to each other, the curve pattern of the VI characteristic differs between the normal case and the short-circuit fault. I have. That is, curve III and wavy line IV in FIG.
As shown in (1), each curve pattern in the logarithmic representation has an inflection point instead of monotonically increasing.

The positions and numbers of these inflection points are different between normal cases and short-circuit faults. That is, when there is a short-circuit failure, the number of inflection points tends to increase as compared with a normal case. For example, the wavy line I in FIG.
V has two inflection points, whereas the curve III in the case where there is a short-circuit fault has three inflection points.

Therefore, the curve III shown in FIG.
If the dashed line IV is second-order differentiated, the inflection point has a peak, so that the position and number of the inflection point can be easily obtained.
Here, FIG. 5 shows a characteristic example when the current is second-order differentiated. The horizontal axis of the graph in FIG. 5 represents the applied voltage (V), and the vertical axis represents the second-order differential current (A / V ² ) in logarithmic representation. A curve V in the graph of FIG. 5 is a second-order derivative of a curve III representing a VI characteristic of a defective LSI having a short-circuit fault therein. A dashed line VI is obtained by performing second-order differentiation of a dashed line IV representing VI characteristics of a normal LSI.

In the curve V in FIG. 5, the two inflection points in the curve III in FIG. 4 are clearly shown as two peaks near -0.5V and -1.2V. On the other hand, in the broken line VI in FIG. 5, one inflection point in the broken line IV in FIG. 4 is clearly shown as one peak near −1.1 V. Therefore, it can be seen that the peak corresponding to the inflection point is increased by one and the position of the peak is also different in the case of failure compared to the case of normal.

As described above, if attention is paid to the position or number of the inflection point or the combination of the position and number of the inflection point in the logarithmic graph, the difference in the VI characteristic between the normal circuit and the defective circuit can be found. It can be even clearer. as a result,
The presence / absence of a short-circuit failure can be more easily determined, and the failure can be more reliably detected.

[Second Embodiment] In a second embodiment, an example of an LSI test method according to claims 1 and 3 and an example of an LSI test apparatus according to claims 8 and 9 will be described. In the above-described first embodiment, an example in which a voltage is applied and a current is measured has been described. In the present embodiment, an example in which a current is applied and a voltage is measured will be described.

Here, a configuration and a test method of the CMOS-LSI test apparatus (hereinafter, also simply referred to as "LSI test apparatus") 6 of the second embodiment will be described with reference to FIG. The CMOS-LS to be tested shown in FIG.
The circuit configuration of the I (DUT) 1 is the same as that shown in FIG. 1, and a description thereof will be omitted.

As shown in FIG. 5, the LSI test apparatus 6 according to the second embodiment includes a current applying / voltage measuring device 61 and a failure detecting section 62. The current application / voltage measurement device 61 is connected to the Vdd terminal 2 of the CMOS-LSI 1 and the Vs terminal.
A reverse current in the direction opposite to the direction of the current flowing at the time of driving is applied between the s terminal 3 and Vdd when the reverse current is applied.
The voltage applied between the terminal 2 and the Vss terminal 3 is measured.

Here, the configuration of the current applying / voltage measuring device 61 will be described with reference to FIG. As shown in FIG. 6, the current application / voltage measuring device 61 includes a control unit 611, a current value memory 612, a D / A converter 614, a voltage value memory 613, and an A / D converter 615.

The control unit 611 indicates the same address to the current value memory 612 and the voltage value memory 613. The current value memory 612 stores each reverse current value applied when changing the reverse current in association with an address, and sequentially outputs a current value corresponding to the address sequentially specified by the control unit 611. Then, the D / A converter 614 D / A converts the current value input from the current value memory 612 and outputs a reverse current.

On the other hand, A / D converter 615 performs A / D conversion of the measured voltage and outputs a measured voltage value. Then, the voltage value memory 613 sequentially stores the measured voltage values input from the A / D converter 615 in association with the addresses sequentially specified by the control unit 611.

Then, each current value stored in the current value memory 612 and each measured voltage value stored in the voltage value memory 613 are sent to the defect detection unit 62. Failure detection unit 62
Calculates the VI characteristic by associating the applied current value with the measured voltage value via an address, similarly to the failure detection unit 52 in the above-described first embodiment. Then, based on the voltage-current characteristics when the reverse current value is changed, the CMOS-LS
A short-circuit fault inside I is detected.

In the second embodiment, a graph of the VI characteristic similar to that shown in FIGS. 3 and 4 is obtained. In the graph of the VI characteristic, the applied current value may be set on the horizontal axis, and the measured voltage value may be set on the vertical axis.

[Third Embodiment] In a third embodiment, an example of the LSI test method according to claim 10 will be described.
In the above-described first and second embodiments, the failure is detected based on the difference in the VI characteristics in a state where the DC reverse voltage is applied to the power supply terminal. An example in which a failure is detected based on a difference in the frequency spectrum of the current in the embodiment will be described.

Here, a configuration and a measuring method of the CMOS-LSI test apparatus (hereinafter, also simply referred to as "LSI test apparatus") 7 of the third embodiment will be described with reference to FIG. The CMOS-LS to be tested shown in FIG.
The circuit configuration of the I (DUT) 1 is also the same as that shown in FIG. 1, and a description thereof will be omitted.

As shown in FIG. 7, the LSI test apparatus 7 according to the third embodiment includes an AC voltage application / current measuring device 71 and a failure detecting section 72. The AC voltage application / current measuring device 71 is a CMOS-LSI (D
An AC voltage is applied between the Vdd terminal 2 and the Vss terminal 3 of the UT) 1 and a current flowing between the Vdd terminal 2 and the Vss terminal 3 when the AC voltage is applied is measured.

When an AC voltage is applied, the frequency spectrum of the current differs depending on the presence or absence of a short circuit defect inside the LSI. Accordingly, the failure detection unit 72 determines the frequency spectrum of the measured current when the frequency of the applied AC voltage changes, that is, based on the frequency distribution of the measured current value.
A short circuit fault inside the MOS-LSI is detected.

FIG. 8 shows the results of testing a normal LSI and an LSI having a short-circuit fault. FIG. 8A shows a fast Fourier transform (F) of a current measured when a DC voltage of 1.6 V and an AC voltage of 1 MHz having an amplitude of 1.5 V are superimposed and applied to a normal LSI.
FIG. 8B shows a frequency spectrum obtained by frequency analysis using the FT) method, and FIG. 8B shows a frequency spectrum of a current measured when an AC voltage is applied to an LSI having a short-circuit fault therein. . The horizontal axis of each graph in FIG. 8 represents the frequency (MHz) of the applied voltage, and the vertical axis represents the measured current (A) in logarithmic representation.

As can be seen by comparing FIGS. 8A and 8B, the spectrum pattern differs between the normal LSI and the defective LSI. Therefore, by detecting the difference between these spectra, a short circuit fault inside the LSI can be easily and reliably detected.

In the above-described embodiment, an example has been described in which the present invention is configured under specific conditions. However, the present invention can be variously modified. For example, in each of the above-described embodiments, an example in which an LSI test is performed using an LSI test apparatus having a specific configuration has been described. However, in the present invention, the configuration of the LSI test apparatus is not limited to this.

[0061]

As described above in detail, according to the CMOS-LSI test method according to the first and second aspects of the present invention, the voltage-current characteristics of the reverse voltage and the reverse current in the direction opposite to the drive voltage are obtained. LSI failure is detected based on This allows
A failure inside the CMOS-LSI can be easily and reliably detected. As a result, by combining the test method of the present invention with a conventional function test, etc.
The reliability of the test can be improved. Further, if the test method of the present invention is performed prior to a conventional function test or the like, an LSI chip in which a defect is detected by this test method can be removed in advance. As a result, the LSIs to be subjected to the function test can be narrowed down, so that the throughput of the LSI test can be improved.

Further, according to the fifth aspect of the present invention, a CMOS
According to the LSI test apparatus, a current is measured by applying a reverse voltage in a direction opposite to the drive voltage, and a failure is detected based on a voltage-current characteristic. Further, a CMOS-type semiconductor memory device according to claim 7 of the present invention.
According to the LSI test apparatus, a voltage is measured by applying a reverse current in a direction opposite to a current flowing during driving, and a failure is detected based on a voltage-current characteristic. Thus, in any of the fifth and seventh aspects of the present invention, a failure inside the CMOS-LSI can be easily and reliably detected by an inexpensive test device.

Further, according to the ninth aspect of the present invention, a CMOS
According to the LSI test method, an AC voltage is applied to a power supply terminal of an LSI to measure a current, and a failure is detected based on a frequency spectrum of the current. Thereby, the CMOS-LS
A failure inside I can be detected easily and reliably.
As a result, the reliability of an LSI test can be improved by combining the test method of the present invention with a conventional function test or the like. Further, if the test method of the present invention is performed prior to a conventional function test or the like, an LSI chip in which a defect is detected by this test method can be removed in advance. As a result, the function test target LS
Since I can be reduced, the throughput of the LSI test can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an LSI test method and apparatus according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a voltage application / current measurement device of the LSI test apparatus according to the first embodiment.

FIG. 3 is a graph showing voltage-current characteristics.

FIG. 4 is a graph showing a voltage-current characteristic when a current is logarithmically displayed.

FIG. 5 is a graph showing characteristics when a current is second-order differentiated.

FIG. 6 is an explanatory diagram of an LSI test method and apparatus according to a second embodiment.

FIG. 7 is a block diagram illustrating a configuration of a current application / voltage measurement device of an LSI test apparatus according to a second embodiment.

FIG. 8 is a block diagram illustrating an LSI test method and apparatus according to a third embodiment.

FIG. 9 is a graph showing a frequency spectrum of a current.

[Explanation of symbols]

 1 CMOS-LSI (DUT) to be tested 2 Power supply voltage terminal (Vdd terminal) 3 Ground voltage terminal (Vss terminal) 4 CMOS circuit (CMOS) 5, 6, 7 LSI test equipment 51 Voltage application / current measurement device 52 Failure detection Unit 61 Current application / voltage measurement device 62 Failure detection unit 71 AC voltage application / current measurement device 72 Failure detection unit

Claims (9)

[Claims] 1. A reverse voltage is applied to a power supply voltage terminal of a CMOS-LSI in a direction opposite to a driving voltage application direction, and a current flowing through the power supply voltage terminal when the reverse voltage is applied is measured. A method for testing a CMOS-LSI, comprising detecting a failure inside the CMOS-LSI based on a voltage-current characteristic when a voltage is changed. 2. A reverse current in a direction opposite to a current flowing during driving is applied to a power supply voltage terminal of a CMOS-LSI, and a voltage appearing at the power supply voltage terminal when the reverse current is applied is measured. A CMOS-LSI test method, wherein a failure inside the CMOS-LSI is detected based on a voltage-current characteristic when the reverse current is changed. 3. The CMOS-LSI test method according to claim 1, wherein the measured current is displayed as a logarithm in the voltage-current characteristics. 4. The CMOS-LSI test method according to claim 3, wherein, in the voltage-current characteristics, the measured current expressed in logarithmic form is expressed by second-order differentiation. 5. A CMOS-LSI test apparatus in which a parasitic diode is formed in a circuit, wherein a reverse voltage in a direction opposite to a drive voltage direction is applied to a power supply voltage terminal of the CMOS-LSI. A voltage application / current measurement unit that measures a current flowing to the power supply voltage terminal when the voltage is applied, and detects a failure inside the CMOS-LSI based on a voltage-current characteristic when the reverse voltage is changed. A CMOS-LSI test apparatus comprising: a defect detection unit. 6. The voltage application / current measurement unit includes a voltage application unit, a current measurement unit, and a control unit, and the voltage application unit specifies each reverse voltage value to be applied when changing the reverse voltage as an address. A voltage value memory for sequentially outputting voltage values corresponding to addresses sequentially designated by the control unit; and a D / A conversion of the voltage value input from the voltage value memory and performing a reverse operation. And a D / A converter that outputs a voltage. The current measurement unit A / D converts an A / D of a measured current and outputs a measured current value.
2. The apparatus according to claim 1, further comprising: a converter; and a current value memory for sequentially storing the measured current values input from the A / D converter in correspondence with the addresses sequentially specified by the control unit. 7. The CMOS-LSI test apparatus according to 6. 7. A CMOS-LSI test apparatus in which a parasitic diode is formed in a circuit, wherein a reverse current in a direction opposite to a direction of a current flowing during driving is applied to a power supply voltage terminal of the CMOS-LSI. A current application / voltage measurement unit that measures a voltage appearing at the power supply voltage terminal when a reverse current is applied; and a voltage-current characteristic inside the CMOS-LSI based on a voltage-current characteristic when the reverse current is changed. A CMOS-LSI test apparatus comprising: a failure detection unit that detects a failure. 8. The current application / voltage measurement unit includes a current application unit, a voltage measurement unit, and a control unit, and the current application unit sets each reverse current value applied when changing the reverse current as an address. A current value memory for sequentially outputting a current value corresponding to an address sequentially designated by the control unit, and a D / A conversion of a current value input from the current value memory to generate a reverse current And a D / A converter that outputs the measured voltage. The voltage measuring unit performs A / D conversion of the measured voltage and outputs the measured voltage value.
2. The apparatus according to claim 1, further comprising: a converter; and a voltage value memory for sequentially storing the measured voltage values input from the A / D converter in correspondence with the addresses sequentially specified by the control unit. 8. The CMOS-LSI test apparatus according to 8. 9. In testing a CMOS-LSI in which a parasitic diode is formed in a circuit, an AC voltage is applied to a power supply voltage terminal of the CMOS-LSI, and when the AC voltage is applied, an AC voltage is applied to the power supply voltage terminal. A CMOS-LSI test method, comprising: measuring a flowing current; and detecting a failure inside the CMOS-LSI based on a frequency spectrum of a measured current corresponding to a frequency of the AC voltage.