JP4754264B2 - Semiconductor integrated circuit and method for testing a product incorporating the semiconductor integrated circuit - Google Patents

Description

  The present invention relates to, for example, a semiconductor integrated circuit that switches and outputs n-stage gradation voltages for each of a plurality of output terminals, and a method for testing a product equipped with the semiconductor integrated circuit.

  In recent years, it has become possible to display a precise CG (computer graphics) image, a high-definition natural image full of realism, and the like by improving the technology of an image display device. However, there is a growing demand for displaying higher-definition images with higher gradation.

  Also in the liquid crystal panel constituting the liquid crystal display device, there is an increasing demand for higher definition of the display image, and the liquid crystal driver LSI (large scale integrated circuit) mounted on the liquid crystal panel is increased in output and output. Gradation is progressing.

  In order to perform this gradation display, each output of the liquid crystal driver has a built-in DA converter, and a gradation voltage is output from each DA converter. Hereinafter, this operation will be specifically described.

  FIG. 6 shows a block diagram of a general liquid crystal driver. In FIG. 6, image data corresponding to each output of the output amplifier 6 (6 bits or more per output) is sequentially sampled by the sampling memory 2 based on the output from the shift register 1, and data corresponding to the number of outputs is held. The data is fetched and latched in the memory 3 and output to the DA converter 5 via the level shifter 4. In the DA converter 5, the gradation voltage generated by the reference voltage generation circuit 7 composed of a ladder resistor is selected for each output, and each gradation is passed through an output amplifier 6 having an operational amplifier provided for each output. Output voltage.

  FIG. 8 shows a ladder resistor as the reference voltage generating circuit 7. Generally, a desired gradation voltage for each gradation is generated by dividing the ladder resistance. Regarding the above image data, 64 gradation display is possible with a 6-bit DA converter, 256 gradation display is possible with an 8-bit DA converter, and 1024 gradation display is possible with a 10-bit DA converter. It is.

  As the number of gradations of the liquid crystal driver LSI increases, high-precision measurement is indispensable for testing the liquid crystal driver LSI to ensure image quality. That is, whether or not each gradation voltage value output from the DA converter 5 is a correct voltage, or is the voltage value of the same gradation output from each output terminal of the DA converter 5 uniform? It is necessary to test whether or not more accurately.

  If the power supply voltage of the device under test is the same, the output terminal performance is improved from 64 gradations to 256 gradations, so that the measurement accuracy needs to be increased four times.

  In the following, a device under test to be tested has a number m of output terminals, and each output terminal has a liquid crystal driver incorporating an n-gradation DA converter for selecting and outputting n voltage levels. A conventional test method will be described with reference to an example of an LSI for use.

  FIG. 5 is a diagram showing a schematic configuration of a semiconductor test apparatus that performs a gradation test using a high-precision voltmeter. The semiconductor test apparatus (tester) 12 inputs a predetermined input signal to the device under test (DUT) 11 and determines the quality of the signal output from the DUT 11. That is, the tester 12 supplies a predetermined input signal to a DUT (Liquid Crystal Driver LSI) 11 to output a voltage at the first gradation level. Then, using the high-precision analog voltage measuring device 13 built in the tester 12, the gradation voltage value of the first gradation is sequentially measured for each output terminal from the first output terminal Y1 to the m-th output terminal Ym, The measurement results are sequentially stored in the data memory 14 built in the tester 12. This operation is repeated for n gradations, and finally, data for all output terminals and all gradations are stored in the data memory 14. As a result, data corresponding to (m × n) output states is stored in the data memory 14.

  Next, the data (grayscale voltage value) stored in the data memory 14 is sent to the arithmetic unit 15 built in the tester 12, and a predetermined calculation is performed by the arithmetic unit 15 so that each output terminal Y The difference between the gradation voltage values and the variation (uniformity) of the gradation voltage values between the output terminals Y are determined. That is, as shown in FIG. 10, the arithmetic unit 15 calculates how much the measured value of the output voltage from each of the output terminals Y1 to Ym deviates from the ideal voltage value (gradation deviation). The difference between the upper limit value (MAX value) and the lower limit value (MIN value) of the measured value is calculated (uniformity).

  In such a liquid crystal driver test, it is necessary to measure the gradation voltage value with higher accuracy as the number of gradations increases. However, it is not unusual for a liquid crystal driver to have an output terminal of about 500 pins, and it takes a long time to measure the DC of each output terminal. Therefore, the analog test method is applied in the case of a mass production test. It has a problem that it is difficult.

  Therefore, in the “IC test apparatus” disclosed in Japanese Patent Laid-Open No. 10-2937 (Patent Document 1), a comparator for comparing the output level of the output terminal under test in the analog test with a predetermined upper limit value and lower limit value. The analog test problem is solved by comparing the digital data as the output result of these comparators with the expected value. However, there are still the following problems.

  That is, in order to pursue a high-quality image, the number of gradation bits of the device for driving the image display apparatus is increasing year by year, and the level change of the output level is becoming very small. Therefore, it is difficult for the comparator in the IC test apparatus of Patent Document 1 to detect a level change of the output level. In the case of a liquid crystal driver as an example, the specifications prescribed for the deviation voltage ΔV (see FIG. 11) between the ideal output voltage of the device under test and the actual output voltage and the variation (uniformity) between output terminals are more stringent. In general, it is ± 20 mV or less in the 64 gradation specification, and ± 10 mV or less in the 256 gradation specification, and is becoming several mV or less as the number of gradations further increases.

  Some liquid crystal drive devices can control the output level with a 10-bit gradation with respect to a 5 V power supply. In this case, it is necessary to measure the output of 5 mV from the gradation unit with high accuracy. However, a test apparatus equipped with a high-precision DC unit capable of measuring an output of 5 mV with high accuracy is expensive, and cannot be introduced into a mass-production device test apparatus.

  From the above, when it is conventionally necessary to screen a device including an analog circuit with high accuracy, for example, when it is used for a large-screen liquid crystal display device in which 10 or more liquid crystal driving devices are used, When used in an in-vehicle liquid crystal display device that requires higher display quality than usual, there is a problem that it is difficult to satisfy the display quality desired by the user. Therefore, it is required for devices used for such applications to ensure higher shipping quality than before in the mass production stage.

  Therefore, in order to compensate for the above-mentioned test items of gradation voltage deviation and uniformity, functional tests of basic operations and tests of items such as operation margins such as AC characteristics, current consumption and delay time are performed. .

  In the test of a semiconductor integrated circuit, a test of a minute leakage current on the order of several μA is an important factor. By performing a test of such a minute leakage current on the order of several μA, the operation is within the normal range, but a potential failure mode (for example, interference between internal wirings or some defect in the transistor (gate oxidation) It is also possible to screen for defects in the reliability mode) that may cause defects in the future.

  In a large-scale logic LSI test, a leak test that measures a minute power supply current can obtain a high screening effect even if the quality test cannot be ensured by a functional test using a test pattern for detecting a functional failure. It is popular. In a CMOS LSI, the leakage current value is usually approximately 0, but does not become 0 if there is an abnormality. Therefore, a defective device can be detected by measuring the leakage current. One of the leakage current measurements is the IDDQ test.

  As a prior art for measuring a power supply current in a stationary state, for example, “Semiconductor integrated circuit device and its test method” disclosed in Japanese Patent Laid-Open No. 5-273298 (Patent Document 2) or Japanese Patent Laid-Open No. 6-58981 (Patent Document) There is a “CMOS integrated circuit current detection circuit” disclosed in the literature 3). In Patent Document 2, a measurement circuit is configured outside a CMOS semiconductor integrated circuit, and the measurement circuit is built in the same semiconductor substrate. As described above, various IDDQ test techniques have been proposed.

However, in the IDDQ test apparatus that detects the abnormal value of the minute power supply current as described above, a device including a large number of analog circuit portions through which a large power supply current caused by a direct current component flows even in a normal state, for example, a liquid crystal driving device However, there is a problem that the screening effect cannot be increased in principle.
Japanese Patent Laid-Open No. 10-2937 JP-A-5-273298 JP-A-6-58981

  SUMMARY OF THE INVENTION An object of the present invention is to provide a test method for a semiconductor integrated circuit that can obtain a high screening effect even in a semiconductor integrated circuit including an analog circuit portion through which a power supply current flows even under normal conditions.

In order to solve the above problems, a method for testing a semiconductor integrated circuit according to the present invention includes:
The first current consumption of the entire semiconductor integrated circuit when the output state of the semiconductor integrated circuit having a plurality of output terminals should be in the first state, the output state of the semiconductor integrated circuit is the first state, and Measuring the second current consumption of the entire semiconductor integrated circuit when it should be in the second state in the first relationship or the second relationship;
The difference value between the value of the first consumption current and the value of the second consumption current when the semiconductor integrated circuit is normal has a specific value,
Detecting a defect of the semiconductor integrated circuit based on a comparison result between a difference value between the first consumption current value and the second consumption current value and a reference value determined in advance based on the specific value. It is characterized by.
The first relationship is the first state, the stress application to be applied to the semiconductor integrated circuit a high current or voltage than the current or voltage is applied at the time of driving, activate the inside of the semiconductor integrated circuit A relationship that is a previous state and the second state is a state after the activation of the inside of the semiconductor integrated circuit is completed.
The second relationship is the first state, the output voltage from each output terminal, n1 (n1 is a natural number) is different from n2 (n2 is this n1 th gradation and gradation voltage gradation th Natural number) gradation voltages of gradations are arranged in a predetermined order, and the second state is the output voltage from each of the output terminals of the two gradation voltages in the first state. A relationship in which the grayscale voltage is different from that in the first state.

According to the configuration, the first consumption current when the output state of the semiconductor integrated circuit should be in the first state, and the second state in the first relationship or the second relationship with the first state. Since the defect of the semiconductor integrated circuit is detected based on the difference value with the second consumption current when it should be in the state, the malfunction of the semiconductor integrated circuit and the internal circuit of the semiconductor integrated circuit is detected by the consumption current. be able to.

  In that case, since the first and second current consumption values are each in the order of mA, even if there is a potential defect of a transistor scale leading to a failure in the future, the fluctuation of the current value caused by the potential defect Is buried in a current value in the order of mA, and it is difficult to find the defect directly from the current consumption value. However, in the present invention, since the determination is based on the difference value of each consumption current value, the difference value between the first consumption current value and the second consumption current value when the semiconductor integrated circuit is normal is approximately. If it is 0, the difference value is on the order of μA, and it becomes possible to detect a change in current caused by the potential defect.

  Further, by taking the difference value between the first and second current consumption values, the fluctuation amount of the current consumption due to the characteristics of the semiconductor integrated circuit and the measurement environment of the semiconductor integrated circuit (effect of contact state, etc.) is taken into consideration. It is possible to make the determination under the same conditions. Therefore, determination on the order of μA is possible. Furthermore, since it is not necessary to consider the amount of fluctuation in current consumption due to the measurement environment, it is possible to make a determination even for an analog circuit in which a power supply current flows even under normal conditions. Therefore, even if the internal circuit of the semiconductor integrated circuit is an analog circuit, it is possible to detect a defect on the order of μA.

In the semiconductor integrated circuit test method of one embodiment,
When the semiconductor integrated circuit is normal, the difference value between the first consumption current value and the second consumption current value is approximately zero.

  Here, the “substantially 0” includes a case of “0” and a case of “within ± 1 mA”.

According to this embodiment, when the semiconductor integrated circuit is normal, the difference value between the first consumption current value and the second consumption current value is approximately zero. Therefore, the difference value is on the order of μA, and a change in current caused by the potential defect can be detected .

Also, the first state and the relationship between the second states, the first state, the stress applied to a high current or voltage than the current or voltage is applied during drive is applied to the semiconductor integrated circuit Accordingly, the state before activating the internal semiconductor integrated circuit, the second state, by an internal with respect to which the first state after the completion of the activation relationship of the semiconductor integrated circuit In particular, it is possible to detect a potential defect on a transistor scale that can be normally operated at present but will cause a failure in the future. Therefore, it is possible to detect a defect related to reliability.

In the semiconductor integrated circuit test method of one embodiment,
The semiconductor integrated circuit is configured to switch and output a multi-gradation voltage from each output terminal,
The relationship between the first state and the second state is the second relationship.

  According to this embodiment, it is possible to detect a malfunction of a semiconductor integrated circuit that switches and outputs a multi-gradation voltage and an internal circuit (particularly, an output amplifier) of the semiconductor integrated circuit based on current consumption.

In the semiconductor integrated circuit test method of one embodiment,
The arrangement order of the gradation voltage of the n1 gradation and the gradation voltage of the n2 gradation in the first state are alternate.

  According to this embodiment, the arrangement of the gradation voltage of the n1 gradation and the gradation voltage of the n2 gradation in the first state is a staggered state, while the arrangement in the second state is Becomes the reverse staggered state. Therefore, the first state and the second state can be easily set.

Further, a method for testing a product equipped with the semiconductor integrated circuit of the present invention is
The first current consumption of the entire product when the output state of the product on which the semiconductor integrated circuit is mounted should be in the first state, and the output state of the product is the first relationship and the first relationship or and the entire product of the second current consumption of time to in a second state in the second relationship is measured,
The difference value between the value of the first current consumption and the value of the second current consumption when the product is normal has a specific value,
Detecting a defect in the product based on a comparison result between a difference value between the first consumption current value and the second consumption current value and a reference value predetermined based on the specific value. It is said.
The first relationship is the first state, the stress application to be applied to the product a high current or voltage than the current or voltage is applied at the time of driving, in a state before activating the interior of the product There, the second state is a state after the completion of the above activation to the inside of the above product relationship.
The second relationship is the first state, the output voltage from the output terminal of the product, n1 (n1 is a natural number) different from the n1 th gradation and the gradation voltages of gray level n2 ( n2 is a natural number) the gradation voltages of the gradations are arranged in a predetermined order, and the second state represents the output voltage from each of the output terminals and the two gradation voltages in the first state. Among these, the relationship is a state in which the gradation voltage is different from that in the first state.

  According to the above configuration, as in the case of the test method of the semiconductor integrated circuit, the product, the semiconductor integrated circuit mounted on the product, and the internal circuit of the semiconductor integrated circuit can be detected by current consumption. it can. In that case, it is possible to detect a change in current due to a potential transistor-scale defect that will lead to a failure in the future. Further, without considering the characteristics of the semiconductor integrated circuit and the amount of change in current consumption due to the measurement environment of the semiconductor integrated circuit (effect of contact state, etc.), the internal circuit of the semiconductor integrated circuit is an analog circuit. However, it is possible to detect defects on the order of μA.

Further, in a test method for a product equipped with the semiconductor integrated circuit of one embodiment,
When the product is normal, the difference value between the first consumption current value and the second consumption current value is approximately zero.

  Here, the “substantially 0” includes a case of “0” and a case of “within ± 1 mA”.

According to this embodiment, since the difference value between the value of the first current consumption and the value of the second current consumption when the product is normal is approximately 0, the difference value is on the order of μA. A change in current due to the potential defect can be detected .

As is clear from the above, the semiconductor integrated circuit test method of the present invention includes the first consumption current when the output state of the semiconductor integrated circuit should be in the first state, the first state, and the following first state. Or the semiconductor integrated circuit and the semiconductor integrated circuit are detected based on the difference value from the second consumption current when the second state is to be in the second state or the second relationship. Can be detected by current consumption.
The first relationship is the first state, the stress application to be applied to the semiconductor integrated circuit a high current or voltage than the current or voltage is applied at the time of driving, activate the inside of the semiconductor integrated circuit A relationship that is a previous state and the second state is a state after the activation of the inside of the semiconductor integrated circuit is completed.
The second relationship is the first state, the output voltage from each output terminal, n1 (n1 is a natural number) is different from n2 (n2 is this n1 th gradation and gradation voltage gradation th Natural number) gradation voltages of gradations are arranged in a predetermined order, and the second state is the output voltage from each of the output terminals of the two gradation voltages in the first state. A relationship in which the grayscale voltage is different from that in the first state.

  Further, since the determination is based on the difference value between the first and second consumption current values, if the difference value between the both consumption current values when the semiconductor integrated circuit is normal is approximately 0, the difference value is On the order of μA, it becomes possible to detect a change in current due to the potential defect.

  Further, by taking the difference between the first and second consumption current values, the fluctuation amount of the consumption current due to the characteristics of the semiconductor integrated circuit and the measurement environment of the semiconductor integrated circuit (effect of contact state, etc.) is taken into consideration. It is possible to make the determination under the same conditions. Therefore, determination on the order of μA is possible.

  Furthermore, since it is not necessary to consider the amount of fluctuation in current consumption due to the measurement environment, it is possible to make a determination even for an analog circuit in which a power supply current flows even under normal conditions. Therefore, even if the internal circuit of the semiconductor integrated circuit is an analog circuit, it is possible to detect a defect on the order of μA.

According to another aspect of the present invention, there is provided a method for testing a product on which a semiconductor integrated circuit is mounted. The first consumption current when the output state of the product on which the semiconductor integrated circuit is mounted should be in the first state; Since the defect of the product is detected based on the difference value between the first state and the second consumption current when the second state should be in the first relationship or the second relationship described below, the semiconductor As in the case of the integrated circuit test method, it is possible to detect malfunctions in the product, the semiconductor integrated circuit mounted in the product, and the internal circuit of the semiconductor integrated circuit based on current consumption.
The first relationship is the first state, the stress application to be applied to the product a high current or voltage than the current or voltage is applied at the time of driving, in a state before activating the interior of the product There, the second state is a state after the completion of the above activation to the inside of the above product relationship.
The second relationship is the first state, the output voltage from the output terminal of the product, n1 (n1 is a natural number) different from the n1 th gradation and the gradation voltages of gray level n2 ( n2 is a natural number) the gradation voltages of the gradations are arranged in a predetermined order, and the second state represents the output voltage from each of the output terminals and the two gradation voltages in the first state. Among these, the relationship is a state in which the gradation voltage is different from that in the first state.

  Furthermore, it is possible to detect changes in current due to potential defects on the transistor scale that will lead to failure in the future. Further, without considering the characteristics of the semiconductor integrated circuit and the amount of change in current consumption due to the measurement environment of the semiconductor integrated circuit (effect of contact state, etc.), the internal circuit of the semiconductor integrated circuit is an analog circuit. However, it is possible to detect defects on the order of μA.

  That is, according to these inventions, the shipping quality level of the semiconductor integrated circuit and the product on which the semiconductor integrated circuit is mounted can be remarkably improved as compared with the prior art.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. In the present embodiment, a test method for a semiconductor integrated circuit according to the present invention will be described by taking a multi-tone / multi-output liquid crystal driver incorporating a DA converter as an example.

  FIG. 6 is a block diagram of a general liquid crystal driver. FIG. 7 shows a schematic configuration of the reference voltage generation circuit 7 in FIG. 6 and a relationship between the DA converter 5 and the output amplifier 6. FIG. 8 shows a ladder resistor as the reference voltage generation circuit 7 in FIG. FIG. 9 shows each gradation voltage generated by the reference voltage generation circuit 7 shown in FIG. The configuration and operation of the liquid crystal driver shown in FIG. 6 are as described in [Background Art].

  FIG. 5 shows a schematic configuration of a semiconductor test apparatus (tester) that executes the test method according to the present embodiment for the liquid crystal driver shown in FIGS. The configuration and operation of the semiconductor test apparatus shown in FIG. 5 are as described in the above [Background Art].

  By the way, as described in the above [Background Art], in the case of a CMOS LSI, the leakage current value is normally approximately 0, but does not become 0 if there is an abnormality. Therefore, a defective device can be detected by measuring the leakage current. However, in the case of a liquid crystal driver, since an operational amplifier is mounted as an analog circuit in the output circuit, a bias current constantly flows and a current on the order of several mA flows even in a stationary state. For this reason, it is impossible to measure a minute current that is performed in the large-scale logic LSI or the like.

  Therefore, in the present embodiment in which the device under test is a “liquid crystal driver”, the following test is performed as a test added to the measurement of the minute leak current performed in the case of the CMOS LSI.

  The liquid crystal driver shown in FIG. 6 can be divided into a logic system (sampling memory 2 and hold memory 3) and a medium withstand voltage system (DA converter 5 and output amplifier 6) before and after the level shifter 4 and is supplied to each. The power supply system is different. As described above, since the operational amplifier is built in the output amplifier 6 that is a medium withstand voltage system circuit, a bias current constantly flows, and the quiescent current of the medium withstand voltage system power supply is a current on the order of several mA. Therefore, the change of the quiescent current due to the minute leak current is buried in the fluctuation due to other causes. For this reason, it is impossible to measure a minute leak current in the medium withstand voltage system circuit, and it is impossible to screen for defects including potential failure factors. In the circuit block of the liquid crystal driver shown in FIG. 6, generally about 60% of the number of transistors is in the medium voltage system block.

  Therefore, by focusing on this medium voltage system circuit, the output state of the medium voltage system circuit is set to the first state and the second state. In this case, if the current consumption in the first state and the second state is theoretically the same (actually measured values are within an allowable range of ± 1 mA), the first of the medium withstand voltage circuits is the first. When there is a potential failure factor in a circuit (such as a transistor) that generates one state, the current consumption value in the first state is larger than the current consumption value in the second state. Therefore, a difference value between the current consumption value in the first state and the current consumption value in the second state is obtained by the arithmetic unit 15 of the gradation test apparatus, and compared with a reference value, for example, to thereby output the amplifier 6. Thus, it is possible to screen for potential defects in units of circuit blocks such as operational amplifiers constituting the output amplifier 6.

  Hereinafter, a liquid crystal driver to which 6-bit image data is input will be described in detail. Input data (6 bits per output) corresponding to each output of the output amplifier 6 is input from the tester 12 shown in FIG. Then, the input data is sequentially sampled by the sampling memory 2, the data corresponding to the number of outputs is fetched into the hold memory 3, latched, and input to the DA converter 5 via the level shifter 4. In the DA converter 5, the gradation voltage generated by the reference voltage generation circuit 7 is selected for each output based on the input data, and each gradation is output via an output amplifier 6 having an operational amplifier provided for each output. Output voltage. For example, if the input data is # 00 (6 bits), the gradation voltage of the 0th gradation is assumed, and if the input data is # 3F (6 bits), the gradation voltage of the 63rd gradation is output from the output amplifier 6. Output from the terminal.

  Therefore, in this embodiment, taking the above-described operation and the state of each circuit block into consideration, the first level, for example, as the input data for the odd-numbered output terminals of the output amplifier 6, the maximum level gradation voltage ( Input data “# 3F” for outputting the gradation voltage of the 63rd gradation) is input. On the other hand, a state in which input data “# 00” for outputting the minimum level gradation voltage (the gradation voltage of the 0th gradation) is input as input data to the even-numbered output terminals is set. As a result, the output state of the output amplifier 6 becomes a staggered state as shown in FIG. On the other hand, as the second state, contrary to the first state, the input data “# 00” that outputs the gradation voltage of the 0th gradation as the input data to the odd-numbered output terminal of the output amplifier 6. ". On the other hand, a state in which input data “# 3F” for outputting the gradation voltage of the 63rd gradation is input as input data for the even-numbered output terminals is set. Then, the output state of the output amplifier 6 becomes an inverted staggered state as shown in FIG. Then, by measuring the value of each power supply current (current consumption of the entire liquid crystal driver) in the first state and the second state, and comparing and verifying the difference value of the current value with the reference value, Potential defects (transistor level defects that are normal in operation but have minor leakage) can be screened indirectly.

  FIG. 3 shows a change in the output voltage of the output amplifier 6 in the zigzag state (first state) and the reverse zigzag state (second state) when two ladder resistors for 256 gradations are used as shown in FIG. Indicates. In this case, in the first state, for example, the output voltage from the odd-numbered output terminal of the output amplifier 6 is the gradation voltage of the 0th gradation from the ladder resistance on the low voltage side of the two ladder resistances. Select. On the other hand, as the output value from the even-numbered output terminal, the gradation voltage of the 0th gradation from the ladder resistor on the high voltage side of the two ladder resistors is selected. On the other hand, in the second state, the gradation voltage of the 0th gradation from the ladder resistor on the high voltage side is selected as the output value from the odd-numbered output terminal. On the other hand, as the output value from the even-numbered output terminal, the gradation voltage of the 0th gradation from the ladder resistor on the low voltage side is selected.

  As described above, in this embodiment, an array pattern of two output voltages from each output terminal of the output amplifier 6 is used as the output state, and the predetermined relationship between the first state and the second state is: The arrangement pattern of the two output voltages is opposite to each other. Specifically, the output signal is obtained by inverting the order of voltage levels of the output signals from the output amplifier 6 to set the staggered state (first state) and the reverse staggered state (second state). It is possible to detect the malfunction of the output amplifier 6 that generates and the operational amplifier in the output amplifier 6.

  In this embodiment, the order of arrangement of the maximum level gradation voltage and the minimum level gradation voltage is reversed, but the maximum / minimum level gradation voltage is not necessarily required. May be two gradation levels having the same voltage difference. Further, the arrangement order of the two voltage levels is not limited to one output terminal but may be a plurality of output terminals.

  In this embodiment, the voltage value output from the output terminal of the output amplifier 6 of the liquid crystal driver and the arrangement pattern thereof are used as the first state and the second state. However, the present invention is not limited to this, and the first and second states may be output states of the semiconductor integrated circuit having a predetermined relationship with each other.

  Next, another embodiment in which the state of the medium withstand voltage circuit is set to the first state and the second state will be described.

  In this embodiment, considering the inversion of the state in the internal circuit of the 6-bit input liquid crystal driver, as the first state, the input data corresponding to the output from the odd-numbered output terminal of the output amplifier 6 is “# “15” is input while each bit of “# 15” is inverted as input data corresponding to the output from the even-numbered output terminal, that is, “# 2A” is in the relationship of “1” and “# 2A”. ”Is set. On the other hand, as the second state, “# 2A” is input as input data corresponding to the output from the odd-numbered output terminal of the output amplifier 6. On the other hand, as the input data corresponding to the output from the even-numbered output terminal, each bit of “# 2A” is inverted, that is, “# 15” that is in the relationship of “# 2A” and 1's complement is input. Set. Then, by measuring the values of the respective power supply currents in the first state and the second state and comparing and verifying the difference value between the current values and the reference value, it is possible to make a determination on the order of μA. As a result, a test equivalent to the measurement of a minute leak can be realized, and potential defects existing in the circuit can be screened indirectly.

  FIG. 4 shows a change in the output voltage of the output amplifier 6 in the first state and the second state when two ladder resistors for 256 gradations are used as shown in FIG. In this case, in the first state, as input data corresponding to the output from the odd-numbered output terminal of the output amplifier 6, for example, “# 00” for the ladder resistor on the low voltage side of the two ladder resistors. ". On the other hand, as input data corresponding to the output from the even-numbered output terminal, a state in which “# 00” is input for the ladder resistor on the high voltage side of the two ladder resistors is set. Thus, the output state of the output amplifier 6 is set to the staggered state. On the other hand, in the second state, as input data corresponding to the output from the odd-numbered output terminal, “# 00” and “1's complement” are used for the low-voltage side ladder resistor “#”. Enter “3F”. On the other hand, as the input data corresponding to the output from the even-numbered output terminal, a state where “# 3F” is input for the ladder resistor on the high voltage side is set. Then, the output state of the output amplifier 6 becomes a staggered state in which the output level change width is small.

  As described above, in this embodiment, the input data corresponding to the second state is set to have a one's complement relationship with the input data corresponding to the first state. In this way, by inverting each bit of the input data to set the first state and the second state, it is possible to detect a malfunction of the DA converter 5 and the level shifter 4 that are mainly controlled by the input data. is there.

  Next, another embodiment in which the state of the medium withstand voltage circuit is set to the first state and the second state will be described.

  In this embodiment, first, the liquid crystal driver in a stationary state is set to the first state. Next, the inside of the liquid crystal driver is activated by applying a stress that applies a current or voltage higher than the current or voltage applied to the liquid crystal driver during driving. Then, the liquid crystal driver in a stationary state after the activation is finished is set to the second state. In this way, the first state and the second state are set depending on the presence or absence of external factors such as before and after the activation of the inside of the liquid crystal driver. Then, by comparing and verifying the differential current value and the reference value in the first state and the second state, a malfunction of the liquid crystal driver is detected. Therefore, it is possible to detect a potential defect on a transistor scale that can be normally operated at present but will cause a failure in the future.

  In other words, according to this embodiment, it is possible to detect a defect related to the reliability of the liquid crystal driver, and it is possible to significantly improve the shipping quality.

  The reference value for comparison with the differential current value in each of the above embodiments is set to an optimum value from statistical data in consideration of the ability value of the device under test, the measurement accuracy of the measuring device, and the like. When applied to the liquid crystal driver, the distribution data of the differential current values of a plurality of liquid crystal drivers is totaled, and an optimum reference value is extracted from the total value.

As described above, in the present embodiment, the state of the input signal or the state of the output signal in the device under test such as the liquid crystal driver is divided into two states, the first state and the second state opposite to the first state. The test is performed by comparing and verifying the difference value of the current consumption value in these two states and the reference value. Therefore, the following effects can be achieved.
(1) When the current consumption in the first state and the current consumption in the second state are substantially equal because the determination is based on the difference between the current consumption values in the first state and the second state. Even if the current consumption level is in the order of mA, the difference value is in the order of μA, and a change in current due to the potential defect can be detected.
(2) Since the determination is based on the difference between the current consumption values in two different states of the same device under test, even if the current value fluctuates depending on the characteristics of the device under test, the measurement conditions, and the ambient temperature, It becomes constant. Therefore, the influence on the determination result of the fluctuation can be suppressed. That is, according to the test method in the present embodiment, there is no influence of device characteristics, measurement conditions, environmental temperature, etc. of the device under test.
(3) Since it is not necessary to consider the amount of fluctuation in current consumption due to the measurement environment, it is possible to make a determination even for an analog circuit in which a power supply current flows even under normal conditions. Therefore, even when the internal circuit is an analog circuit such as the output amplifier 6 of the liquid crystal driver, it is possible to detect a defect on the order of μA.
(4) When the device under test is a liquid crystal driver, the two states are different depending on only the state of the operational amplifier built in the output amplifier 6, as shown in FIGS. By setting the state of the output signal to be different, it is possible to screen the operational amplifier for defects (defects at the transistor level) with a minute leak current.

  The defects that can be screened in this case include a gate oxide film defect, an inter-wiring interference defect, a P-type N-type region etching defect, a foreign matter defect on the gate electrode, a gate electrode shape abnormality, and a pattern defect. Further, specific examples of the pattern defect include a step generated from the P-type region pattern or the N-type region pattern to the surrounding LOCOS region, a defect generated in the contact portion of the P-type region pattern or the N-type region pattern, and the like. Any of these is a potential defect that is within the normal range in terms of operation but may possibly become a failure in the future.

  In the present embodiment, the liquid crystal driver has been described as an example of the semiconductor integrated circuit to be tested. However, according to the present invention, as long as the first state and the second state can be set so that the current consumption is substantially equal to each other in an output state in which each other is in a predetermined relationship, The present invention can also be applied to a semiconductor integrated circuit or a product on which the semiconductor integrated circuit is mounted, and its application range is wide.

  For example, as an example applied to a liquid crystal panel that is a product equipped with the liquid crystal driver, the first state in which all pixels of the liquid crystal display panel are all displayed in red and the second state in which blue display or green display is performed. By comparing and verifying the difference value of the consumption current value with the reference value, it is possible to detect a defect of the mounted component or the mounted substrate.

It is explanatory drawing of the 1st state in the test method of the semiconductor integrated circuit of this invention. It is explanatory drawing of the 2nd state following FIG. It is a figure which shows the example of a change of the output level in a zigzag state (1st state) and a reverse zigzag state (2nd state). It is a figure which shows the example of a change of the output level in the test method different from FIG. It is a figure which shows schematic structure of the semiconductor test apparatus (tester) which performs the test method shown in FIGS. It is a block diagram of a liquid crystal driver. FIG. 7 is a diagram illustrating a schematic configuration of a reference voltage generation circuit in FIG. 6 and a relationship between a DA converter and an output amplifier. It is a figure which shows the ladder resistance as a reference voltage generation circuit in FIG. It is a figure which shows each gradation voltage produced | generated by the reference voltage generation circuit shown in FIG. It is explanatory drawing of the conventional gradation test. It is a figure which shows the deviation voltage of the ideal output voltage of a to-be-tested device, and an actual output voltage.

1 ... shift register,
2 ... Sampling memory,
3 ... Hold memory,
4 Level shifter,
5 ... DA converter,
6 ... Output amplifier,
7: Reference voltage generation circuit,
11: Device under test (DUT),
12. Semiconductor test equipment (tester)
13 ... High-precision analog voltage measuring instrument,
14: Data memory,
15: Arithmetic unit.

Claims (6)

The first current consumption of the entire semiconductor integrated circuit when the output state of the semiconductor integrated circuit having a plurality of output terminals should be in the first state, the output state of the semiconductor integrated circuit is the first state, and Measuring the second current consumption of the entire semiconductor integrated circuit when it should be in the second state in the first relationship or the second relationship;
The difference value between the value of the first consumption current and the value of the second consumption current when the semiconductor integrated circuit is normal has a specific value,
Detecting a defect of the semiconductor integrated circuit based on a comparison result between a difference value between the first consumption current value and the second consumption current value and a reference value determined in advance based on the specific value. A test method for semiconductor integrated circuits.
The first relationship is the first state, the stress application to be applied to the semiconductor integrated circuit a high current or voltage than the current or voltage is applied at the time of driving, activate the inside of the semiconductor integrated circuit A relationship that is a previous state and the second state is a state after the activation of the inside of the semiconductor integrated circuit is completed.
The second relationship is the first state, the output voltage from each output terminal, n1 (n1 is a natural number) is different from n2 (n2 is this n1 th gradation and gradation voltage gradation th Natural number) gradation voltages of gradations are arranged in a predetermined order, and the second state is the output voltage from each of the output terminals of the two gradation voltages in the first state. A relationship in which the grayscale voltage is different from that in the first state. The method of testing a semiconductor integrated circuit according to claim 1,
A test method for a semiconductor integrated circuit, wherein a difference value between the first consumption current value and the second consumption current value when the semiconductor integrated circuit is normal is substantially zero. The method of testing a semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit is configured to switch and output a multi-gradation voltage from each output terminal,
A test method for a semiconductor integrated circuit, wherein the relationship between the first state and the second state is the second relationship. The method for testing a semiconductor integrated circuit according to claim 3,
A test method for a semiconductor integrated circuit, wherein the arrangement order of the gradation voltage of the n1 gradation and the gradation voltage of the n2 gradation in the first state is alternate. The first current consumption of the entire product when the output state of the product on which the semiconductor integrated circuit is mounted should be in the first state, and the output state of the product is the first relationship and the first relationship or and the entire product of the second current consumption of time to in a second state in the second relationship is measured,
The difference value between the value of the first current consumption and the value of the second current consumption when the product is normal has a specific value,
Detecting a defect in the product based on a comparison result between a difference value between the first consumption current value and the second consumption current value and a reference value predetermined based on the specific value. Test method for products equipped with semiconductor integrated circuits.
The first relationship is the first state, the stress application to be applied to the product a high current or voltage than the current or voltage is applied at the time of driving, in a state before activating the interior of the product There, the second state is a state after the completion of the above activation to the inside of the above product relationship.
The second relationship is the first state, the output voltage from the output terminal of the product, n1 (n1 is a natural number) different from the n1 th gradation and the gradation voltages of gray level n2 ( n2 is a natural number) the gradation voltages of the gradations are arranged in a predetermined order, and the second state represents the output voltage from each of the output terminals and the two gradation voltages in the first state. Among these, the relationship is a state in which the gradation voltage is different from that in the first state. In a method for testing a product equipped with the semiconductor integrated circuit according to claim 5,
A test method for a product on which a semiconductor integrated circuit is mounted, wherein a difference value between the value of the first current consumption and the value of the second current consumption when the product is normal is approximately zero.

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