JP2011015259A - Semiconductor integrated circuit device and method for testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently exclude an initial defect.SOLUTION: A semiconductor integrated circuit device includes: terminals 11a and 11m; first to (2n+1)th resistive elements ((n) is an integer of at least 1) (resistive element group 12) connected in series between the terminals 11a and 11m; a selection circuit 14 selecting, assuming that a terminal 11a connected to one end of the first resistive element is a 0th node, a terminal 11m connected to the other end of the (2n+1)th resistive element is a (2n+1)th node, and a connection point of the other end of an (i)th resistive element ((i) is an integer from 1 to 2n) and one end of an (i+1)th resistive element is an (i)th node, any one of the 0th to (2n+1)th nodes and outputting a voltage applied to the selected node; a switch group 15a which can short-circuit any (2k)th node ((k) is an integer from 0 to n); and a switch group 15b which can short-circuit any (2k+1)th node. The (2k)th and (2k+1)th nodes are all short-circuited, and subsequently, a predetermined voltage is temporarily applied between the terminals 11a and 11m.

Description

  The present invention relates to a semiconductor integrated circuit device and a test method therefor, and more particularly to a test circuit and a test method for a semiconductor integrated circuit device having a D / A conversion function configured by a resistor divider circuit.

  A multi-gradation liquid crystal driver IC having a built-in D / A converter (DAC) has a DAC for every liquid crystal drive output terminal, and according to a multi-bit digital signal that is input multi-gradation data. The analog voltage is output from each liquid crystal drive output terminal. For this reason, the inspection of the multi-tone liquid crystal driver IC incorporating the DAC measures and determines the analog voltage output from all the DACs. Such a driver IC inspection requires measurement with a highly accurate analog voltage measuring instrument.

  Therefore, instead of measuring with a high-accuracy analog voltage measuring device, it is possible to make a digital judgment with a comparator, a semiconductor integrated circuit that can greatly reduce the inspection time and perform high-precision inspection by using an inexpensive digital inspection device An apparatus is disclosed in Patent Document 1. In this semiconductor integrated circuit device, at least two reference power supply voltage input terminals, a resistance dividing circuit for dividing the voltage between the reference power supply voltage input terminals to generate an intermediate voltage, and an input digital signal, A D / A converter including a switch circuit for selecting and outputting one voltage from the reference power supply voltage and the intermediate voltage is built in, and the output voltage of the D / A converter is supplied from its output terminal. It is set as the structure to output. Then, switch means for partially short-circuiting a part of the resistance dividing circuit is provided. According to such a semiconductor integrated circuit device, the potential difference between the output voltages to be inspected can be increased, and digital determination by the comparator is possible.

JP 2000-165244 A

  The following analysis is given in the present invention.

  By the way, in general, an LCD driver is laid out so that wirings of a potential divided by a resistance dividing circuit run in parallel over a long distance. Considering the lifetime of the LCD driver having such a configuration, it is desirable that the voltage of the adjacent wiring is low. However, when screening is performed to eliminate initial defects, it is required to apply a sufficiently high voltage between adjacent wirings.

  The conventional semiconductor integrated circuit device has a function of applying a voltage between adjacent wirings to obtain a screening effect, although the potential difference between adjacent wirings is enlarged as a means for facilitating the test, in order to increase the gradation potential difference. Not. Therefore, effective screening cannot be performed and initial defects cannot be efficiently eliminated.

  A semiconductor integrated circuit device according to one aspect (side surface) of the present invention includes first and second terminals, and first to second n + 1 (n is 1 or more) that connects the first and second terminals in series. The first terminal to which one end of the first resistance element is connected is defined as the 0th node, and the second terminal to which the other end of the 2n + 1th resistance element is connected is defined as the 2n + 1th resistance element. A connection point between the other end of the i-th (i = 1 to 2n) resistance element and one end of the (i + 1) th resistance element is the i-th node, and any one of the 0th to (2n + 1) th nodes is the node A selection circuit enabling selection and output; a first switch group capable of short-circuiting all nodes of the 2k (k = 0 to n); and a second switch capable of short-circuiting all of the 2k + 1 nodes. A switch group.

  According to another aspect (side surface) of the present invention, a semiconductor integrated circuit device testing method includes first and second terminals, and first to second n + 1 (n) connecting the first and second terminals in series. Is an integer greater than or equal to 1), a first terminal to which one end of the first resistance element is connected is defined as a 0th node, and a second terminal to which the other end of the 2n + 1th resistance element is connected. , The connection point between the other end of the i-th (i = 1 to 2n) resistance element and the one end of the i + 1-th resistance element is the i-th node, and the 0th to 2n + 1-th node A method of testing a semiconductor integrated circuit device that enables output by selecting any one of the nodes, wherein all 2k (k = 0 to n) integers are short-circuited and all 2k + 1 nodes are short-circuited Step (a) for setting the state, and then the first and second terminals A step of temporarily applying a predetermined voltage to (b), and then a step of setting all of the 2k (k = 0 to n) nodes to an open state and setting all of the 2k + 1 nodes to an open state (c) ) And.

  According to the present invention, a voltage necessary for screening can be applied between adjacent wirings, and shipping quality is improved.

1 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. It is a figure which shows the layout of the semiconductor integrated circuit device based on the Example of this invention. 3 is a flowchart showing a first test method for a semiconductor integrated circuit device according to an embodiment of the present invention; It is a flowchart which shows the 2nd test method of the semiconductor integrated circuit device based on the Example of this invention.

  A semiconductor integrated circuit device according to an embodiment of the present invention includes first and second terminals (11a and 11m in FIG. 1) and first to second n + 1 (first to second n + 1) connected in series between the first and second terminals. n is an integer greater than or equal to 1) (12 in FIG. 1) and the first terminal to which one end of the first resistance element is connected is defined as the 0th node, and the other end of the 2n + 1 resistance element is connected. And the connection point of the other end of the i-th (i = 1 to 2n) resistance element and one end of the i + 1-th resistance element is the i-th node. A selection circuit (14 in FIG. 1) capable of selecting and outputting any one of the (2n + 1) th nodes, and a first switch capable of short-circuiting all the 2k (k = 0 to n) nodes Group (15a in FIG. 1) and a second switch group capable of short-circuiting all the 2k + 1 nodes It provided with 15b) in FIG. 1, a.

  In the semiconductor integrated circuit device, the first and second switch groups are preferably opened in the normal operation mode and temporarily short-circuited in the test mode.

  In the semiconductor integrated circuit device, it is preferable that a plurality of selection circuits are provided, and the corresponding wirings from the 0th to (2n + 1) th nodes are wired in parallel toward the branch points to the plurality of selection circuits.

  In the semiconductor integrated circuit device, it is preferable that the plurality of selection circuits be arranged in the output cell arrangement region below the plurality of wiring arrangement regions in the output cell arrangement region.

  In the test method of the semiconductor integrated circuit device as described above, a step (a) in which all the 2k (k = 0 to n) nodes are short-circuited and all the 2k + 1 nodes are short-circuited; A step (b) of temporarily applying a predetermined voltage between the first and second terminals, and thereafter, all the 2k (k = 0 to n) nodes are opened, and the 2k + 1 node is Step (c) in which all are opened.

  The semiconductor integrated circuit device testing method preferably further includes a step (d) of measuring electrical characteristics of the first to (2n + 1) th resistance elements after the step (c).

  In the method for testing a semiconductor integrated circuit device, a step (a0) of measuring initial electrical characteristics of the first to (2n + 1) th resistance elements before step (a) and a step (a) after step (d) Preferably, the method further includes a step (e) of comparing the measurement results of the corresponding initial electrical characteristics in a0) and (d).

  According to the test method as described above, all of the 2k (k = 0 to n) nodes are short-circuited, all of the 2k + 1 nodes are short-circuited, and then between the first and second terminals. Since a predetermined voltage is temporarily applied, a voltage necessary for screening can be applied between adjacent wirings. Therefore, effective screening can be performed, and initial defects can be efficiently eliminated.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. 1, the semiconductor integrated circuit device includes terminals 11a, 11b,... 11m, a resistance element group 12, a wiring group 13, a selection circuit 14, switch groups 15a and 15b, and an output terminal 16.

  The terminals 11a, 11b,... 11m are terminals for supplying a reference voltage source, respectively, and the resistance element group 12 is connected between the terminals 11a and 11m. The resistance element group 12 includes a large number of resistance elements connected in series, and each wiring of the wiring group 13 is wired from each connection point (node) between the resistance elements. The selection circuit 14 selects one of the wiring groups 13 by a control signal (not shown) and outputs the voltage of the selected wiring to the output terminal 16.

  Here, in the resistance element group 12, a point where the terminal 11a is connected is a node 0, and a point where the terminal 11m is connected is a node 2n + 1. In addition, the connection points in the middle of the resistance element group 12 are referred to as nodes 1, 2,. The switch group 15a can short-circuit all the 2k nodes (k = 0 to n). The switch group 15b can short-circuit all the 2k + 1 nodes.

  In the configuration as described above, when all the switch groups 15a and 15b are opened, the reference power supply is applied to the terminal 11a, and the terminal 11m is grounded, the gradation potentials obtained by dividing the reference voltage are respectively applied to the nodes 0 to 2n + 1. Appears. The selection circuit 14 functions as a D / A converter that selects one of the nodes 0 to 2n + 1 and outputs the voltage of the selected wiring to the output terminal 16.

  The terminals 11b,... 11m-1 may be in an open state. Further, a potential that appears when each resistance value of the resistance element group 12 is ideal may be applied to the terminals 11b,. In this case, the error in the D / A converter can be reduced.

  Next, an example of the layout of the semiconductor integrated circuit device will be described. FIG. 2 is a diagram showing a layout of the semiconductor integrated circuit device according to the embodiment of the present invention. 2, the semiconductor integrated circuit device includes resistance element groups 12 a and 12 b, wiring groups 13 a and 13 b, output cell arrangement regions 17 a and 17 b, and a control circuit 18.

  The control circuit 18 has a function of supplying voltage to the switch groups 15a, 15b, terminals 11a, 11b,... 11m and terminals 11a, 11b,. The resistance element groups 12 a and 12 b are the same as the resistance element group 12. The wiring groups 13a and 13b are the same as the wiring group 13, and are arranged so as to extend from the control circuit 18 to the output cell arrangement regions 17a and 17b on both sides. In the output cell arrangement regions 17a and 17b, a plurality of selection circuits 14 are arranged under the arrangement regions of the wiring groups 13a and 13b, respectively.

  FIG. 3 is a flowchart showing a first test method of the semiconductor integrated circuit device according to the embodiment of the present invention.

  In step S11, all the switch groups 15a and 15b are short-circuited (ON).

  In step S12, a voltage of, for example, 10V is applied to the terminal 11a, and the terminal 11m is grounded. Here, the application time is about 1 second, for example. These voltages and application time are set to values necessary to exclude initial failures.

  In step S13, all the switch groups 15a and 15b are opened (off).

  In step S14, the electrical characteristics of the resistance element group 12 are measured. If the electrical characteristics are out of the predetermined range, the semiconductor integrated circuit device subjected to the test is determined to be defective. Here, the measurement of electrical characteristics refers to the entire product test excluding the aging test. Specifically, a gradation test by a precision resistance measurement, a leak current test, a function test, and the like.

  As described above, according to the method of testing shown in the flowchart of FIG. 3, it is possible to determine and reliably screen a product having a problem in reliability with a small number of test steps.

  FIG. 4 is a flowchart showing a second test method of the semiconductor integrated circuit device according to the embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. 3 are steps for performing the same processing, and the description thereof is omitted.

  In step S10, the initial electrical characteristics of the resistance element group 12 are measured, and the measurement results are stored. Here, the “initial” electrical characteristics mean electrical characteristics before voltage application to the terminal in step S12 described later.

  In step S14a, the electrical characteristics of the resistance element group 12 are measured again, and the measurement results are stored.

  In step S15, the two electrical characteristics measured in step S10 and step S14a are compared. If the comparison result indicates that the distance is greater than a predetermined value, the semiconductor integrated circuit device subjected to the test is determined to be defective.

  According to the test method of the semiconductor integrated circuit device as described above, a product having a problem in reliability can be obtained by turning on all the wiring shorting switches 15a and 15b and applying the maximum voltage between adjacent wirings. Destroyed. Thereafter, all the switch groups 15a and 15b are turned off to remove defective products. In this way, by applying the maximum voltage between adjacent wirings, it is possible to destroy and remove a product that may be judged as a good product while having a problem with reliability.

  Here, in the test method shown in the flowchart of FIG. 3, whether the product determined to be defective is determined as a characteristic failure as a result of the voltage application in step S12 being deteriorated, or is an initial defective element. It is not possible to judge whether this is a product.

  On the other hand, in the test method shown in the flowchart of FIG. 4, whether the product determined to be defective is a characteristic failure as a result of deterioration due to voltage application in step S12, or originally has an initial defective element. It is possible to determine whether the product has been used. By using the discrimination result to identify the manufacturing process that has caused the product failure, it is possible to provide feedback to the manufacturing process. Thereby, it has the outstanding effect that a manufacturing yield can be improved.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

11a, 11b,... 11m Terminals 12, 12a, 12b Resistive element groups 13, 13a, 13b Wiring group 14 Selection circuit 15a, 15b Switch group 16 Output terminals 17a, 17b Output cell arrangement region 18 Control circuit

Claims (7)

First and second terminals;
First to second n + 1 (n is an integer greater than or equal to 1) resistance elements connecting the first and second terminals in series;
The first terminal to which one end of the first resistance element is connected is defined as a zeroth node, the second terminal to which the other end of the second n + 1 resistance element is coupled is defined as a second n + 1 node, The connection point of the other end of the resistance element i (i = 1 to 2n) and one end of the (i + 1) th resistance element is the i-th node,
A selection circuit capable of selecting and outputting any one of the 0th to 2n + 1 nodes;
A first switch group capable of short-circuiting all the 2k (k = 0 to n) nodes;
A second switch group capable of short-circuiting all the 2k + 1 nodes;
A semiconductor integrated circuit device comprising:   2. The semiconductor integrated circuit device according to claim 1, wherein the first and second switch groups are opened in a normal operation mode and temporarily short-circuited in a test mode. A plurality of the selection circuits are provided,
2. The semiconductor integrated circuit device according to claim 1, wherein corresponding wirings from the 0th to (2n + 1) th nodes run parallel to the branch points to the plurality of selection circuits.   4. The semiconductor integrated circuit device according to claim 3, wherein the plurality of selection circuits are arranged in an output cell arrangement region below a plurality of wiring arrangement regions in the output cell arrangement region. First and second terminals, and first to second n + 1 (n is an integer of 1 or more) resistance elements that connect the first and second terminals in series.
The first terminal to which one end of the first resistance element is connected is defined as a zeroth node, the second terminal to which the other end of the second n + 1 resistance element is coupled is defined as a second n + 1 node, The connection point of the other end of the resistance element i (i = 1 to 2n) and one end of the (i + 1) th resistance element is the i-th node,
A test method of a semiconductor integrated circuit device that enables output by selecting any one of 0th to 2n + 1 nodes,
A step (a) of setting all 2k (k = 0 to n) nodes to a short-circuited state and setting all 2k + 1 nodes to a short-circuited state;
Thereafter, a step (b) of temporarily applying a predetermined voltage between the first and second terminals;
Then, the step (c) of setting all of the 2k (k = 0 to n) nodes to the open state and setting all the 2k + 1 nodes to the open state;
A method for testing a semiconductor integrated circuit device, comprising:   6. The method for testing a semiconductor integrated circuit device according to claim 5, further comprising a step (d) of measuring electrical characteristics of the first to (2n + 1) th resistive elements after the step (c). Before the step (a), a step (a0) of measuring initial electrical characteristics of the first to 2n + 1 resistive elements;
(E) after the step (d), comparing the measurement results of the corresponding initial electrical characteristics in the steps (a0) and (d),
The method of testing a semiconductor integrated circuit device according to claim 6, further comprising:

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